JP2008263513A - Dll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence of electromagnetic radiation noise on an electronic apparatus by reducing electromagnetic radiation strength of an LSI provided with a DLL circuit. <P>SOLUTION: The DLL circuit is provided with an input circuit 101 for generating a synchronous reference signal on the basis of an input signal; a first delaying part 102 for delaying the synchronous reference signal; a timing offset circuit 103 for adjusting a synchronizing position of the synchronous reference signal delayed by the first delaying part 102 to generate a synchronization object signal; a phase comparison circuit 105 for comparing phase differences between the synchronous reference signal and the synchronization object signal; a first control circuit 106 for selecting an output signal of the first delaying part 102 on the basis of a comparison result of the phase comparison circuit 105; a second delaying part 104 for delaying the synchronous reference signal or the synchronization object signal; and a second control circuit 107 for selecting an output signal of the second delaying part 104 when the comparison result of the phase comparison circuit 105 is within a prescribed range, wherein the phase comparison circuit 105 compares phase differences between a signal delayed by the second delaying part 104 and the other signal out of signals between the synchronous reference signal and the synchronization object signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DLL (Delay Locked Loop) circuit, and more particularly to a DLL circuit having a function of reducing the intensity of electromagnetic radiation noise.

  An LSI mounted on an electronic device emits electromagnetic waves according to the power consumption or the operating frequency. Electromagnetic waves adversely affect the entire electronic device as electromagnetic radiation noise. The main cause of electromagnetic radiation noise is an electromagnetic wave generated from a DLL (Delay Locked Loop) circuit provided in the LSI and other circuits using an output signal (DLL output signal) of the DLL circuit. In particular, strong electromagnetic waves are generated from other circuits using the DLL output signal.

  On the other hand, the power consumption and operating frequency, and the integration density and number of LSIs mounted on electronic devices are increasing with the recent enhancement of functionality and integration technology of electronic devices. As a result, the intensity of electromagnetic waves emitted from LSI (electromagnetic radiation intensity) has increased, and the influence of electromagnetic radiation noise on electronic devices cannot be ignored.

  A general LSI includes a DLL circuit. When the DLL circuit is in the locked state (that is, when the LSI including the DLL circuit and the DLL circuit is in the operating state), the frequency of the DLL output signal of the DLL circuit shows a constant value (DLL Lock frequency). As a result, the electromagnetic radiation intensity at the DLL lock frequency becomes very strong.

  Patent Document 1 discloses a DLL circuit that suppresses a minimum delay time (minimum slew rate) of a delay time that can be adjusted over a wide range. However, Patent Document 1 does not disclose means for reducing electromagnetic radiation noise caused by the DLL circuit.

Therefore, the conventional DLL circuit has a problem in that the electromagnetic radiation intensity of the LSI including the DLL circuit and the DLL circuit is increased, and the electronic device including the LSI is adversely affected by electromagnetic radiation noise.
JP 2004-260663 A

  An object of the present invention is to reduce the electromagnetic radiation intensity of an LSI having a DLL circuit and to reduce the influence of electromagnetic radiation noise on an electronic device.

  According to the first aspect of the present invention, the input circuit for generating the synchronization reference signal based on the input signal, the first delay unit for delaying the synchronization reference signal, and the synchronization reference signal delayed by the first delay unit A timing offset circuit that generates a synchronization target signal, a phase comparison circuit that compares a phase difference between the synchronization reference signal and the synchronization target signal, and a comparison result of the phase comparison circuit The comparison result of the first control unit circuit that selects the output signal of the first delay unit based on the second delay unit that delays the synchronization reference signal or the synchronization target signal and the phase comparison unit circuit is within a predetermined range And a second control unit circuit that selects an output signal of the second delay unit when the second delay unit is included in the synchronization reference signal and the synchronization target signal. Delayed by DLL circuit is provided which is characterized by comparing the phase difference between the No. and the other signal.

  According to a second aspect of the present invention, an input circuit that generates a synchronization reference signal based on an input signal, a first delay unit that delays the synchronization reference signal generated by the input circuit, and the first delay The timing offset unit circuit that adjusts the synchronization position of the synchronization reference signal delayed by the unit and generates the synchronization target signal, the synchronization reference signal generated by the input unit circuit, and the synchronization target generated by the timing offset unit circuit A phase comparison unit circuit for comparing a phase difference with a signal, a first control unit for selecting an output signal of the first delay unit based on a comparison result of the phase comparison unit circuit, and a comparison result of the phase comparison unit circuit And a second delay unit that delays the output signal selected by the first control unit when the signal is within a predetermined range.

  ADVANTAGE OF THE INVENTION According to this invention, the electromagnetic radiation intensity of LSI provided with the DLL circuit can be reduced, and the influence on the electronic device of an electromagnetic radiation noise can be reduced by extension.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are one embodiment of the present invention and do not limit the scope of the present invention.

  First, Example 1 of the present invention will be described.

  FIG. 1 is a circuit diagram showing a configuration of a DLL circuit according to the first embodiment of the present invention.

  The DLL circuit according to the first embodiment of the present invention includes an input circuit 101, a first delay unit 102, a timing offset circuit 103, a second delay unit 104, a phase comparison circuit 105, a first control circuit 106, and a second control circuit 107. I have.

  The input circuit 101 generates a “synchronization reference signal (202)” serving as a synchronization reference from the DLL input signal (201), and outputs it to the first delay unit 102 and the phase comparison circuit 105.

  The first delay unit 102 includes a delay line 1021 and a selection circuit 1022. The delay line 1021 and the selection circuit 1022 are serially connected via a plurality of signal lines.

  The delay line 1021 receives the “synchronization reference signal (202)” output from the input circuit 101 and delays it by a predetermined delay time to generate a “delay synchronization reference signal (203)”.

  In accordance with a “control signal (207)” output from the first control circuit 106 to be described later, the selection circuit 1022 selects “DLL output signal (204)” from the “delay synchronization reference signal (203)” output from the delay line 1021. Is output to an external circuit (not shown) connected to the timing offset circuit 103 or the DLL circuit.

  The timing offset circuit 103 receives the “DLL output signal (204)” output from the selection circuit 1022, adjusts the synchronization position, generates a “synchronization target signal (205)”, and outputs it to the second delay unit 104. To do.

  The second delay unit 104 includes five delay circuits 1041 to 1045 and a phase comparison target selection circuit 1046. Each of the delay circuits 1041 to 1045 has a different delay time (D1 to D5). For example, when the operating frequency of the processor mounted on the LSI is 1 GHz, D1 = 20 ps, D2 = 40 ps, D3 = 60 ps, D4 = 80 ps, D5 = 100 ps. Note that a circuit (in the above example, the delay circuit 1043) having an average delay time (in the above example, D3 = 60 ps) of each of the delay circuits 1041 to 1045 is a standard delay circuit. Further, the number of delay circuits 1041 to 1045 may be any number as long as it is two or more.

  Each of the delay circuits 1041 to 1045 receives the “synchronization target signal (205)” output from the timing offset circuit 103, delays it by a predetermined delay time (D1 to D5), and outputs the “delay synchronization target signal ( 2081-2085) ”and output to the phase comparison target selection circuit 1046.

  The phase comparison target selection circuit 1046 outputs “delay synchronization target signals (2081 to 2085)” output from the delay circuits 1041 to 1045 according to a “selection signal (214)” output from the selection signal generation circuit 1073 described later. The “selected delay synchronization target signal (209)” as the output signal of the second delay unit 104 is selected from among them, and is output to the phase comparison circuit 105. The phase comparison target selection circuit 1046 always selects the “delay synchronization target signal (2083)” output from the standard delay circuit (for example, the delay circuit 1043) when the DLL circuit is not in the locked state.

  The phase comparison circuit 105 receives the “synchronization reference signal (202)” output from the input circuit 101 and the “selection delay synchronization target signal (209)” output from the phase comparison target selection circuit 1046, and sets the phases of both. The comparison is made, and the “comparison result (206)” is output to the first control circuit 106.

  The first control circuit 106 receives the “comparison result (206)” output from the phase comparison circuit 105, and “control signal (207)” for controlling the selection circuit 1022 in accordance with the “comparison result (206)”. Is output to the selection circuit 1022. Further, the first control circuit 106 generates a “cycle counter enable signal (210)” for enabling a cycle counter 1071 described later according to the “comparison result (206)”, and outputs it to the cycle counter 1071. . The DLL circuit is in a so-called “locked state” when the “cycle counter enable signal (210)” is generated by the first control circuit.

  The second control circuit 107 includes a cycle counter 1071, a comparison circuit 1072, and a selection signal generation circuit 1073.

  The cycle counter 1071 starts counting the number of cycles in response to the “cycle counter enable signal (210)” output from the first control circuit 106, and outputs the “cycle count value (212)” to the comparison circuit 1072. The cycle counter 1071 resets the cycle count value when a “comparison result (212)” of a comparison circuit 1072 described later indicates “match”.

  The comparison circuit 1072 compares the “cycle count value (212)” output from the cycle counter 1071 with a predetermined “delay circuit switching cycle setting value (211)”, and generates a “comparison result (213)” as a selection signal. Output to the circuit 1073.

  The selection signal generation circuit 1073 generates a “selection signal (214)” for controlling the phase comparison target selection circuit 1046 according to the “comparison result (213)” output from the comparison circuit 1072, and the phase comparison target selection circuit It outputs to 1046. Here, the selection signal generation circuit 1073 is output from a delay circuit having a delay time next to the delay circuit selected immediately before (for example, the delay circuit 1044 when the delay circuit 1043 was selected immediately before). The “selection signal (214)” is generated so that the “delayed synchronization target signal (2083)” is selected. The selection signal generation circuit 1073 generates the “selection signal (214)” so that the “delay synchronization target signal” output from the delay circuit with the shortest delay time next to the delay circuit selected immediately before is selected. It may be configured to. Further, when the delay circuit selected immediately before is the delay circuit having the shortest delay time (or the longest delay time), the selection signal generation circuit 1073 has the longest delay time (or the shortest delay time). The “selection signal (214)” may be generated so that the “delay synchronization target signal” output from the delay circuit having the above is selected.

  FIG. 2 is a flowchart illustrating the processing procedure of the DLL circuit in the selection delay synchronization target signal generation processing according to the first embodiment of the present invention.

  First, when it is not in the locked state (S201-No), the phase comparison target selection circuit 1046 selects the selection delay synchronization target signal (for example, “selection delay synchronization target signal” output from the standard delay circuit (for example, the delay circuit 1043)). (2083) ") is selected (S202).

  On the other hand, when it is in the locked state (S201-Yes), the first control circuit 106 generates a “cycle counter enable signal (210)” (S203). Subsequently, the cycle counter 107 starts cycle counting (S204). Subsequently, when the “comparison result (213)” output from the comparison circuit 1072 indicates a match (S205—Yes), the selection signal generation circuit 1073 generates a “selection signal (214)” (S206). Subsequently, the cycle counter 107 resets the cycle count value (S207). Subsequently, the phase comparison target selection circuit 1046 selects the selected delay synchronization output from a delay circuit different from the delay circuit selected immediately before (for example, a delay circuit having a delay time next to the delay circuit selected immediately before). A target signal is selected (S208).

  S201 to S208 are repeated until an end signal is detected (S209-No). On the other hand, when the end signal is detected after S202 or S208 (S209-Yes), the selection delay synchronization target signal generation process of the first embodiment of the present invention ends. The end signal is detected when the LSI goes into the sleep state, resets, or goes into the power saving mode. In the power saving mode, the DLL circuit according to the first embodiment of the present invention stops the operations of the timing offset circuit 103, the second delay unit 104, the phase comparison circuit 105, and the second control circuit 107. At this time, the first delay unit 102 outputs the “DLL output signal (204)” at a constant frequency.

  According to the first embodiment of the present invention, when the DLL is in the locked state and the LSI is in the operating state, the phase comparison target selecting circuit 1046 has a constant frequency of the “DLL output signal (204)”. Since the “selection delay synchronization target signal (209)” is selected so as to change in the cycle, it is possible to reduce the electromagnetic radiation intensity of the LSI and, in turn, reduce the influence of the electromagnetic radiation noise on the electronic device. it can.

  Next, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment of the present invention, the example in which the synchronization target signal is delayed has been described. In the second embodiment of the present invention, an example in which the synchronization reference signal is delayed will be described. In addition, the description about the content similar to Example 1 of this invention is abbreviate | omitted.

  FIG. 3 is a circuit diagram showing a configuration of a DLL circuit according to the second embodiment of the present invention.

  The DLL circuit according to the second embodiment of the present invention includes an input circuit 301, a first delay unit 302, a timing offset circuit 303, a second delay unit 304, a phase comparison circuit 305, a first control circuit 306, and a second control circuit 307. I have.

  The input circuit 301 generates a “synchronization reference signal (402)” serving as a synchronization reference from the DLL input signal (401), and outputs it to the second delay unit 304.

  The first delay unit 302 includes a delay line 3021 and a selection circuit 3022. The delay line 3021 and the selection circuit 3022 are serially connected via a plurality of signal lines.

  The delay line 3021 receives a “selected delay synchronization reference signal (409)” output from the second delay unit 304 described later, and generates a “delay synchronization reference signal (403)” by delaying it by a predetermined delay time. .

  In accordance with a “control signal (407)” output from the first control circuit 306, which will be described later, the selection circuit 3022 outputs a “DLL output signal (404) from the“ delay synchronization reference signal (403) ”output from the Delay Line 4021. Is output to an external circuit (not shown) connected to the timing offset circuit 303 or the DLL circuit.

  The timing offset circuit 303 receives the “DLL output signal (404)” output from the selection circuit 3022, adjusts the synchronization position, generates a “synchronization target signal (405)”, and outputs it to the phase comparison circuit 305. .

  The second delay unit 304 includes five delay circuits 3041 to 3045 and a phase comparison target selection circuit 3046. Each of the delay circuits 3041 to 3045 has a different delay time (D1 to D5). For example, when the operating frequency of the processor mounted on the LSI is 1 GHz, D1 = 20 ps, D2 = 40 ps, D3 = 60 ps, D4 = 80 ps, D5 = 100 ps. Note that a circuit (in the above example, the delay circuit 1043) having an average delay time (in the above example, D3 = 60 ps) of each of the delay circuits 3041 to 3045 is a standard delay circuit. Further, the number of delay circuits 3041 to 3045 may be any number as long as it is two or more.

  Each of the delay circuits 3041 to 3045 receives the “synchronization reference signal (402)” output from the input circuit 301, delays it by a predetermined delay time (D1 to D5), and outputs a “delay synchronization reference signal (4081). ˜4085) ”is generated and output to the phase comparison target selection circuit 3046.

  The phase comparison target selection circuit 3046 receives the “delay synchronization reference signals (4081 to 4085)” output from the delay circuits 3041 to 3045 in accordance with “selection signal (414)” output from the selection signal generation circuit 3073 described later. The “selected delay synchronization target signal (409)” as the output signal of the second delay unit 304 is selected from the inside, and is output to the phase comparison circuit 305. The phase comparison target selection circuit 3046 always selects the “delay synchronization reference signal (4083)” output from the standard delay circuit (for example, the delay circuit 3043) when the DLL circuit is not in the locked state.

  The phase comparison circuit 305 receives the “synchronization target signal (405)” output from the timing offset circuit 303 and the “selection delay synchronization reference signal (409)” output from the phase comparison target selection circuit 3046. And “comparison result (406)” is output to the first control circuit 306.

  The first control circuit 306 and the second control circuit 307 are the same as the first control circuit 106 and the second control circuit 107 according to the first embodiment of the present invention.

  FIG. 4 is a flowchart illustrating the processing procedure of the DLL circuit in the selection delay synchronization reference signal generation processing according to the second embodiment of the present invention.

  First, when it is not in the locked state (S201-No), the phase comparison target selection circuit 3046 selects the selection delay synchronization reference signal (for example, “selection delay synchronization reference signal” output from the standard delay circuit (for example, the delay circuit 3043)). (4083) ") is selected (S402).

  On the other hand, when it is in the locked state (S401-Yes), the same processing as S203 to S207 in FIG. 2 is performed (S403). Subsequently, the phase comparison target selection circuit 3046 selects the selected delay synchronization output from a delay circuit different from the delay circuit selected immediately before (for example, a delay circuit having a delay time next to the delay circuit selected immediately before). A reference signal is selected (S404).

  S401 to S404 are repeated until an end signal is detected (S405-No). On the other hand, when the end signal is detected after S402 or S404 (S405-Yes), the selection delay synchronization reference signal generation process according to the second embodiment of the present invention ends.

  According to the second embodiment of the present invention, when the DLL is in the locked state and the LSI is in the operating state, the phase comparison target selection circuit 3046 has a constant frequency of the “DLL output signal (404)”. Since the “selection delay synchronization reference signal (409)” is selected so as to change in the cycle of the LSI, the electromagnetic radiation intensity of the LSI can be reduced, and consequently the influence of the electromagnetic radiation noise on the electronic equipment can be reduced. it can.

  Next, Embodiment 3 of the present invention will be described with reference to the drawings. In the first embodiment of the present invention, the example in which the synchronization target signal is delayed has been described. In the third embodiment of the present invention, an example in which the DLL output signal is delayed will be described. In addition, the description about the content similar to Example 1 and 2 of this invention is abbreviate | omitted.

  FIG. 5 is a circuit diagram showing a configuration of a DLL circuit according to the third embodiment of the present invention.

  The DLL circuit according to the first embodiment of the present invention includes an input circuit 501, a first delay unit 502, a timing offset circuit 503, a second delay unit 504, a phase comparison circuit 505, a first control circuit 506, and a second control circuit 507. I have.

  The selection circuit 5022 of the first delay unit 502 selects “delay synchronization reference signal (603)” output from the delay line 5021 according to “control signal (607)” output from the first control circuit 506 described later. DLL output signal (604) ”is selected and output to the timing offset circuit 503 or the second delay unit 504.

  The timing offset circuit 503 receives the “DLL output signal (604)” output from the selection circuit 5022, adjusts the synchronization position, generates a “synchronization target signal (605)”, and outputs it to the phase comparison circuit 505. .

  The second delay unit 504 includes five delay circuits 5041 to 5045 and a DLL output signal selection circuit 5046. Each of the delay circuits 5041 to 5045 has a different delay time (D1 to D5). For example, when the operating frequency of the processor mounted on the LSI is 1 GHz, D1 = 20 ps, D2 = 40 ps, D3 = 60 ps, D4 = 80 ps, D5 = 100 ps. Note that a circuit (in the above example, the delay circuit 5043) having an average delay time (in the above example, D3 = 60 ps) of each of the delay circuits 5041 through 5045 is a standard delay circuit. Further, the number of delay circuits 5041 to 5045 may be any number as long as it is two or more.

  Each of the delay circuits 5041 to 5045 receives the “DLL output signal (604)” output from the selection circuit 5022, delays it by a predetermined delay time (D1 to D5), and outputs the “delayed DLL output signal (6081). ˜6085) ”is generated and output to the DLL output signal selection circuit 5046.

  The DLL output signal selection circuit 5046 outputs “delayed DLL output signals (6081 to 6085)” output from the delay circuits 5041 to 5045 in accordance with “selection signal (614)” output from the selection signal generation circuit 5073 described later. The “selection delay DLL output signal (609)” as the output signal of the DLL circuit is selected from the inside, and is output to an external circuit (not shown) connected to the DLL circuit. Note that the DLL output signal selection circuit 5046 always selects the “delayed DLL output signal (6083)” output from the standard delay circuit (for example, the delay circuit 5043) when the DLL circuit is not in the locked state.

  The phase comparison circuit 505 receives the “synchronization reference signal (602)” output from the input circuit 101 and the “synchronization target signal (605)” output from the timing offset circuit 503, compares the phases of both, The comparison result (606) "is output to the first control circuit 506.

  The input circuit 501, the delay line 5021 of the first delay unit 502, the first control circuit 506, and the second control circuit 507 are the input circuit 101 of the first embodiment of the present invention, the delay line 1021 of the first delay unit 102, This is the same as the first control circuit 106 and the second control circuit 107.

  FIG. 6 is a flowchart illustrating the processing procedure of the DLL circuit in the selection delay DLL output signal generation processing according to the third embodiment of the present invention.

  First, when the lock state is not established (S601-No), the DLL output signal selection circuit 5046 selects the selection delay DLL output signal (for example, “selection delay DLL output signal” output from the standard delay circuit (for example, the delay circuit 5043)). (5083) ") is selected (S602).

  On the other hand, when it is in the locked state (S601-Yes), the same processing as S203 to S207 in FIG. 2 is performed (S603). Subsequently, the DLL output signal selection circuit 5046 selects a selected delay DLL output from a delay circuit different from the delay circuit selected immediately before (for example, a delay circuit having a delay time next to the delay circuit selected immediately before). An output signal is selected (S604).

  S601 to S604 are repeated until an end signal is detected (S605-No). On the other hand, when the end signal is detected after S602 or S604 (S605-Yes), the selection delay DLL output signal generation processing according to the third embodiment of the present invention ends.

  According to the third embodiment of the present invention, when the DLL is in the locked state and the LSI is in the operating state, the DLL output signal selection circuit 5046 has a constant frequency of the “DLL output signal (604)”. Since the “delayed DLL output signal (609)” is selected so as to change in the cycle, it is possible to reduce the electromagnetic radiation intensity of the LSI, and in turn reduce the influence of the electromagnetic radiation noise on the electronic equipment. .

  Further, according to the third embodiment of the present invention, the second delay unit 504 is connected to the subsequent stage of the first delay unit 502, so that the design of the DLL circuit can be facilitated.

Comparative example

  Next, a comparative example of the present invention will be described with reference to the drawings. In addition, the description about the same content as Examples 1-3 is abbreviate | omitted.

  FIG. 7 is a circuit diagram showing a configuration of a DLL circuit according to a comparative example of the present invention.

  The DLL circuit of the comparative example of the present invention includes an input circuit 701, a first delay unit 702, a timing offset circuit 703, a phase comparison circuit 705, and a first control circuit 706.

  The timing offset circuit 703 receives the “DLL output signal (804)” output from the selection circuit 7022, adjusts the synchronization position, generates a “synchronization target signal (805)”, and outputs it to the phase comparison circuit 705. .

  The phase comparison circuit 705 receives the “synchronization reference signal (802)” output from the input circuit 701 and the “synchronization target signal (805)” output from the timing offset circuit 703, compares the phases of both, The comparison result (806) "is output to the first control circuit 706.

  The first control circuit 706 receives the “comparison result (806)” output from the phase comparison circuit 705, and “control signal (807)” for controlling the selection circuit 7022 according to the “comparison result (806)”. Is output to the selection circuit 7022.

  The input circuit 701 and the first delay unit 702 are the same as the input circuit 101 and the first delay unit 102 according to the first embodiment of the present invention.

  FIG. 8 is a graph showing an example of electromagnetic wave radiation intensity distribution of an LSI including the DLL circuits according to the first to third embodiments of the present invention and the DLL circuit according to the comparative example of the present invention. FIG. 8A shows an example of the distribution of the electromagnetic wave radiation intensity of an LSI having a DLL circuit according to a comparative example of the present invention, and FIG. 8B shows the electromagnetic wave radiation intensity of an LSI having a DLL circuit according to the first to third embodiments of the present invention. An example of the distribution of is shown.

  In the DLL circuit of the comparative example of the present invention, when the DLL is in the locked state and the LSI is in the operating state, the frequency (DLL lock frequency) of the “DLL output signal (804)” is constant. The maximum value of electromagnetic wave radiation intensity increases (Level-A) and the width of the DLL lock frequency decreases (see FIG. 8A). As shown in FIG. 8A, in the DLL circuit of the comparative example of the present invention, the electromagnetic wave radiation intensity at a specific frequency is increased.

  On the other hand, in the DLL circuits according to the first to third embodiments of the present invention, when the DLL is in the locked state and the LSI is in the operating state, the frequency of the “DLL output signal” swings in a constant cycle. Therefore, the maximum value of the electromagnetic wave radiation intensity is smaller than that of the comparative example of the present invention (Level-B), and the width of the DLL lock frequency is widened (see FIG. 8B). As shown in FIG. 8B, in the DLL circuits according to the first to third embodiments of the present invention, the frequency band indicating the maximum value of the electromagnetic wave radiation intensity is widened and the maximum value is also small.

  From the above, it was found that the electromagnetic wave radiation intensity was reduced in the DLL circuits of Examples 1 to 3 of the present invention compared to the DLL circuit of the comparative example of the present invention.

It is a circuit diagram which shows the structure of the DLL circuit of Example 1 of this invention. It is a flowchart which shows the process sequence of the DLL circuit in the selection delay synchronous object signal generation process of Example 1 of this invention. It is a circuit diagram which shows the structure of the DLL circuit of Example 2 of this invention. It is a flowchart which shows the process sequence of the DLL circuit in the selection delay synchronous reference signal generation process of Example 2 of this invention. It is a circuit diagram which shows the structure of the DLL circuit of Example 3 of this invention. It is a flowchart which shows the process sequence of the DLL circuit in the selection delay DLL output signal generation process of Example 3 of this invention. It is a circuit diagram which shows the structure of the DLL circuit of the comparative example of this invention. It is a graph which shows an example of distribution of the electromagnetic wave radiation intensity discharge | released by the DLL circuit of Examples 1-3 of this invention, and the DLL circuit of the comparative example of this invention.

Explanation of symbols

101 Input Circuit 102 First Delay Unit 1021 Delay Line
1022 selection circuit 103 timing offset circuit 104 second delay units 1041 to 1045 delay circuit 1046 phase comparison target selection circuit 105 phase comparison circuit 106 first control circuit 107 second control circuit 1071 cycle counter 1072 comparison circuit 1073 selection signal generation circuit

Claims (5)

An input circuit for generating a synchronization reference signal based on the input signal;
A first delay unit for delaying the synchronization reference signal;
A timing offset circuit for adjusting a synchronization position of the synchronization reference signal delayed by the first delay unit and generating a synchronization target signal;
A phase comparison circuit for comparing a phase difference between the synchronization reference signal and the synchronization target signal;
A first control circuit that selects an output signal of the first delay unit based on a comparison result of the phase comparison circuit;
A second delay unit that delays the synchronization reference signal or the synchronization target signal;
A second control circuit that selects an output signal of the second delay unit when a comparison result of the phase comparison circuit is within a predetermined range;
The phase comparison circuit compares a phase difference between a signal delayed by the second delay unit of the synchronization reference signal and the synchronization target signal and the other signal. The second delay unit delays the synchronization target signal generated by the timing offset circuit,
The DLL circuit according to claim 1, wherein the phase comparison circuit compares a phase difference between a synchronization reference signal generated by the input unit and a synchronization target signal delayed by the second delay unit. The second delay unit delays the synchronization reference signal generated by the input unit,
The DLL circuit according to claim 1, wherein the phase comparison circuit compares a phase difference between the synchronization reference signal delayed by the second delay unit and the synchronization target signal generated by the timing offset circuit. An input circuit for generating a synchronization reference signal based on the input signal;
A first delay unit for delaying the synchronization reference signal generated by the input circuit;
A timing offset circuit for adjusting a synchronization position of the synchronization reference signal delayed by the first delay unit and generating a synchronization target signal;
A phase comparison circuit that compares the phase difference between the synchronization reference signal generated by the input circuit and the synchronization target signal generated by the timing offset circuit;
A first control unit that selects an output signal of the first delay unit based on a comparison result of the phase comparison circuit;
A DLL circuit comprising: a second delay unit that delays an output signal selected by the first control unit when a comparison result of the phase comparison circuit is within a predetermined range. The first control unit, when the comparison result of the phase comparison circuit is within a predetermined range, gives the comparison result to the second control unit,
The second controller is
Counting means for counting the number of cycles when the comparison result is given by the first control unit;
Comparing means for comparing the count value of the counting means with a predetermined value;
5. A selection signal generation unit configured to generate a selection signal for selecting an output signal of the second delay unit when a comparison result of the comparison unit matches. 6. DLL circuit.

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