JP2008263312A - Crystal oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a crystal oscillation circuit which is free of a harmonic noise due to power supply variation. <P>SOLUTION: The crystal oscillation circuit 100 includes an inverter 102 composed of current mode logic (CML: Current Mode Logic), a feedback resistor R2 connected to the inverter 102 in parallel, and a resonance circuit 101 connected to the inverter 102 in parallel through a resistor R1 for output, and the resonance circuit 101 has a crystal vibrator 103 connected to the inverter 102 in parallel through the resistor R1 for output and capacitors C1 and C2 connected between both ends of the crystal vibrator 103 and a ground respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a crystal oscillation circuit used for a radio receiver or the like.

Conventionally, since the frequency stability is high, a crystal oscillator is used as an oscillator in a transceiver such as a radio or a reference oscillator of a measuring instrument.
As shown in FIG. 4, the crystal oscillation circuit 400 generally includes a crystal resonator 103, capacitors C1 and C2, an inverter 401, an output resistor R1, and a feedback resistor R2.

  Here, the inverter 401 includes a plurality of inverters 401a, 402b,... Having the same or different sizes, and the size of the inverter can be switched by a switch included in each inverter. With this configuration, the negative resistance of the circuit is variable.

  For example, a sufficient oscillation margin can be ensured by switching the switch so that the inverter 401 becomes the maximum size at the time of startup and sufficiently increasing the negative resistance of the circuit with respect to the equivalent resistance of the crystal unit 103. it can. Further, by switching the switch so as to reduce the size of the inverter 401 in a steady state or the like, the through current passing through the CMOS constituting each of the inverters 401a, 401b,. Alternatively, harmonics (hereinafter referred to as “harmonic noise”) generated due to voltage fluctuation of the ground) can be suppressed.

  Here, the through current is a phenomenon in which the P-type MOS transistor and the N-type MOS transistor constituting the CMOS circuit are simultaneously turned on at the moment when the input signal to the CMOS circuit is inverted (ON to OFF, OFF to ON). This refers to the current generated through the power source-P-type MOS transistor-N-type MOS transistor-ground. As a result of fluctuations in the power supply voltage and the like due to the change in the through current, harmonic noise generated in the crystal oscillation circuit adversely affects circuit operations (characteristics) of other circuits in the device (semiconductor IC).

  In relation to the above-described technique, Patent Document 1 discloses a low-pass filter having characteristics equivalent to a low-pass filter characteristic formed by a capacitance component of a resonator generated on the second transistor side and a feedback resistor. In addition, a sinusoidal oscillator is also disclosed which can suppress oscillation of harmonics and enable oscillation at a single frequency.

  In Patent Document 2, a resonator for performing an oscillation operation provided between an input and an output of a first amplifier circuit having a variable gain function is provided to perform the oscillation operation, and the first amplification is performed. A gain control circuit is provided for receiving an output signal of a second amplifier circuit having a variable gain function for receiving and amplifying the output signal of the circuit and controlling the oscillation output signal of the second amplifier circuit to be constant. By controlling the gain of the first and second amplifier circuits so that the oscillation output signal becomes constant in response to the loss variation and fluctuation of the resonator, the oscillation component can be suppressed while stabilizing the oscillation operation. A circuit is disclosed.

  Further, in Patent Document 3, a pull-down resistor provided between an output terminal of an ECL (emitter coupling logic) as an oscillation amplifier and the ground is used as first and second divided resistors connected in series, and the divided resistors are A crystal oscillation circuit is disclosed in which a bypass capacitor is provided between a connection point and ground to maintain an output level and prevent a change in oscillation frequency due to a fluctuation in power supply voltage.

However, as shown in FIG. 4, as long as the inverter 401 is composed of CMOS, the through current cannot be reduced to 0 (this inverter is referred to as “CMOS inverter”). For example, when the crystal oscillation circuit 400 is oscillated, a through current shown in FIG. As a result, as shown in FIG. 5B, there is a problem that harmonic noise generated due to fluctuations in the power supply voltage and the like due to the through current deteriorates the sensitivity of the reception channel.
Japanese Patent Laid-Open No. 05-152848 Japanese Patent Laid-Open No. 10-084222 JP 2004-320321 A

  The present invention has been made in view of the above-described problems, and the problem to be solved is to provide a crystal oscillation circuit with less harmonic noise caused by power supply fluctuations caused by a through current generated in a CMOS inverter. is there.

  In order to solve the above problems, a crystal oscillation circuit according to the present invention includes a resonance circuit in which a crystal resonator and a capacitor are connected in series, and an inverter circuit having a constant current characteristic connected in parallel to the resonance circuit. .

  As described above, according to the present invention, since the inverter circuit has a constant current characteristic, no through current is generated unlike a CMOS inverter. Therefore, it is possible to provide a crystal oscillation circuit free from harmonic noise caused by fluctuations in power supply voltage (or ground) due to through current.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
FIG. 1 is a diagram showing an overall configuration of a crystal oscillation circuit 100 according to an embodiment of the present invention.
A crystal oscillation circuit 100 illustrated in FIG. 1 is a crystal oscillation circuit including a resonance circuit 101 and an inverter 102 that is connected in parallel to the resonance circuit 101 and configured by current mode logic (CML: Current Mode Logic). Further, the crystal oscillation circuit 100 according to the present embodiment includes an output resistor R1 between the resonance circuit 101 and the inverter 102, and a feedback resistor R2 in parallel with the inverter 102.

  The resonance circuit 101 includes a crystal resonator 103 and capacitors C1 and C2. Both ends of the crystal unit 103 are connected to capacitors C1 and C2, respectively. The other ends of the capacitors C1 and C2 are connected to the ground. The resonance circuit 101 and the inverter 102 are connected so that the crystal unit 103 and the inverter 102 are connected in parallel.

FIG. 2 is a diagram showing a specific configuration of the inverter 102 according to the embodiment of the present invention.
The inverter 102 illustrated in FIG. 2 includes a signal inverting circuit 201 that generates an inverted signal Vout with respect to the input signal Vin, and a current source circuit 202 that is connected to the signal inverting circuit 201.

The signal inverting circuit 201 includes N-type MOS transistors Tra1 and Tra2 and resistors R3 and R4.
In the signal inversion circuit 201, the drain of the MOS transistor Tra1 and the drain of Tra2 are connected to the power supply (Vdd) via the resistors R3 and R4, respectively, and the source of the MOS transistor Tra1 and the source of Tra2 are connected to each other. Configure the circuit.

The current source circuit 202 includes an N-type MOS transistor Trb1, N-type MOS transistors Trc1 to Trcn (n is an integer of 2 or more, and the same applies hereinafter) and a power source J.
The drain of the MOS transistor Trb1 is connected to the power source (Vdd) via the current source J, and the source is connected to the ground. Further, the drains of the MOS transistors Trc1, Trc2,..., Trcn are connected to the signal inversion circuit 201 (the sources of the MOS transistors Tra1 and Tra2), and the sources are connected to the ground.

  The MOS transistors Trb1 and Trc1 constitute a current mirror circuit. Similarly, the MOS transistor Trb1 and the MOS transistors Trc2,..., Trc1 form a current mirror circuit.

  Further, switches SW11 and SW12 are provided between the gates of the MOS transistors Trc1 and Trc2. Similarly, switches SW21 and SW22, SW31 and SW32,..., SW (n−1) are provided between the gate of the MOS transistor Trc1 and the gates of the MOS transistors Trc3, Trc4,. 1 and SW (n-1) 2.

  In the above configuration, a predetermined bias voltage Vbia is input to the gate of the MOS transistor Tra1. An input signal is input to the gate of the MOS transistor Tra2. When the input signal Vin to the MOS transistor Tra2 becomes High, the MOS transistor Tra2 is turned on, so that the drain-source becomes conductive and the output signal Vout becomes Low. Similarly, when the input signal Vin to the MOS transistor Tra2 becomes Low, the MOS transistor Tra2 is turned OFF, so that the output signal Vout becomes High.

  Then, by switching ON / OFF of the switches SW11 and SW12, SW21 and SW22,..., SW (n-1) 1 and SW (n-1) 2, the current I1 flowing through the MOS transistor Trb1 and the signal inversion are switched. The current ratio I1: I2 with the current I2 flowing through the circuit 201 can be switched from 1: 1 to 1: n.

  Therefore, by switching the switches SW11 and SW12, SW21 and SW22,..., SW (n-1) 1 and SW (n-1) 2, the output amplitude and current consumption of the inverter 102 configured by CML are stepped. Can be changed automatically.

  Here, when the crystal oscillation circuit 100 according to the present embodiment is used for a reception circuit of an FM radio receiver, for example, when the reception frequency of the reception circuit is n times the oscillation frequency of the crystal resonator 103, the switch SW11, SW21,..., SW (n-1) 1 are turned off (switches SW12, SW22,..., SW (n-1) 2 are turned on) to reduce the gain and current consumption of the inverter 102. Reduce harmonic noise and switch SW11, SW21,..., SW (n-1) 1 ON (switches SW12, SW22,..., SW (n-1) 2 OFF at times other than n times. ) To increase the gain and current consumption of the inverter 102 and improve the stability of the oscillation operation. Further, for example, at the time of start-up (at the start of oscillation), the switches SW11, SW21,..., SW (n-1) 1 are turned on (switches SW12, SW22,..., SW (n-1) 2 are turned off. ) To increase the size of the inverter 102 to ensure a sufficient negative resistance, and the switches SW11, SW21,..., SW (n−1) 1 are turned off (switches SW12, SW22,. .., SW (n-1) 2 so that the power consumed by the crystal oscillation circuit 100 is suppressed by turning on SW (n-1) 2. And SW (n-1) 2 may be controlled digitally.

  Although the device for controlling the above-described switch is not shown, for example, the switches SW11 and SW12, SW21 and the logic circuit using an FPGA (Field Programmable Gate Array) or the like and an MPU execute a predetermined program. SW22,..., SW (n-1) 1 and SW (n-1) 2 may be controlled.

FIG. 3 is a diagram illustrating characteristics of the crystal oscillation circuit 100 according to the embodiment of the present invention.
In a steady state where the output voltage Vout shown in FIG. 3A is generated, the current I2 flowing through the inverter 102 has a current waveform shown in FIG. Compared with FIG. 5A, it can be seen that no through current flows through the inverter 102.

  FIG. 3C shows a spectrum of current consumption of the inverter 102, which is proportional to the magnitude of harmonic noise generated in the power supply. As compared with FIG. 5B, it can be seen that the harmonic noise of about 100 (dB) is reduced.

  As described above, since the inverter 102 constituting the crystal oscillation circuit 100 according to the present embodiment is composed of CML, no through current is generated unlike a CMOS inverter. Accordingly, there is no fluctuation of the power supply voltage (or ground) due to the through current, and it is possible to eliminate the harmonic noise generated due to the fluctuation.

  Further, since the inverter 102 uses the drain voltage of the MOS transistor Tra2 whose voltage has dropped by the resistor R4 as the output voltage, it can oscillate with an output voltage having a smaller amplitude than that of the CMOS inverter. As a result, the power consumed by the crystal oscillation circuit 100 can be reduced.

  Further, since the inverter 102 includes a plurality of switches SW11 and SW12, SW21 and SW22,..., SW (n-1) 1 and SW (n-1) 2, by switching these switches digitally, The gain (output amplitude) can be easily adjusted.

It is a figure which shows the whole structure of the crystal oscillation circuit which concerns on the Example of this invention. It is a figure which shows the specific structure of the inverter which concerns on the Example of this invention. It is a figure which shows the characteristic of the crystal oscillation circuit which concerns on the Example of this invention. It is a figure which shows the prior art example of a crystal oscillation circuit. FIG. 5 is a diagram illustrating characteristics of the crystal oscillation circuit illustrated in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Crystal oscillation circuit 101 ... Resonance circuit 102 ... Inverter 103 ... Crystal oscillator 201 ... Signal inversion circuit 202 ... Current source circuit

Claims (6)

A resonant circuit in which a crystal unit and a capacitor are connected in series;
An inverter circuit having a constant current characteristic connected in parallel to the resonant circuit;
A crystal oscillation circuit comprising: The inverter circuit is a differential amplifier circuit composed of a MOS transistor whose drain is connected to a power supply via a resistor,
A first transistor in which a bias voltage is input to the gate as an input voltage;
A second transistor having an input signal input to the gate;
A current source circuit commonly connected to sources of the first transistor and the second transistor,
The drain voltage of the second transistor is an output voltage.
The crystal oscillation circuit according to claim 1.   The crystal oscillation circuit according to claim 2, wherein the current source circuit is a variable current source circuit. The current source circuit is a current mirror circuit including a third transistor and a plurality of fourth transistors, and at least one of the fourth transistors includes a switch.
The crystal oscillation circuit according to claim 2. The switch is switched so that the current flowing through the inverter circuit is minimized when the predetermined frequency is an integral multiple of the oscillation frequency generated by the crystal resonator, and is other than an integral multiple of the predetermined frequency. In such a case, the current flowing through the inverter circuit is switched so as to become maximum.
The crystal oscillation circuit according to claim 4. The switch is switched so that the current flowing through the inverter circuit is maximized at the start of oscillation, and is switched so that the current flowing through the inverter circuit is minimized during steady state.
The crystal oscillation circuit according to claim 4.