JP2008263015A - Semiconductor light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-power semiconductor light-emitting element which can achieve the proper bonding of a substrate and can improve an yield. <P>SOLUTION: A light-emitting diode 100 is provided with a compound semiconductor layer 14 which has a light-emitting layer part, a conductive support substrate 10 which supports the compound semiconductor layer 14, a metal light reflection layer 9 which is arranged between the compound semiconductor layer 14 and the conductive support substrate 10 and reflects light from the light-emitting layer part, an interface electrode 8 which is formed in a part of a joint interface between the compound semiconductor layer 14 and the metal light reflection layer 9, a Ti layer 18 which is formed in contact with the major surface of the conductive support substrate 10 on the side of the metal light reflection layer 9, a metal joining layer 11 of Au which is formed in contact with the major surface of the Ti layer 18 on the side of the metal light reflection layer 9, a surface electrode 12 which is formed on the side of a first major surface as the light extraction surface of the compound semiconductor layer 14 and a back electrode 13 which is formed on the major surface on the other side of the Ti layer 18 of the conductive support substrate 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor light-emitting device, and more particularly to a semiconductor light-emitting device having a structure in which a compound semiconductor layer having a light-emitting layer portion is supported by a conductive support substrate using a substrate pasting technique.

  In recent years, light emitting diodes (LEDs), which are semiconductor light emitting devices, have been able to grow GaN-based and AlGaInP-based high-quality crystals by the MOVPE method, so blue, green, orange, yellow, red High brightness LED can be manufactured. And with the increase in brightness of LEDs, their uses have expanded to automobile brake lamps, liquid crystal display backlights, and the like, and demand for LEDs has been increasing year by year.

  Currently, since high-quality crystals can be grown by the MOVPE method, the internal quantum efficiency of AlGaInP-based LEDs in particular is approaching a theoretical limit value. However, the light extraction efficiency from the LED element is still low, and it is important to improve the light extraction efficiency.

  For example, a high-intensity red LED is formed of an AlGaInP-based material, and includes an n-type AlGaInP layer and a p-type AlGaInP layer made of an AlGaInP-based material having a lattice-matched composition on a conductive GaAs substrate, and an AlGaInP layer sandwiched between them. Alternatively, a double heterostructure having a light emitting layer (active layer) made of GaInP is formed. However, since the band gap of the GaAs substrate is narrower than the band gap of the light emitting layer, most of the light from the light emitting layer is absorbed by the GaAs substrate, and the light extraction efficiency is significantly reduced.

  To deal with these physical problems, for example, as disclosed in Patent Document 1, a multilayer reflective film structure in which semiconductor layers having different refractive indexes are laminated between a light emitting layer and a GaAs substrate is formed. There is a method for reducing light absorption and improving light extraction efficiency. However, in this method, only light with a limited small incident angle can be reflected from the light traveling from the light emitting layer to the multilayer reflective film structure.

  Therefore, as disclosed in Patent Document 2, for example, a double heterostructure made of an AlGaInP-based material is bonded to a Si support substrate via an Au-based metal layer (also a substrate bonding metal bonding layer) having a high reflectance. Thereafter, a method of removing the GaAs substrate used for growth has been devised. When this method is used, since a metal layer is used as the reflective film, it is possible to obtain a high reflectance without selecting an incident angle of light to the metal layer.

In the case of a laminating method through a metal layer, even if either a thermocompression bonding or a eutectic bonding method is adopted, the epitaxial growth substrate to be bonded and the support substrate have sufficient bonding strength, etc. For this purpose, it is necessary to heat to a temperature of about 150 ° C. to 400 ° C., for example. However, if the difference in linear expansion coefficient between the growth substrate and the support substrate is too large, a large warp due to the difference in linear expansion coefficient occurs when the substrates are heat-bonded, and the substrate is cracked or cracked. There is a case. Therefore, in selecting a material for the support substrate, an important reason for selection is that the difference in linear expansion coefficient between the growth substrate (starting substrate, mainly a GaAs substrate) and the support substrate is small.
In other words, selecting the bonding temperature for bonding and the material of the support substrate for the growth substrate is an extremely important parameter in order to prevent the generation of “cracks” and “cracks” in the bonding process. The reason why the Si substrate is used as the material of the support substrate in Patent Document 2 is largely due to these factors.

  However, in the method disclosed in Patent Document 2, a substrate-side bonding layer made of AuSb (gold / antimony alloy) or AuSn (gold / tin alloy) is inserted between the Si substrate as the support substrate and the Au-based metal layer. Has been. The substrate-side bonding layer is a layer provided in order to improve the ohmic contact with the Si substrate and is effective for reducing the series resistance with the Si substrate, but the main component is composed of Au. Therefore, it is very easy to cause an alloying reaction with Si. For this reason, in the bonding process, the Au-Si alloying reaction between the Si substrate and the Au-based substrate side bonding layer spreads to the alloying reaction of the Au-based metal layer that is the reflective layer, and the Au-based metal layer Decreases reflectivity. Further, in the electrode alloy process of the LED wafer, the Au—Si alloy is melted by alloying reaction between the Si substrate and the Au-based metal layer in the alloy, and the epitaxial layer thereon is peeled off.

  Therefore, in order to prevent the alloying reaction of the Au-based metal layer, which is a reflective layer, and to suppress a decrease in the light reflectance of the Au-based metal layer, a patent is made so that the Au-based metal layer itself can be kept pure. Document 3 discloses a method of providing a diffusion-preventing metal layer mainly composed of Ti or Ni between an Au-based metal layer and an Au-based substrate-side bonding layer bonded to a Si support substrate. .

JP-A-7-66455 JP 2004-235581 A JP 2004-235506 A

  In the method of Patent Document 3 described above, by providing the diffusion preventing metal layer, it is possible to prevent and suppress the diffusion of Si into the Au-based metal layer. However, the phenomenon that the epitaxial layer is peeled off cannot be suppressed by melting the Au-based substrate side bonding layer into an Au—Si alloy. This is because this exfoliation phenomenon occurs because the melted layer is generated between the Si support substrate and the epitaxial layer, so that the epitaxial layer is physically released from stress and the like. Patent Document 3 shows an example in which Ni is used for the diffusion-preventing metal layer. Ni is also a material that easily causes an alloying reaction with Si, and the above-described alloying reaction between Au and Si. Like the problem, the material of concern increases, and it is difficult to say that it is a preferable material.

  An object of the present invention is to provide a high-output semiconductor light-emitting device that can solve the above-described problems, can realize good substrate bonding, and can improve the yield of the semiconductor light-emitting device.

In order to solve the above problems, the present invention is configured as follows.
According to a first aspect of the present invention, there is provided a compound semiconductor layer having a light emitting layer portion, a conductive support substrate that supports the compound semiconductor layer, and the compound semiconductor layer and the conductive support substrate. A metal light reflection layer that reflects light from the light emitting layer, an interface electrode formed at a part of a bonding interface between the compound semiconductor layer and the metal light reflection layer, and the metal light reflection of the conductive support substrate A Ti layer formed in contact with the main surface on the layer side; a metal bonding layer made of Au formed in contact with the main surface on the metal light reflecting layer side of the Ti layer; and a light extraction surface of the compound semiconductor layer And a back electrode formed on the main surface opposite to the Ti layer of the conductive support substrate, and a semiconductor light emitting device comprising: It is an element.

According to a second aspect of the present invention, in the semiconductor light emitting device according to the first aspect, the conductive support substrate is a Si substrate, and the resistivity of the Si substrate is 0.1 Ω · cm or less. To do.

  According to a third aspect of the present invention, in the semiconductor light emitting device according to the first or second aspect, the thickness of the Ti layer is 50 nm or more and 2 μm or less.

  According to a fourth aspect of the present invention, in the semiconductor light emitting device according to any one of the first to third aspects, a thickness of the metal bonding layer is 0.5 μm or more and 3 μm or less.

  According to a fifth aspect of the present invention, in the semiconductor light emitting device according to any one of the first to fourth aspects, the interface electrode is a dielectric layer formed between the compound semiconductor layer and the metal light reflection layer. The metal layer is formed by connecting the second main surface of the compound semiconductor layer and the metal light reflection layer to the opening.

  According to a sixth aspect of the present invention, in the semiconductor light emitting device according to any one of the first to fifth aspects, the interface electrode is a second main surface of the compound semiconductor layer with respect to the surface area of the second main surface of the compound semiconductor layer. The ratio of the surface area of the surface in contact with the surface is 30% or less.

  According to a seventh aspect of the present invention, in the semiconductor light emitting device according to any one of the first to sixth aspects, the interface electrode is formed dispersedly outside a region immediately below the surface electrode. To do.

According to an eighth aspect of the present invention, in the semiconductor light emitting device according to any one of the fifth to seventh aspects, the main component of the dielectric layer is SiO ₂ .

  According to the present invention, by providing a structure in which only the Ti layer is provided between the conductive support substrate made of Si or the like and the metal bonding layer made of Au, the Ti layer is made of a conductive support substrate made of Si or the like and an alloy. The alloying reaction is not caused or the alloying reaction is hardly caused, so that the alloy melt can be surely prevented by the heat treatment during the production, and the alloying of the conductive support substrate made of Si or the like and the metal bonding layer made of Au is made. The reaction can be effectively suppressed by the Ti layer, and good ohmic contact with the conductive support substrate is possible. As a result, the yield of the replaceable semiconductor light emitting device can be remarkably improved, and a semiconductor light emitting device having a high output and a low operating voltage can be obtained.

  Hereinafter, a light emitting diode (LED) according to an embodiment of a semiconductor light emitting device of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing the structure of the LED element of this embodiment.

  As shown in FIG. 1, the LED element 100 includes a compound semiconductor layer 14 having a light emitting layer portion, a conductive support substrate (Si substrate or the like) 10 that supports the compound semiconductor layer 14, a compound semiconductor layer 14, and a conductive support. A metal light reflection layer 9 provided between the substrate 10 and reflecting the light from the light emitting layer portion, and an interface electrode 8 formed at a part of the bonding interface between the compound semiconductor layer 14 and the metal light reflection layer 9. And Ti layer 18 formed in contact with the main surface of the conductive support substrate 10 on the metal light reflecting layer 9 side, and Au formed in contact with the main surface of the Ti layer 18 on the metal light reflecting layer 9 side. The metal bonding layer 11 (11a and 11b), the surface electrode 12 formed on the first main surface side to be the light extraction surface of the compound semiconductor layer 14, and the main layer on the opposite side to the Ti layer 18 of the conductive support substrate 10 And a back electrode 13 formed on the front surface side. .

There is no particular limitation on the material of the growth substrate (starting substrate) for forming the compound semiconductor layer 14 by epitaxial growth. In addition to GaAs, InP, Ge, sapphire, or the like may be used as a material for the growth substrate. The growth substrate having the compound semiconductor layer 14, the interface electrode 8, the metal light reflecting layer 9, and the metal bonding layer 11a is bonded to the conductive support substrate 10 having the Ti layer 18 and the metal bonding layer 11b, and is grown from the bonded substrate. After the working substrate is removed by etching or the like, the surface electrodes 12 and 13 are formed.

As a material for the light emitting layer portion of the compound semiconductor layer 14, in addition to the AlGaAs compound semiconductor and the AlGaInP compound semiconductor, a GaN compound semiconductor, an InGaAsP compound semiconductor, and the like may be selected. However, when obtaining a high-power semiconductor light emitting device of yellow band to red band, the growth substrate material is preferably GaAs, and the compound semiconductor layer material is preferably an AlGaInP-based material.
In the case of the high-brightness red LED of FIG. 1, the light emitting layer is sandwiched between an n-type AlGaInP clad layer 4 and a p-type AlGaInP clad layer 6 having a lattice-matched composition on a conductive n-type GaAs substrate. It has a double hetero structure with the AlGaInP active layer (light emitting layer) 5 formed. In the compound semiconductor layer 14 of FIG. 1, the n-type GaAs contact layer 3 is between the n-type AlGaInP cladding layer 4 and the surface electrode 12, and the p-type is between the p-type AlGaInP cladding layer 6 and the interface electrode 8. GaP contact layers 7 are respectively provided.
For epitaxial growth of the compound semiconductor layer 14, it is preferable to perform vapor phase growth by MOVPE (metal organic vapor phase epitaxy) method using an MOCVD apparatus, but is not limited to this, for example, LPE method (liquid phase growth) Of course, it may be produced by another manufacturing method such as

The interface electrode 8 is formed in the p-type GaP contact layer 7 serving as the second main surface of the compound semiconductor layer 14 in the opening of the dielectric layer 15 formed between the p-type GaP contact layer 7 and the metal light reflection layer 9. It is a metal layer formed by connecting the interface and the metal light reflection layer 9. The openings of the dielectric layer 15, that is, the interface electrodes 8 are preferably dispersed and formed outside the region immediately below the surface electrode 12 because the light extraction efficiency can be improved. The ratio of the surface area of the surface of the interface electrode 8 in contact with the contact layer 7 to the surface area of the second main surface of the p-type GaP contact layer 7 is preferably 30% or less. The main component of the dielectric layer 15 is preferably SiO ₂ .

In this embodiment, an alloying barrier layer 16 made of Pt or the like is provided between the metal light reflection layer 9 and the Au metal bonding layer 11. The metal bonding layer 11 includes a metal bonding layer 11a on the growth substrate side and a metal bonding layer 11b on the support substrate 10 side. When the growth substrate and the support substrate 10 are bonded to each other, the surfaces of the metal bonding layer 11a and the metal bonding layer 11b are brought into close contact with each other and heated and bonded together under pressure. The thickness of the metal bonding layer 11 is preferably 0.5 μm or more and 3 μm or less.

Further, the Ti layer 18 formed in contact with the conductive support substrate 10 has good adhesion to any of an oxide substrate, a compound semiconductor substrate, and a metal substrate. Can be bonded to materials with low contact resistance. Therefore, the material of the conductive support substrate 10 used for bonding is not particularly limited. The thickness of the Ti layer 18 is preferably 50 nm or more and 2 μm or less.
In consideration of heat conduction and electric conduction, the conductive support substrate 10 is preferably a simple substance rather than a compound or alloy, and examples thereof include silicon, germanium, aluminum, gold, silver, copper, platinum, titanium, molybdenum, and tungsten. . However, the material of the support substrate 10 is not necessarily limited to these. For example, if the difference in the linear expansion coefficient between the support substrate and the growth substrate or the epitaxial layer becomes too large, the epitaxial layer or the substrate cracks, In view of these problems, compounds and alloys such as GaP, Cu—W alloy, Cu—Mo alloy, and the like are also within the range of selection of the support substrate 10 material.
Moreover, it can be said that the support substrate material used for bonding is preferably an Si substrate that is industrially available at a low cost and does not have a large difference in linear expansion coefficient from GaAs. In the case of a Si substrate, the resistivity is preferably 0.1 Ω · cm or less. When a semiconductor is used as the support substrate material, it is preferable to use a low resistance substrate having a resistivity of 0.05 Ω · cm or less in order to reduce the series resistance with the Ti layer 18.

  The grounds and reasons for adopting the light emitting diode structure of the above-described embodiment will be described next.

First, when the conductive support substrate 10 is made of Si, the resistivity of the Si support substrate is preferably at least 0.1 Ω · cm or less. The reason for this is to keep the contact resistance with the Ti main layer 18 and the back electrode 13 formed on the first main surface and the second main surface of the Si support substrate low, and hence the operating voltage of the LED element low. Further, if the resistivity is higher than 0.1 Ω · cm, not only ohmic contact with the electrodes 13 and 18 can be obtained, but also the series resistance by the support substrate in operating the LED is too large. Therefore, the operating voltage of the LED becomes abnormally high.

Second, the thickness of the Ti layer 18 on the first main surface of the support substrate 10 made of Si or the like is preferably in the range of 50 nm to 2 μm. The grounds for the lower limit of 50 nm of the thickness of the Ti layer 18 are as follows. For example, if the Ti layer 18 becomes too thin, ohmic contact between the Ti layer 18 and the Si support substrate 10 becomes difficult to obtain, and the Si and Au metal bonding layers 11 of the Si support substrate 10 become difficult to obtain. This is because the effect of suppressing the Si—Au alloying reaction with Au by the Ti layer 18 is also reduced.
The grounds for the upper limit of 2 μm are as follows. There is no particular problem even if the thickness of the Ti layer 18 becomes 5 μm or 10 μm, for example, due to the characteristics of the LED element, but the alloying barrier effect as intended by the Ti layer 18 and the function as an ohmic electrode Can be sufficiently obtained even when the Ti layer is thinner. Therefore, excessively thickening the Ti layer is a cheaper material compared to Au and Pt, but it only increases the amount of raw materials used and increases the cost, such as a decrease in the throughput of vacuum deposition. . Moreover, even if the Ti layer is formed by either sputtering or vacuum evaporation, excessive deposition of the Ti layer will cause the temperature inside the apparatus to become abnormally hot, and shorten the maintenance cycle due to excessive deposition. This increases the burden on the device. Therefore, about 2 μm is preferable as a suitable range in which no excessive deposition occurs. As described above, the film thickness range of the Ti layer that is more suitable for obtaining ohmic contact, inhibiting the alloying reaction between Au and Si, etc. includes the heating temperature at the time of wafer bonding in manufacturing, and the electrode. Although depending on the alloy temperature at the time of alloying, it can be said that it is about 100 nm or more and 1 μm or less.

Third, the film thickness of the metal bonding layer 11 is preferably in the range of 0.5 μm or more and 3.0 μm or less at the bonding interface between the wafers. This is because the film thickness of the metal bonding layer 11 is extremely important for the yield in bonding. Basically, if the thickness of the metal bonding layer 11 is large, for example, even if a convex foreign material adheres at the bonding interface, the metal bonding layer 11 acts as a buffer layer so as to softly include the foreign material. I can do it. That is, if the metal bonding layer 11 is thick, voids (bonding failure portions) due to foreign matters or the like can be eliminated or suppressed. That is, in order to obtain a good bonding yield in the manufacture of the replaceable LED, the thickness of the metal bonding layer 11 at the bonding interface is required to be approximately 0.5 μm or more. If the film thickness is thinner than that, a large void will be generated even if it is a very small foreign object, and the bias of pressure application during bonding will be greatly influenced and reflected in the void. End up.
As for the influence of the film thickness of the metal bonding layer 11 on the bonding yield, the thicker the film, the better the result. However, as a matter of course, there is a limit to the yield, and even if the film thickness of the metal bonding layer 11 is increased, the yield improvement effect tends to be gradually saturated. Increasing the film thickness of the metal bonding layer 11 as it approaches the saturation state increases the disadvantage of raw material costs for LED manufacturing rather than improving the acquisition rate of LED elements, and is very advantageous. hard. Accordingly, the film thickness of the metal bonding layer 11 has an upper limit, and 3.0 μm is appropriate as a range in which a sufficient bonding yield can be obtained.
Furthermore, Au is suitable for the material constituting the metal bonding layer 11. In thermocompression bonding using metal as a bonding layer, various materials such as Ag and In can be used.
Since the bonding surface is difficult to oxidize and has a high melting point, it can be said that Au is a very suitable material for the metal bonding layer 11. Moreover, Au has a stronger bonding strength than when bonded by a metal bonding layer such as Ag or an Ag alloy. This is also one of the very important factors in manufacturing the replaceable LED. The upper limit film thickness of the metal bonding layer 11 is as described above. However, if the material of the metal bonding layer is Au, the raw material cost is very high, so the upper limit value becomes more important.

Fourth, the occupation area ratio of the interface electrode 8 is preferably 30% or less. Incidentally, the occupied area ratio of the interface electrode refers to the ratio of the surface area of the surface of the interface electrode in contact with the second main surface of the compound semiconductor layer to the surface area of the compound semiconductor layer at the second main surface. A part of the light emitted from the light emitting layer 5 is emitted to the outside from the first main surface of the compound semiconductor layer 14, but many other lights are on the second main surface side of the compound semiconductor layer 14, that is, metal light. It goes toward the reflective layer 9 and the interface electrode 8. Due to the configuration of the LED element, the metal light reflecting layer 9 has a good light reflectance (approximately 80% or more) with respect to the light emitted from the light emitting layer 5. In FIG. 5, the measurement result of the reflectance of Al, Ag, Au (used as the metal light reflection layer 9) with respect to light having a wavelength of 400 to 700 nm is shown.
However, the interface electrode 8 portion has a very low light reflectance (approximately 50% or less). This is a metal electrode provided for the interface electrode 8 to obtain ohmic contact with the compound semiconductor layer 14, and therefore generally forms an alloyed state with the compound semiconductor layer 14. It is known that the reflectivity of a metal alloyed with a semiconductor is lowered. For this reason, the interface electrode 8 is a region where light reflection characteristics cannot be expected. That is, for these reasons, if the occupied area ratio of the interface electrode 8 on the second main surface of the compound semiconductor layer 14 is too large, the output of the LED element is reduced. FIG. 6 shows the measurement results of the light emission output (mW) and the operating voltage (V) of the LED element with respect to the occupied area ratio (%) of the interface electrode.
From the above, in the manufacture of an LED element having good output characteristics, at least the occupation area ratio of the interface electrode 8 is preferably 30% or less, and more preferably 15% or less.

Fifth, the material of the dielectric layer 15 formed between the compound semiconductor layer 14 and the metal light reflection layer 9 is preferably SiO ₂ . The reason for this is that the formation of SiO ₂ is general and simple with respect to the formation of various dielectric films, and furthermore, extremely good transmission characteristics with respect to the light emitted from the light emitting element made of a compound semiconductor, that is, This is because of its low absorption loss. Further, the metal light reflection layer 9 has a feature that adhesion to a material used for example, Al, for example, is very strong, and voids at the bonding interface are not easily generated. From the above, it can be said that SiO ₂ is suitable for the material used for the dielectric layer 15.

  In the embodiment shown in FIG. 1, the AlGaInP active layer (light emitting layer) 5 is an undoped bulk layer, but the active layer (light emitting layer) 5 may have a multiple quantum well structure or a strained multiple quantum well structure. In the above embodiment, for example, the conductivity of the GaAs substrate used as the starting substrate is n-type, and the conductivity of the GaP contact layer 7 is p-type. Although the structure is adopted, the same effect can be obtained even if the conductivity of each layer is reversed so as to adopt a p-side-up structure.

Next, examples of the present invention will be described.
(Example)
A red LED element having the same cross-sectional structure as that of the above embodiment shown in FIG. 1 and having an emission wavelength of around 630 nm was produced. 2A and 2B show process diagrams of the manufacturing process of the LED element of this example.

  First, a red LED epitaxial wafer having an emission wavelength of about 630 nm and having the structure shown in FIG. 2A (a) was produced. The epitaxial growth method, the epitaxial layer thickness, the epitaxial structure, the electrode formation method, and the LED element manufacturing method are as follows.

An n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P etching stop layer (Si-doped, film thickness 200 nm, carrier concentration 1 is formed on an n-type GaAs substrate 1 having a diameter of 3 inches by MOVPE. × 10 ¹⁸ / cm ³ ) 2, n-type GaAs contact layer (Si doped, film thickness 100 nm, carrier concentration 1 × 10 ¹⁸ / cm ³ ) 3, n-type (Al _o.7 Ga _0.3 ) _0.5 In _0.5 P clad layer (Si-doped, film thickness 2.0 μm, carrier concentration 1 × 10 ¹⁸ / cm ³ ) 4, undoped (Al _0.1 Ga _0.9 ) _0.5 In _0.5 P active layer ( 500 nm thick) 5, p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P clad layer (Mg doped, 400 nm thick, carrier concentration 1.2 × 10 ¹⁸ / cm ³ ) 6, p-type GaP contact layer (Mg doped, film thickness 8
00 nm, carrier concentration of 1 × 10 ¹⁸ / cm ³ ) 7 were sequentially stacked and grown, and the compound semiconductor layer 14 was formed on the GaAs substrate 1 as a starting substrate. Here, “un-dope” means that dopant is not actively added, and inclusion of a dopant component inevitably mixed in a normal manufacturing process (for example, 10 ^13). 10 to 10 ¹⁶ / cm ³ is the upper limit).

Here, the growth parameters and the raw materials used for the compound semiconductor layer 14 were determined as follows. First, the growth temperature by the MOVPE method using the MOCVD apparatus is set to 650 ° C., the growth pressure is about 6666 Pa (50 Torr), the growth rate of each layer is 0.3 to 1.0 nm / sec, and the V / III ratio is about 200. It was. Incidentally, the V / III ratio referred to here is the ratio (quotient) when the denominator is the number of moles of a group III material such as TMGa or TMAl and the molecule is the number of moles of a group V material such as AsH ₃ or PH _3. Point to. Examples of raw materials for MOVPE growth include organometallic gases such as trimethylgallium (TMGa), triethylgallium (TEGa), trimethylaluminum (TMAl), and trimethylindium (TMIn), arsine (AsH ₃ ), and phosphine (PH ₃ ). A hydride gas such as was used. Disilane (Si ₂ H ₆ ) is used as an additive material for the conductivity type determining impurity of the n-type semiconductor layer, and biscyclopentadienyl magnesium (Cp) is used as an additive material for the conductivity type determining impurity of the p-type semiconductor layer. ₂ Mg) was used. In addition, hydrogen selenide (H ₂ Se), monosilane (SiH ₄ ), diethyl tellurium (DETe), or dimethyl tellurium (DMTe) can also be used as an additive material for the conductivity determining impurity of the n-type layer. In addition, dimethyl zinc (DMZn), diethyl zinc (DEZn), or the like can be used as a p-type additive material for the p-type layer.

Next, after this LED epitaxial wafer was unloaded from the MOCVD apparatus, a SiO ₂ film 15 of about 110 nm was formed on the surface of the p-type GaP contact layer 7 by a p-CVD (plasma CVD) apparatus (FIG. 2A (b)). ). Further, a general photolithography apparatus / technology such as a resist or a mask aligner is used, and an opening is formed in the SiO ₂ film 15 using a hydrofluoric acid etching solution diluted with pure water. The interface electrode 8 was formed by the vacuum evaporation method (FIG. 2A (c)). AuZn alloy (gold / zinc alloy, Au: 95 wt%, Zn: 5 wt%) was used as the material of the interface electrode 8. In addition, the interface electrode 8 is appropriately designed so as to be disposed in a region other than directly below the surface electrode 12 to be formed later. The arrangement of the interface electrode 8 is as follows.

In FIG. 3, the top view of the LED element (bare chip) 100 of a present Example is shown. As shown in FIG. 3, the surface electrode 12 of this embodiment is extended from a pad electrode 12 a having a diameter of 100 μm located at the center of the upper surface of the LED element 100 and four positions (disposed at 90 degrees) of the pad electrode 12 a. Further, it is composed of a thin wire electrode 12b having a length of 100 μm and a width of 15 μm. The interface electrode 8 has a circular dot shape with a cross section of 15 μm in diameter, and each interface electrode 8 is dispersed and arranged in a region portion that does not overlap with the region immediately below the surface electrode 12 when viewed from the upper surface of the light emitting diode 100. The interface electrode located in a portion overlapping with the surface electrode 12 when viewed from the first main surface of the LED element 100 is designed by removing in advance from the photomask design stage.
As shown in FIG. 3, the interface electrode 8 is arranged in a hexagonal close-packed structure with a pitch between the centers of adjacent interface electrodes 8 and 8 being 40 μm. That is, when a regular hexagon having a side of 40 μm was continuously drawn in a honeycomb shape on a plane, the interface electrode 8 was arranged at the apex and center of each regular hexagon.

  Next, 400 nm of Al (aluminum) was formed as the metal light reflecting layer 9 on the epitaxial wafer with the interface electrode 8 (FIG. 2A (c)) by vacuum deposition. Further, 50 nm of Pt (platinum) as the alloying barrier layer 16 and 500 nm of Au (gold) as the metal bonding layer 11a were sequentially formed on the metal light reflection layer 9 (FIG. 2A (d)).

  On the other hand, on the first main surface of the conductive p-type Si support substrate 10 having a diameter of 3 inches prepared as a conductive support substrate, a 250 nm Ti layer 18 is formed as an ohmic electrode / alloyed barrier layer by vacuum deposition. Further, an Au metal bonding layer 11b having a thickness of 500 nm was formed on the Ti layer 18 (FIG. 2B (e)).

The metal bonding layer 11a of the epitaxial wafer (FIG. 2A (d)) produced as described above and the metal bonding layer 11b of the Si support substrate (FIG. 2B (e)) are bonded together by a thermocompression bonding method. Bonding is performed by heating to a temperature of 350 ° C. with a pressure of 15 kgf / cm ² applied to the wafer in an atmosphere of about 1.33 Pa (0.01 Torr), and further heating and holding in that state for 30 minutes. A wafer was obtained (FIG. 2B (f)).

Next, the GaAs substrate 1 which is the substrate material of the epitaxial wafer bonded to the support substrate 10 is removed by wet etching using a mixed etchant of ammonia water and hydrogen peroxide solution, and n-type (Al _0.7 Ga _{0 .3} ) The _0.5 In _0.5 P etching stop layer 2 was exposed. Further, the etching stop layer 2 was removed by wet etching using hydrochloric acid to expose the n-type GaAs contact layer 3 (FIG. 2B (g)).

Next, a photolithography apparatus / technology was applied to the surface of the GaAs contact layer 3 to form the surface electrode 12 having the above-described shape by a vacuum deposition method. As for the structure of the surface electrode 12, AuGe (gold / germanium alloy), Ni (nickel), and Au (gold) were sequentially formed in thicknesses of 100 nm, 20 nm, and 600 nm, respectively. After the surface electrode 12 is formed, the n-type GaAs contact layer 3 other than directly below the surface electrode 12 is wet-etched using a mixed etchant of sulfuric acid, hydrogen peroxide water, and water, using the surface electrode 12 previously formed as a mask material. The n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P cladding layer 4 was exposed by this selective etching. Further, a back electrode 13 was formed on the entire surface of the second main surface of the Si support substrate 10 by the same vacuum deposition method. The back electrode 13 is formed by sequentially forming AuSn (gold / tin alloy), Pt (platinum), and Au (gold) in thicknesses of 250 nm, 50 nm, and 500 nm, respectively, and then performing an alloying process that is an alloying process of the electrodes. This was carried out with an alloy device equipped with independent upper and lower heaters. The alloying conditions were to heat up to 400 ° C. in a nitrogen gas atmosphere and heat-treat in that state for 5 minutes. The wafer was placed on a graphite tray, and the tray was placed on a lower plate with a lower heater built therein. After the alloying process, the replaceable LED epitaxial wafer formed as described above is cut using a dicing apparatus so that the circular pad portion of the surface electrode 12 is arranged at the approximate center, and the chip size is 300 μm square. 2 was produced (FIG. 2B (h)). FIG. 3 shows an external view of the LED element 100 viewed from the light extraction surface side, that is, the upper surface side.

Further, the LED element (bare chip) was mounted on the TO-18 stem 20 by die bonding and wire bonding to produce a state where the LED element could be energized (FIG. 2).
B (i)). 19 is an Au wire, and 21 is a pin.

When the initial characteristics of the LED element manufactured as described above were evaluated, the characteristics when energized with 20 mA (during evaluation) were as shown in Table 1. In FIG. 4, the evaluation position on the LED wafer of the LED element which evaluated the LED element characteristic of Table 1 is shown.

As shown in Table 1, all LED elements in the LED wafer surface were obtained with a high light emission output and a low operating voltage. Further, in this example, the alloying reaction and the melt phenomenon did not occur in the outer peripheral portion of the wafer even after the LED element fabrication process.
This is excellent in that the Ti layer 18 does not directly alloy with the Si support substrate 10 and the barrier effect that suppresses the Au—Si alloying reaction between the Au metal bonding layer 11 b and the Si support substrate 10. This means that the Ti layer 18 can be formed on the Si support substrate 10 with good adhesion, and good ohmic contact with the Si support substrate 10 can be obtained. Further, unlike known barrier materials such as Pt, they can be obtained at a low price as with Al and Ni. Furthermore, since the structure of the metal layer on the Si support substrate 10 side can be configured extremely simply, the manufacturing is easy, and the apparatus such as a vacuum vaporizer can reduce the number of evaporation sources and the like, so that it can be suppressed to an inexpensive configuration. As a result, the manufacturing cost of the replaceable LED can be kept low, and the LED can be manufactured with a high manufacturing yield.

  In addition, in the said Example, although the red LED element of 630 nm of light emission wavelength was produced, it is used also in other LED elements manufactured using the same AlGaInP type material, for example, LED elements of light emission wavelength of 560 nm to 660 nm. The material and carrier concentration of each layer to be used are the same, and in particular, the contact layer has no change. Therefore, it goes without saying that the same effect can be obtained even if the emission wavelength of the LED element is set to a wavelength band different from that of the above embodiment.

  In the above embodiment, the structure of the epitaxial layer composed of the compound semiconductor is composed of the AlGaInP etching stop layer 2, the GaAs contact layer 3, the AlGaInP cladding layers 4 and 6, the AlGaInP active layer 5, and the GaP contact layer 7. However, the structure is not particularly limited to these structures. In addition to these structures, a so-called intermediate layer having an intermediate composition is inserted, or a structure in which the contact layer is formed of another material is replaced. Even when the (distributed Bragg reflection layer) is inserted, the same effect can be obtained particularly when there is no significant difference in the relationship between the support substrate 10, the Ti layer 18, and the metal bonding layer 11 that is a feature of the present invention. It can be said that.

  In the above embodiment, the Ti layer 18 is formed on the first main surface of the Si support substrate 10 and the Au metal bonding layer 11 is formed thereon. For example, the Ti layer 18 and the Au metal bonding layer 11 are formed. It is also possible to adopt a structure in which a material that is difficult to alloy with Au, such as Pt, is inserted in a certain thickness.

(Comparative Example 1)
As Comparative Example 1, a red LED element having an emission wavelength near 630 nm and having the same structure as that of the above example was manufactured. Process steps such as epitaxial growth method, epitaxial layer thickness, epitaxial layer structure, interface electrode, metal light reflecting layer, Si substrate support, method of etching, LED device manufacturing method, etc. Although the same, in Comparative Example 1, the structure of the metal film formed on the first main surface of the Si support substrate 10 was configured as follows.

  On the first main surface of the Si support substrate 10, AuSn (gold / tin alloy), Pt (platinum), and Au (gold) were sequentially formed with film thicknesses of 250 nm, 50 nm, and 500 nm, respectively. The AuSn layer is an ohmic contact metal layer, the Pt layer is a diffusion barrier layer, and the Au layer is a metal bonding layer.

When the initial characteristics of the LED device fabricated as the above structure were evaluated in the same manner as in the above example, the results shown in Table 2 were obtained.

  After passing through the above LED element manufacturing steps, Au contained in the AuSn layer used as Au of the metal bonding layer or ohmic electrode in a large area of the epitaxial wafer for repositionable LED having a diameter of 3 inches, and Si support The phenomenon of floating of the epitaxial layer due to the alloying reaction with the Si of the substrate and the melting phenomenon has occurred. The area where this lift phenomenon occurs is severely alloyed and the LED characteristics are greatly deteriorated. Furthermore, since the surface observation state is significantly different from the area of the non-alloying reaction, the image recognition function is applied. It cannot be recognized by an inspection device such as a wafer prober. That is, the region where the above-described lifting phenomenon occurs is a portion having industrially insufficient characteristics as an LED element, and has an area equivalent to this region (having a variation of about 50 to 80% of a 3-inch wafer having a diameter). The yield was zero, and it was a loss.

(Comparative Example 2)
As Comparative Example 2, a red LED element having an emission wavelength near 630 nm and having the same structure as that of the above example was manufactured. Process steps such as epitaxial growth method, epitaxial layer thickness, epitaxial layer structure, interface electrode, metal light reflecting layer, Si substrate support, method of etching, LED device manufacturing method, etc. Although the same, in Comparative Example 2, the structure of the metal film formed on the first main surface of the Si support substrate 10 was configured as follows.

  On the first main surface of the Si support substrate 10, Al (aluminum), Pt (platinum), and Au (gold) were sequentially formed with thicknesses of 250 nm, 50 nm, and 500 nm, respectively. Here, the Al layer serves as an ohmic electrode with respect to the Si support substrate 10. The Pt layer also has an effect of suppressing the alloying reaction between Si constituting the Si support substrate 10 and Au as the metal bonding layer 11, but Al and Au are materials that are very easily alloyed. The purpose of suppressing the alloying reaction of Au is stronger.

When the initial characteristics of the LED device fabricated as the above structure were evaluated in the same manner as in the above example, the results shown in Table 2 were obtained.

In the case of the comparative example 2, unlike the comparative example 1, the alloying reaction and the melting phenomenon when the LED element manufacturing process is performed are suppressed only at the outer peripheral portion of the wafer, and the region is the outer periphery (edge portion) of the wafer. To about 6 mm. This area is a part having industrially insufficient characteristics as an LED element, and the yield of the area of this area (corresponding to about 30% of a 3-inch diameter wafer) is zero, which is a loss. The reason why the area of the loss area was suppressed as compared with Comparative Example 1 was that the Al layer formed immediately above the first main surface of the Si support substrate did not directly cause Si and melt reaction. It has become.
However, the reason why the melting phenomenon still occurs and the lift of the epitaxial layer occurs is that the Al layer and the Au metal bonding layer cause an alloying reaction, and Au diffuses close to the Al layer side, that is, the Si support substrate side. As a result, an alloying reaction between Au and Si occurred. That is, the Pt alloying barrier layer (thickness 50 nm) was insufficient to suppress the alloying reaction between the Al layer and the Au metal bonding layer.

Further, in the case of the replaceable LED element described in Comparative Example 2, the Au metal bonding layer and the Al layer on the first main surface side of the Si support substrate are alloyed depending on the heating temperature during the bonding process with the epitaxial wafer. It will cause chemical reaction. When an Au—Al alloy of Au and Al is generated, the diffusion reaction of Au metal atoms is not smoothly performed, and adversely affects the bonding failure to the thermocompression bonding of Au to each other. For this reason, in the case of the replaceable LED epitaxial wafer of Comparative Example 2, a defectively bonded portion was generated in a region other than the outer peripheral portion of the wafer. The defective bonding portion was in a state where the epitaxial layer transferred to the supporting substrate side was peeled off after the removal process by wet etching of GaAs, which was the starting substrate, and floated to cause voids. Since this void part (part of poor bonding) cannot be obtained as an LED element, the yield of LED element manufacturing is reduced.

(Comparative Example 3)
As Comparative Example 3, a red LED element having an emission wavelength near 630 nm and having the same structure as that of the above example was fabricated. Process steps such as epitaxial growth method, epitaxial layer thickness, epitaxial layer structure, interface electrode, metal light reflecting layer, Si substrate support, method of etching, LED device manufacturing method, etc. Although the same, in Comparative Example 3, the structure of the metal film formed on the first main surface of the Si support substrate 10 was configured as follows.

  On the first main surface of the Si support substrate 10, Ni (nickel) and Au (gold) were sequentially formed with film thicknesses of 250 nm and 500 nm, respectively. Here, the Ni layer plays the role of an ohmic electrode with respect to the Si support substrate 10, but it is known that the Ni layer also has an effect as an alloying barrier layer. In addition, Pt, which is a general barrier layer on the other side, is greatly different in terms of raw material costs, and is a material that can be obtained at a low price as in the case of Al. That is, the Ni layer is formed on the first main surface of the Si support substrate 10 and is provided to obtain ohmic contact with Si and at the same time suppress the alloying reaction between the Au metal bonding layer and the Si support substrate. Is.

When the initial characteristics of the LED device fabricated as the above structure were evaluated in the same manner as in the above example, the results shown in Table 4 were obtained.

In the case of this comparative example 3, the state is worse than that in the case of the above comparative example 1, and the alloying reaction and the melting phenomenon have occurred on almost the entire surface of the wafer after the LED element fabrication process. This region had industrially insufficient characteristics as an LED element, and the yield of the area of this region (corresponding to about 90% to 100% of a 3-inch diameter wafer) was zero, resulting in a loss. The reason why the area of the loss area is larger than that of the first comparative example is that Ni formed immediately above the first main surface of the Si support substrate is a material that is vigorously alloyed with Si. The diffusion force is very strong, and the alloyed region of Ni—Si reaches the part of the metal light reflection layer all at once. When the alloyed region erodes to the metal light reflection layer, the reflectance of the metal light reflection layer is remarkably lowered, and as a result, the light emission output of the LED element is greatly reduced.

It is sectional drawing which shows the structure of the LED element which concerns on embodiment of this invention. It is process drawing which shows a part of manufacturing process of the LED element of the Example of this invention. It is process drawing which shows a part of manufacturing process of the LED element of the Example of this invention. It is a top view of the LED element of the Example of this invention. It is the figure which showed the acquisition position of the LED element on the LED wafer which evaluated the characteristic with respect to the LED element of the Example of this invention, and a prior art example. It is a figure which shows the measured value of the light reflectivity in the various metal applicable to a metal light reflection layer. It is a figure which shows the result of having measured the relationship between the occupation area rate of the interface electrode in the LED element of embodiment of this invention, light emission output, and an operating voltage.

Explanation of symbols

1 n-type GaAs substrate (growth substrate)
2 n-type AlGaInP etching stop layer 3 n-type GaAs contact layer 4 n-type AlGaInP cladding layer 5 AlGaInP active layer 6 p-type AlGaInP cladding layer 7 p-type GaP contact layer 8 interface electrode 9 metal light reflection layer 10 Si support substrate (conductive Support substrate)
11 Au metal bonding layer 11a Growth substrate side metal bonding layer 11b Support substrate side metal bonding layer 12 Front electrode 13 Back electrode 14 Compound semiconductor layer 15 SiO ₂ film (dielectric layer)
16 Alloying barrier layer 18 Ti layer 19 Au wire 20 TO-18 stem 100 LED element

Claims (8)

A compound semiconductor layer having a light emitting layer portion;
A conductive support substrate for supporting the compound semiconductor layer;
A metal light reflection layer provided between the compound semiconductor layer and the conductive support substrate and reflecting light from the light emitting layer portion;
An interface electrode formed on a part of the bonding interface between the compound semiconductor layer and the metal light reflection layer;
A Ti layer formed in contact with the main surface of the conductive support substrate on the metal light reflection layer side;
A metal bonding layer made of Au formed in contact with the main surface of the Ti layer on the metal light reflection layer side;
A surface electrode formed on the first main surface side to be a light extraction surface of the compound semiconductor layer;
A back electrode formed on the main surface side opposite to the Ti layer of the conductive support substrate;
A semiconductor light emitting device comprising:   2. The semiconductor light emitting device according to claim 1, wherein the conductive support substrate is a Si substrate, and the resistivity of the Si substrate is 0.1 [Omega] .cm or less.   3. The semiconductor light emitting device according to claim 1, wherein the thickness of the Ti layer is 50 nm or more and 2 [mu] m or less.   4. The semiconductor light emitting device according to claim 1, wherein a thickness of the metal bonding layer is not less than 0.5 μm and not more than 3 μm.   5. The semiconductor light-emitting device according to claim 1, wherein the interface electrode is formed in an opening of a dielectric layer formed between the compound semiconductor layer and the metal light reflection layer. A semiconductor light emitting device, characterized in that the semiconductor light emitting element is a metal layer formed by connecting the second main surface of the metal light reflecting layer and the metal light reflecting layer.   6. The semiconductor light emitting device according to claim 1, wherein a ratio of a surface area of a surface where the interface electrode is in contact with a second main surface of the compound semiconductor layer to a surface area of the second main surface of the compound semiconductor layer is 6. 30% or less of a semiconductor light emitting device.   7. The semiconductor light emitting device according to claim 1, wherein the interface electrode is formed in a dispersed manner outside a region immediately below the surface electrode. The semiconductor light emitting device according to any one of claims 5 to 7, the semiconductor light-emitting device main component of the dielectric layer is characterized by a SiO _2.

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