JP2008257642A - Packet processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet processor, for rapidly receiving packets. <P>SOLUTION: The packet processor adapted to receive a packet from an external device through an NIC (network interface card) 20 by a plurality of CPUs a1-an comprises an OS 40 which sets a plurality of DMA receiving buffers b1-bn for receiving the packet DMA-transferred from the NIC 20 within a kernel space; and a packet receiving processing part 1 which receives the packet from the NIC 20 by a predetermined DMA receiving buffer based on an instruction from the OS 40 and transfers it to a host layer processing part 62. The processing part 1 changes setting of CPU for reporting interruption next and setting of DMA receiving buffer for receiving the packet next before starting the next DMA transfer from the NIC 20, and receives the packet by the set DMA receiving buffer in addition to interruption notice to the set CPU when the NIC 20 performs the next DMA transfer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a packet processing apparatus that receives a packet from a network interface device using a plurality of processors.

  In recent years, communication services using the Internet have appeared one after another, and the amount of IP traffic in the access network and the core network has been increasing year by year. As the amount of IP traffic increases, a wired network represented by the Ethernet (registered trademark) standard (IEEE (Institute of Electrical and Electronics Engineers) 802.3) and WiMAX (Worldwide Interoperability for Microwave Access) (IEEE 802.16). In a wireless network represented by (1), studies are being made to increase the transmission bandwidth. In particular, for wired communication, a 10 Gbps Ethernet (registered trademark) standard of 100 Mbps or 1 Gbps or higher has been established, and a network interface device (hereinafter referred to as NID) corresponding to 10 Gbps has already been commercialized.

  By the way, the CPU (Central Processing Unit) is also clocked up, and the performance of the multi-core processor / multiprocessor is increasing. However, in a communication device including a CPU and an NID equipped with an OS (Operating System), the CPU and the NID Packet transmission / reception between the two becomes a bottleneck and it is difficult to accommodate a high-speed transmission band such as 10 Gbps.

  A packet receiving process in a conventional communication apparatus configured with a CPU and NID equipped with a general-purpose OS will be described. In the packet reception process in this conventional communication apparatus, first, the OS determines a CPU to notify of an interrupt, and prepares a DMA reception buffer in the kernel space for storing a packet transferred from NID to DMA (Direct Memory Access). . A packet received from a PHY (physical layer) device is filtered by a MAC (Media Access Control) header, FCS (Frame Check Sequence) or the like, and transferred from the buffer in the NID to the DMA reception buffer. Thereafter, the NID notifies the CPU of a hardware ware (HW) interrupt in order to notify the CPU (OS) of the arrival of the packet.

  On the CPU side, the reception of a packet is confirmed by activating an interrupt handler and a network driver corresponding to the HW interrupt from the NID, and then control of packet processing is transferred to the upper protocol stack (for example, non-patent document) 1). A method of parallelizing packet reception processing by distributing HW interrupts to a plurality of CPUs has also been proposed (see, for example, Patent Document 1).

K. Salah, K. El-Badawi, "Performance evaluation of interrupt-driven kernels in gigabit networks," Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE, pp. 3953-3957 JP-A-8-36498 (page 3, FIG. 1)

  However, in the former prior art, in the sequence of packet reception processing, a delay in reception processing occurs due to thread generation and allocation during interrupt handler processing by the OS, network driver processing, and context switch generation by the OS. There was a problem of becoming a bottleneck of processing.

  In the former and latter prior arts, only one DMA receive buffer is prepared in the kernel space. Therefore, when receiving a packet, the DMA transfer is completed and the CPU receives an HW interrupt, and the packet by the network driver is received. The NID can start the next DMA transfer only after the reception process is completed. For this reason, there is a problem that it is impossible to parallelize reception processing only by distributing HW interrupts to a plurality of CPUs.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a packet processing apparatus that performs packet reception processing quickly.

  In order to solve the above-described problems and achieve the object, the present invention provides a packet processing apparatus in which a plurality of processors receive packets from an external apparatus via a network interface device, and performs DMA transfer from the network interface device. An OS storage unit that stores a plurality of OSs that are set in the kernel space as a DMA reception buffer, and a packet that is DMA-transferred from the network interface device is determined based on an instruction from the OS. A packet reception processing unit that receives the DMA reception buffer and transfers the packet to the upper layer side. The packet reception processing unit receives an interrupt notification for DMA transfer from the network interface device. Once the next DMA transfer is started Until then, the processor setting for the next interrupt notification is switched to another processor different from the currently set processor, and the DMA receive buffer setting for receiving the next DMA transfer packet is currently set. Switch to another DMA receive buffer different from the current DMA receive buffer, and when the network interface device performs the next DMA transfer, it notifies the other processor that has been set and notifies the interrupt. The packet is received by the other DMA reception buffer.

  According to the present invention, since the OS sets a plurality of DMA reception buffers for receiving DMA transferred packets in the kernel space, the DMA transferred packets can be received in parallel by the plurality of DMA reception buffers, There is an effect that packet reception processing can be performed quickly.

  Hereinafter, embodiments of a packet processing apparatus according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a packet processing apparatus according to Embodiment 1 of the present invention. FIG. 1 shows the flow of packet reception processing together with the configuration of the packet processing device (communication device) 101.

  The packet processing device 101 is a network device that executes transfer of communication packets such as IP packets and processing of higher layer protocols by an application on the OS. In the present embodiment, the packet processing apparatus 101 performs packet reception processing using a plurality of DMA reception buffers.

  The packet processing apparatus 101 includes a physical device 10, a network interface card (NIC) 20 that is a network interface device, an interrupt notification mechanism 30, an OS storage unit 4, and a packet reception processing unit 1.

  The physical device 10 is a device that transmits and receives IP packets (frames) to and from an external network device (not shown) via a physical layer (PHY layer). The physical device 10 is connected to the NIC 20 via the NIC-PHY IF 15.

  The NIC-PHY IF 15 is a communication interface between the physical device 10 and the NIC, such as GMII (Gigabit Media Independent Interface), XAUI (10 Gigabit Attachment Unit Interface), and XGMII (10 Gigabit Media Independent Interface). It is.

  The NIC 20 is a hardware network interface device specialized for packet processing, such as a general-purpose network interface card or ASIC / FPGA / NPU (Application Specific Integrated Circuit / Field Programmable Gate Array / Network Processing Unit). The NIC 20 receives a frame from the physical device 10 and performs mainly MAC layer processing (Ethernet (registered trademark) processing) as frame packet processing.

  The NIC 20 includes a MAC layer processing unit (MAC Block) 22 and a frame buffer 21. In the NIC 20, the MAC layer processing unit 22 performs processing related to the MAC layer protocol on the IP packet from the physical device 10. The frame buffer 21 is a buffer for storing frame data, and stores a frame sent from the MAC layer processing unit 22. The NIC 20 DMA-transfers the frame stored in the frame buffer 21 to the receiving unit 50 as a packet.

  The interrupt notification mechanism 30 exchanges data (such as an HW interrupt) between the NIC 20 and the receiving unit 50. The interrupt notification mechanism 30 performs processing for distributing HW interrupts from the I / O interface and various devices (NIC 20) to each processor (CPUa1 to CPUan described later) based on an instruction from the OS 40 described later.

  The OS storage unit 4 stores the OS 40. The OS 40 is a multicore processor and an OS compatible with the multiprocessor, and controls the NIC 20 and the interrupt notification mechanism 30 packet reception processing unit 1. The OS 40 according to the present embodiment is configured to recognize and use a plurality of CPUs in the same memory space.

  The packet reception processing unit 1 includes a reception unit 50, a plurality of queues c1 to cn, and a packet aggregation processing unit 60. The receiving unit 50 has a plurality of processor cores (processors). Each processor core includes a multi-core processor / multiprocessor-compatible CPU, a network driver, and a DMA receive buffer. In the present embodiment, the case where the receiving unit 50 is a multi-core processor will be described.

  In FIG. 1, CPUa1, DMA receive buffer b1, processor core having network driver d1, CPUa2, DMA receive buffer b2, processor core having network driver d2, CPUan (n is a natural number), DMA receive buffer bn, network driver dn The case where the receiving part 50 is comprised by the processor core which has is shown.

  The CPUs a <b> 1 to an generate an interrupt handler when receiving a HW interrupt notification from the interrupt notification mechanism 30. The interrupt handler generated by each of the CPUa1 to CPUan causes the network driver d1 to dn corresponding to its own CPU to perform reception processing of a packet transferred from the NIC 20 by DMA. In the present embodiment, the CPUs a <b> 1 to an are designated in turn by the interrupt notification mechanism 30, and receive HW interrupt notifications from the interrupt notification mechanism 30 in order.

  The DMA reception buffers b1 to bn are buffers for storing packets (frame data) in the CPU memory space (reception unit 50) recognized by the OS 40. Packets are transferred from the frame buffer 21 of the NIC 20 to the DMA reception buffers b1 to bn by, for example, DMA transfer without the CPUs a1 to an.

  After the HW interrupt notification is sent from the interrupt notification mechanism 30 to any of the CPUa1 to CPUan from the interrupt notification mechanism 30, the network drivers d1 to dn check the consistency of the received packet and send the packet data to the upper layer side (packet aggregation processing unit 60). Forward.

  The queues c1 to cn are packet buffer queues used for transfer to an upper layer, and are connected to the network drivers d1 to dn, respectively. The queues c1 to cn are connected to the packet aggregation processing unit 60.

  The packet aggregation processing unit 60 includes a packet aggregation mechanism (Packet Aggregation module) 61, an upper layer processing unit 62, and a plurality of CPUs 63. The packet aggregation mechanism 61 (control module) transfers the packets stored in the respective queues c1 to cn to the upper layer processing unit 62 based on the order of the queues to which the packets are transferred. After receiving the reception completion notification from the network driver d1, the packet aggregation mechanism 61 transfers the packet to the higher layer processing unit 62. The upper layer processing unit 62 performs upper layer processing on the packet received from the packet aggregation mechanism 61. The CPU 63 controls the packet aggregation mechanism 61 and the upper layer processing unit 62.

  Next, an operation procedure of the packet processing apparatus 101 will be described. FIG. 2 is a flowchart showing an operation procedure of the packet processing apparatus. The OS 40 of the packet processing apparatus 101 prepares a CPU for performing only reception processing and a plurality of DMA reception buffers in advance. The OS 40 of the present embodiment prepares CPUs a1 to an and DMA reception buffers b1 to bn.

  The OS 40 designates the DMA reception buffer b1 in the kernel space as a reception buffer for performing DMA transfer to the NIC 20 at the time of device initialization. Furthermore, the OS 40 designates the CPU a1 as the CPU that notifies the interrupt notification mechanism 30 of the HW interrupt from the NIC 20 (step S110).

  An IP packet from an external network device receives and terminates a physical signal at the physical device 10 and transmits it to the NIC 20 that performs MAC layer processing via the NIC-PHY IF 15 (specified interface). The NIC 20 receives the IP packet from the physical device 10 (step S120).

  The NIC 20 analyzes the MAC header in the MAC layer processing unit 22, performs frame verification and verification of the transmission destination / source address, and stores a frame to be transmitted to the upper layer in the apparatus in its own buffer (frame buffer 21) (Step S130).

  The NIC 20 DMA-transfers the frame stored in the frame buffer 21 to the DMA reception buffer b1 in the kernel space designated at the time of device initialization (step S140). Note that the number of DMA transfer packets (frames) to the DMA reception buffer in the kernel space depends on the specifications and parameter settings of the NIC 20, and a plurality of packets may be DMA transferred together.

  The NIC 20 notifies the interrupt notification mechanism 30 of a HW interrupt after a predetermined time has elapsed from the start of DMA transfer or when the number of packets transferred by DMA reaches a predetermined number of packets (step S150). When receiving the notification of the HW interrupt from the NIC 20, the interrupt notification mechanism 30 notifies the CPU a1 designated by the OS 40 of the HW interrupt (step S160).

  When the CPU a1 receives the HW interrupt, it generates an interrupt handler. At this time, the OS 40 causes the interrupt notification mechanism 30 to change the CPU that notifies the next HW interrupt to the CPU a2. Further, the OS 40 causes the NIC 20 to change the reception buffer for performing the next DMA transfer from b1 in the kernel space to the DMA reception buffer b2 (step S170).

  In other words, the OS 40 receives the interrupt notification for the DMA transfer from the NIC 20 and before the next DMA transfer is started, the CPU a1 that is currently set as the CPU to notify the next interrupt is set. It is switched to another CPUa2 different from the above. At this time, the OS 40 switches the setting of the DMA reception buffer for receiving the next DMA-transferred packet to another DMA reception buffer b2 different from the currently set DMA reception buffer b1.

  After the switching to the CPU a2 and the switching to the DMA reception buffer b2 are completed, the NIC 20 starts DMA transfer to the DMA reception buffer b2. Thereafter, the CPU and the DMA reception buffer are changed in round robin after notification of the HW interrupt. That is, the packet processing apparatus 101 repeats the same processing as steps S110 to 170. Specifically, every time the OS 40 receives a HW interrupt from the NIC 20, the OS 40 changes the CPU that notifies the HW interrupt to the interrupt notification mechanism 30 in the order of CPUa3, CPUa4, and CPUan. Further, the OS 40 causes the NIC 20 to change the reception buffer for performing DMA transfer in the order of the DMA reception buffer b3, the DMA reception buffer b4, and the DMA reception buffer bn.

  In other words, the OS 40 causes the interrupt notification mechanism 30 to change the CPU that notifies the HW interrupt in the order of CPUam (m is a natural number from 1 to n) to a (m + 1). Also, the OS 40 causes the NIC 20 to change the reception buffer for performing DMA transfer in the order of the DMA reception buffers bm to b (m + 1).

  In the reception unit 50, the interrupt handler causes the network driver d1 to perform reception processing. The network driver d1 acquires frame information from the DMA reception buffer b1. Then, the network driver d1 uses the frame of the DMA reception buffer b1 to generate packet data (socket buffer) in a format that can be managed inside the OS 40, and queues it in the queue c1 for upper layer transfer. When the reception process (queuing to the queue c1) is completed, the network driver d1 notifies the packet aggregation mechanism 61 of the packet aggregation processing unit 60 that the reception process has been completed (reception completion notification).

  Information on the order of queues to which packets are transferred from the OS 40 is given to the packet aggregation mechanism 61 in advance. Upon receiving the reception completion notification from the network driver d1, the packet aggregation mechanism 61 transfers the packets stored in the respective queues c1 to cn to the upper layer side (upper layer processing unit 62) based on the queue order information. . At this time, the packet aggregation mechanism 61 is controlled by a CPU 63 (SW (Soft Ware) interrupt handler).

  In the present embodiment, the HW interrupt is notified in the order of CPUa1 to CPUan, and the reception buffer for performing DMA transfer is specified in the order of DMA reception buffers b1 to bn. Therefore, the OS 40 is in the order of queues c1 to cn. The packet aggregation mechanism 61 is instructed to transfer the packet.

  The packet aggregation mechanism 61 transfers the packet stored in the queue c1 to the upper layer (upper layer processing unit 62). At this time, the packet aggregation mechanism 61 does not transfer the packets stored in the queues c2 to cn to the upper layer processing unit 62 until the packets stored in the queue c1 are transferred to the upper layer.

  The NIC 20 notifies the CPU a2 of an HW interrupt after completing the DMA transfer to the DMA reception buffer b2. When the CPU a2 receives the HW interrupt, the CPU a2 generates an interrupt handler and causes the network driver d2 to perform packet reception processing.

  In other words, when the NIC 20 performs the next DMA transfer, an interrupt notification is sent to another CPU a 2 different from the CPU a 1 set until the next DMA transfer is started, and the next DMA transfer starts. The packet is received by another DMA reception buffer b2 that is different from the DMA reception buffer b1 that has been set up until then.

  When this process is repeated to notify the CPUan of the HW interrupt, the OS 40 changes the CPU that notifies the HW interrupt next to the CPUa1 and changes the DMA reception buffer to the DMA reception buffer a1.

  FIG. 3 is a diagram for explaining a procedure of packet reception processing by the CPU. FIG. 3 shows the processing timing of the interrupt processing (interrupt handler generation, etc.) of each of the CPUs a1 to ann, the CPU and DMA reception buffer switching processing that notifies the HW interrupt, and the packet reception processing.

  When the first DMA transfer is performed from the NIC 20 to the receiving unit 50, the interrupt notification mechanism 30 notifies the CPU a1 designated by the OS 40 of the HW interrupt. When receiving the HW interrupt, the CPU a1 generates an interrupt handler (interrupt processing).

  The OS 40 changes the CPU that notifies the HW interrupt next from the CPU a1 to the CPU a2, and also changes the reception buffer that performs the next DMA transfer from the DMA reception buffer b1 to the DMA reception buffer b2 (switching process). When the switching process is completed, the NIC 20 starts DMA transfer to the DMA reception buffer b2, and the interrupt handler of the CPU a1 causes the network driver d1 to perform packet reception processing.

  As in the case of the CPUa1, when the next DMA transfer is performed from the NIC 20 to the receiving unit 50, the interrupt notification mechanism 30 notifies the CPUa2 designated by the OS 40 of the HW interrupt. When receiving the HW interrupt, the CPU a2 generates an interrupt handler (interrupt processing).

  The OS 40 changes the CPU that notifies the HW interrupt next from the CPUa2 to the CPUa3, and changes the reception buffer for performing the next DMA transfer from the DMA reception buffer b2 to the DMA reception buffer b3 (switching process). When the switching processing is completed, the NIC 20 starts DMA transfer to the DMA reception buffer b2, and the interrupt handler of the CPU a2 causes the network driver d2 to perform packet reception processing.

  As in the case of the CPUs a1 and a2, when the next DMA transfer is performed from the NIC 20 to the receiving unit 50, the interrupt notification mechanism 30 notifies the CPU a3 designated by the OS 40 of the HW interrupt. When receiving the HW interrupt, the CPUa3 generates an interrupt handler (interrupt process).

  The OS 40 changes the CPU that notifies the HW interrupt next from the CPU a3 to the next CPU, and changes the reception buffer for performing the next DMA transfer from the DMA reception buffer b3 to the next DMA reception buffer (switching process). When the switching processing is completed, the NIC 20 starts DMA transfer to the DMA reception buffer b3, and the interrupt handler of the CPU a3 causes the network driver d3 to perform packet reception processing.

  Thereafter, as in the case of the CPUs a1 to a3, the CPU interrupt processing, the CPU and DMA reception buffer switching processing for notifying the HW interrupt, and the packet reception processing by each CPU are repeated.

  With the above operation, it is possible to shorten the time for interrupt handler processing, task scheduling processing, and network driver processing performed by the OS 40 when receiving an interrupt-based packet. Thereby, high-speed packet reception processing can be realized.

  Note that the DMA transfer start timing by the NIC 20 and the packet reception start timing by the CPU interrupt handler need not be the same timing, and the timing may be shifted.

  As described above, according to the first embodiment, since the plurality of DMA reception buffers b1 to bn are provided in the kernel space, the next DMA transfer is performed while the CPU that has received the interrupt is performing reception processing. And an interrupt notification to the next CPU. Therefore, since the same kind of interrupts can be processed in parallel by a plurality of CPUs, packet reception processing can be performed quickly.

  Further, since the packet aggregation mechanism 61 transfers the packets stored in the respective queues c1 to cn to the upper layer processing unit 62 based on the order of the queues to which the packets are transferred, It is possible to prevent the order from being reversed.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, a CPU with a low processing load is selected from CPUs that are not performing packet reception processing, and a HW interrupt is notified.

  FIG. 4 is a block diagram showing the configuration of the packet processing apparatus according to Embodiment 2 of the present invention. FIG. 4 shows the flow of packet reception processing together with the configuration of the packet processing device (communication device) 102. Among the constituent elements in FIG. 4, constituent elements that achieve the same functions as those of the packet processing apparatus 101 of the first embodiment shown in FIG. 1 are assigned the same numbers, and redundant descriptions are omitted.

  The packet processing device 102 has a CPU load determination mechanism 31 in addition to the functions of the packet processing device 101. The CPU load determining mechanism 31 is connected to the CPUs a <b> 1 to an and the interrupt notification mechanism 30, and manages information (load information) regarding the loads of the CPUs a <b> 1 to an. This load information includes information on whether or not each of the CPUs a1 to an is performing reception processing in addition to the information about the loads of the CPUs a1 to an. The CPU load determination mechanism 31 sends load information to the interrupt notification mechanism 30 when the interrupt notification mechanism 30 selects a CPU that notifies the HW interrupt.

  Next, an operation procedure of the packet processing apparatus 102 will be described. Since the interrupt notification mechanism 30 is the same as the processing procedure of the packet processing apparatus 101 according to the first embodiment described in FIG. 2 except for the CPU changing process for notifying the HW interrupt, the description thereof is omitted.

  When the packet processing apparatus 102 performs packet reception processing, the CPU load determination mechanism 31 acquires load information of each CPU a <b> 1 to an from each CPU a <b> 1 to an. The CPU load determination mechanism 31 transmits the acquired load information to the interrupt notification mechanism 30.

  When selecting the CPU that notifies the HW interrupt, the interrupt notification mechanism 30 selects a CPU that is not performing reception processing and that has a low CPU load (for example, a CPU with the lowest processing load). Specifically, the interrupt notification mechanism 30 selects a CPU that notifies the HW interrupt based on the load information acquired by the CPU load determination mechanism 31 from each of the CPUs a1 to an.

  The receiving unit 50 assigns a specific CPU 63 to the packet aggregation mechanism 61 as a reception order control process when the packet aggregation mechanism 61 receives packets from the queues c1 to cn. Then, the packet aggregation mechanism 61 monitors the state of each of the queues c1 to cn (whether or not a packet is stored) by polling each of the queues c1 to cn, and the monitoring result (the queue used for packet reception). The order of packet reception is controlled based on the order of In this embodiment, since the packet aggregation mechanism 61 polls each of the queues c1 to cn, the network driver d1 performs the packet aggregation mechanism 61 when queuing to the queues c1 to cn is completed. There is no need to notify the reception completion notification.

  For example, when the order of the queues used for packet reception is the order of the queue c1 and the queue c3, the packet aggregation mechanism 61 transfers the packet from the queue c1 to the upper layer processing unit 62 and then the packet from the queue c3. Transfer to upper layer processing unit 62.

  In the present embodiment, the interrupt notification mechanism 30 selects the CPU that notifies the HW interrupt based on the load information of each of the CPUs a1 to an. However, even if the CPU that notifies the HW interrupt is selected by other methods. Good.

  For example, an interrupt notification mechanism 30 that can change a CPU that performs an interrupt notification without receiving a CPU change instruction from the OS 40 and a NIC 20 that can change a DMA reception buffer without receiving a DMA reception buffer change instruction from the OS 40 are used.

  In this case, the OS 40 provides the interrupt notification mechanism 30 with information on the CPUs a1 to an that may perform the HW interrupt notification in advance. In addition, the OS 40 provides the NIC 20 with information on a plurality of DMA reception buffers b1 to bn prepared in the kernel space.

  The NIC 20 notifies the interrupt notification mechanism 30 of a HW interrupt after a predetermined time has elapsed from the start of DMA transfer or when the number of packets transferred by DMA reaches a predetermined number of packets.

  When the NIC 20 notifies the interrupt notification mechanism 30 of the HW interrupt, based on the information of the DMA reception buffers b1 to bn, the NIC 20 changes the DMA reception buffer in the kernel space for performing the DMA transfer to another DMA reception buffer (next DMA reception buffer). Change to (Receive buffer) and start DMA transfer. At this time, the NIC 20 may change the next DMA reception buffer based on the load information of the CPUs a <b> 1 to an acquired by the CPU load determination mechanism 31.

  When the NIC 20 notifies the interrupt notification mechanism 30 of the HW interrupt, for example, the NIC 20 notifies the interrupt notification mechanism 30 of information on the DMA reception buffer after the change (next DMA reception buffer).

  When the interrupt notification mechanism 30 receives the notification of the HW interrupt from the NIC 20, the CPU that notifies the next time of the HW interrupt based on the information of the CPUa1 to an given from the OS 40 and the information related to the next DMA reception buffer is set as another CPU. (Next CPU) Change.

  Specifically, the interrupt notification mechanism 30 sets the CPU corresponding to the next DMA reception buffer as the CPU that notifies the next HW interrupt. For example, when the next DMA reception buffer is the DMA reception buffer b3, the interrupt notification mechanism 30 sets the CPU a3 corresponding to the DMA reception buffer b3 as the CPU that notifies the HW interrupt next time.

  Note that the interrupt notification mechanism 30 may determine the CPU to notify the HW interrupt next time and transmit the determined CPU information to the NIC 20. In this case, the NIC 20 sets the DMA reception buffer corresponding to the CPU information determined by the interrupt notification mechanism 30 as the next DMA reception buffer.

  In this embodiment, the case where DMA transfer is sequentially performed to each of the DMA reception buffers b1 to bn has been described. However, the DMA transfer may be performed to the DMA reception buffers b1 to bn by other procedures.

  For example, an interrupt notification mechanism 30 that simultaneously notifies a plurality of CPUs of the same HW interrupt when an HW interrupt is received, and an NIC 20 that can change the DMA reception buffer without receiving an instruction to change the DMA reception buffer from the OS 40 are used. .

  In this case, the NIC 20 performs DMA transfer in a round robin manner for each of a plurality of DMA reception buffers prepared from the OS 40 by a predetermined number of packets (for example, one packet). Specifically, the NIC 20 sends an HW interrupt to the interrupt notification mechanism 30 after a predetermined time has elapsed from the start of DMA transfer or when the number of DMA transferred packets reaches a predetermined number of packets (for example, all packets). To be notified. Then, when receiving the HW interrupt, the interrupt notification mechanism 30 notifies the CPU a1 to an corresponding to the DMA reception buffers b1 to bn all at once.

  When the packet aggregation mechanism 61 receives a reception completion notification from each of the network drivers d1 to dn, based on the queue order information given from the OS 40, the top packet stored in each of the queues c1 to cn The packet is transferred to the (upper layer processing unit 62) by round robin.

  As described above, according to the second embodiment, a CPU that does not receive a packet among processor CPUs and that has a low processing load is selected and HW interrupt notification is made. It becomes possible to perform packet reception quickly.

  Further, the NIC 20 switches the DMA reception buffer for receiving a packet next based on information given in advance from the OS 40 (information on the DMA reception buffers b1 to bn prepared in the kernel space). It is not necessary to send an instruction to change the DMA reception buffer from the OS 40 to the NIC 20 each time. Therefore, the processing load on the OS 40 is reduced.

  Further, since the interrupt notification mechanism 30 switches the CPU that performs the next interrupt notification based on information given in advance from the OS 40 (information of the CPUs a1 to an that may perform the HW interrupt notification), the interrupt notification mechanism 30 performs the HW interrupt notification. It is not necessary to send an instruction to change the CPU from the OS 40 to the NIC 20 each time. Therefore, the processing load on the OS 40 is reduced.

  Further, since the NIC 20 performs DMA transfer of a predetermined number of packets to each of the DMA reception buffers b1 to bn in a round-robin manner, and notifies each CPU a1 to an interrupt after the DMA transfer is completed, each of the DMA reception buffers b1 to b1. Control of bn and each of the CPUs a1 to an is facilitated.

  The packet aggregation mechanism 61 monitors each queue c1 to cn by polling each queue c1 to cn, and controls the order of packet reception based on the monitoring result. There is no need to provide information on the order of queues to which packets are transferred. Therefore, the load on the OS 40 can be reduced.

  As described above, the packet processing apparatus according to the present invention is suitable for receiving packets from the network interface device.

1 is a block diagram illustrating a configuration of a packet processing device according to a first embodiment. It is a flowchart which shows the operation | movement procedure of a packet processing apparatus. It is a figure for demonstrating the procedure of the reception process of the packet by CPU. FIG. 6 is a block diagram illustrating a configuration of a packet processing device according to a second embodiment.

Explanation of symbols

1 Packet reception processing unit 4 OS storage unit 10 Physical device 15 NIC-PHY interface
20 NIC
21 Frame buffer 22 MAC layer processing unit 30 Interrupt notification mechanism 31 Load determination mechanism 40 OS
DESCRIPTION OF SYMBOLS 50 Receiving part 60 Packet aggregation process part 61 Packet aggregation mechanism 62 Upper layer process part 101,102 Packet processing apparatus a1-an, 63 CPU
b1 to bn DMA reception buffer c1 to cn queue d1 to dn network driver

Claims (6)

In a packet processing apparatus that receives packets from an external device via a network interface device by a plurality of processors,
An OS storage unit for storing an OS that sets a plurality of buffers in a kernel space as a DMA reception buffer that receives a DMA transfer packet from the network interface device;
A packet reception processing unit that receives a DMA transfer packet from the network interface device by a predetermined DMA reception buffer based on an instruction from the OS and transfers the packet to an upper layer side;
With
The packet reception processing unit
What is the currently set processor after receiving an interrupt notification for DMA transfer from the network interface device and before the next DMA transfer is started? The network interface is switched to another different processor and the DMA reception buffer for receiving the next DMA transferred packet is switched to another DMA reception buffer different from the currently set DMA reception buffer. When the device performs the next DMA transfer, an interrupt is notified to the other processor that has been set and the packet is received by the other DMA reception buffer that has been set Processing equipment.   The packet reception processing unit includes a control module that acquires the packets from the queue and transfers them to an upper layer side in a queue order to which packets received by the DMA reception buffer are transferred. 2. The packet processing device according to 1.   The packet reception processing unit is a processor that does not perform packet reception processing among the processors when the setting of the processor that notifies the next interrupt is switched to another processor different from the currently set processor. 3. The packet processing apparatus according to claim 1, wherein a processor having the lowest processing load is selected and set to the other processor. An interrupt notification mechanism for receiving an interrupt notification for DMA transfer from the network interface device and notifying a predetermined processor based on an instruction from the OS of an interrupt from the network interface device;
The network interface device switches the setting of the processor to be notified of the next interrupt based on information previously given from the OS, and the interrupt notification mechanism is next configured to perform DMA based on the information previously given from the OS. The packet processing apparatus according to claim 1, wherein the setting of a DMA reception buffer that receives a packet to be transferred is switched.   2. The network interface device according to claim 1, wherein a predetermined number of packets are DMA-transferred in a round robin manner to each of the DMA reception buffers, and an interrupt is notified to each of the processors after the DMA transfer is completed. 3. The packet processing device according to 2.   5. The control module according to claim 2, wherein the control module monitors each of the queues by polling the queue, and performs packet reception order control based on the monitoring result. 6. Packet processing equipment.

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