JP2007088709A - Packet communication apparatus and processing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet communication apparatus capable of making communication through transmission/reception of packet data in a network system such as a LAN and to provide a processing method thereof. <P>SOLUTION: The packet communication apparatus 10 includes: an ordinary buffer 26 which a main control section 12 uses for data processing; and a processing buffer 24 which an accelerator 22 uses for encryption/decryption processing, integrally configures a MAC 20 and the accelerator 22, and the MAC 20 discriminates whether or not a received packet is an emergent packet, transfers the received packet to the processing buffer 24 when the received packet is the emergent packet, or transfers the received packet to the ordinary buffer 26 under the control of a DMA control section 18 in the other cases, and further the MAC 20 transmits an interruption IRQ 2 to the main control section 12 in response to the transfer of the emergent packet, and the main control section 12 preferentially applies data processing to the emergent packet in the processing buffer 24 in response to the interruption IRQ 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a packet communication apparatus capable of transmitting and receiving packet data in a network system such as a LAN, and a processing method thereof.

  2. Description of the Related Art Conventionally, in a network system such as a LAN (Local Area Network), data is exchanged by connecting devices such as a personal computer (PC) and a printer with wiring such as a twisted pair cable. Among LAN communication control methods, Ethernet (registered trademark) is widely used as a standard network equipped in a PC using a NIC (Network Interface Card). Ethernet is a LAN standard that was devised by Xerox and DEC in the United States and standardized by the IEEE802.3 committee. Today, Ethernet is a fast Ethernet with a communication speed of 100 Mbps (Fast Ethernet) and Gigabit Ethernet ( (Gigabit Ethernet).

  In addition, conventional communication devices used in LANs have a direct memory access (DMA) controller, media access controller (MAC), encryption / decryption accelerator, and bus arbiter connected to the internal bus. Some hardware is configured. This communication device stores data in packets as communication units (hereinafter referred to as packets) in transmission / reception buffers and processes them by application programs. The DMA controller and MAC realize packet transfer between the LAN and transmission / reception buffers. ing.

  In this communication apparatus, a structure called a descriptor is provided in a memory in advance, and the array of the descriptor is transferred to the MAC to perform packet DMA transfer.

  The MAC receives packets addressed to itself from a high-speed LAN such as high-speed Ethernet. Normally, the maximum data amount of a packet is about 1514 bytes, so the MAC has a FIFO memory of about several kilobytes and is a received packet. Can be temporarily held. When the MAC receives the packet, it sends a reception notification to the DMA controller.

  The DMA controller controls DMA transfer, and transfers a packet received by the MAC to a reception buffer on the memory via the internal bus based on the reception descriptor in response to a reception notification from the MAC. When the amount of data in the reception buffer reaches a predetermined threshold as a result of the DMA transfer, the DMA controller sends an interrupt (Interrupt ReQuest: IRQ) to the CPU (Central Processing Unit) of the communication device.

  In response to the interrupt IRQ from the DMA controller, the CPU processes the packets stored in the reception buffer in the order of storage.

  In addition, when the packet encryption / decryption processing is necessary in this data processing, the CPU causes an encryption / decryption accelerator such as DESA (Data Encryption Standard Accelerator) to perform the encryption / decryption processing. DESA is usually composed of hardware and performs 64-bit or 128-bit encryption / decryption processing at high speed. The processing conditions for encryption / decryption processing in DESA are application programs executed by the CPU. Is set.

  For example, when decrypting an encrypted packet, the packet is transferred from the reception buffer to the DESA processing buffer, the DESA decrypts the packet on the processing buffer, and the decrypted packet is further processed. Transfer again to the receive buffer.

  In addition, when transmitting a packet in a conventional communication device, the packet to be transmitted is stored in a transmission buffer by data processing by an application program, and DMA-transferred based on the transmission descriptor by the DMA controller. The data is transferred to the MAC and then transmitted from the MAC to the high-speed LAN.

  If it is necessary to encrypt the packet to be transmitted, this packet is transferred from the transmission buffer to the DESA processing buffer, DESA encrypts this packet on the processing buffer, and then the encrypted packet. Is transferred again to the send buffer.

  In this communication apparatus, the CPU bus and the control bus are shared, and the processing by the CPU between the memory and the DESA and the packet DMA transfer processing are performed in a time division manner.

  By the way, in the data transfer device described in Patent Document 1, when a data transfer with a high priority is requested to the DMA control circuit, the DMA control circuit temporarily suspends the data transfer with a low priority and the status at the time of the interruption. Is stored in the address register and the current transfer amount register, and the DMA control circuit has a low priority corresponding to the status stored in the address register and the current transfer amount register when the high-priority data transfer ends. Data transfer can be resumed.

JP-A-6-131294

  However, the conventional DMA transfer method has an effect of improving the throughput of the entire system, but has a high priority and it is difficult to process a packet that must be processed urgently. For example, voice data transmitted / received by VoIP (Voice over Internet Protocol) is known as a packet that has to be processed urgently because the transfer rate is low but the time delay causes quality degradation.

  In the conventional DMA transfer method, the CPU performs data processing in the order of transfer to the transmission / reception buffer and accumulation without determining whether the packet is a priority packet. As described above, the priority packet DMA transfer and data processing are not preferentially performed, and therefore there is a problem that the processing speed of the priority packet is delayed due to an increase in transfer data accompanying an increase in speed of the LAN and an increase in the functionality of the network device.

  For example, in a conventional communication device, three normal packets that do not require urgent processing are sequentially received, and priority packets that require urgent processing are received after receiving the second normal packet and before receiving the third normal packet. Receive. At this time, the DMA controller DMA-transfers this priority packet from the MAC to the reception buffer, and stores it after the second normal packet. In this way, the received packet is stored in the reception buffer in the order in which it is DMA-transferred and received by the DMA controller, regardless of whether it is a normal packet or a priority packet.

  Therefore, regardless of whether the packet received by this communication device is a normal packet or a priority packet, the CPU processes the data in the order in which it is stored in the reception buffer. Done using.

  Further, a packet to be encrypted / decrypted by data processing by the CPU is usually cut out from a transmission / reception buffer in the memory a plurality of times and transferred to a processing buffer in DESA. Thereafter, the packet encrypted / decrypted by DESA needs to be transferred again to the transmission / reception buffer. As described above, in the encryption / decryption processing, a burden is caused by packet transfer between the transmission / reception buffer and the processing buffer, which not only reduces the use efficiency of the internal bus, but also significantly reduces the data processing throughput of the entire system. is there.

  In network equipment that performs packet transfer processing, there is hardware with a structure that has a memory queue according to the priority of packets and high-speed DSP processing, but it is costly to apply this structure to general terminals. high.

  In addition, when a prioritized packet requiring urgent processing is transmitted in a conventional communication apparatus, it is necessary to wait for processing of the prioritized packet until transmission of a packet already transferred by DMA ends. Note that even if the transfer between the MAC and the DESA is a separate DMA transfer, the transfer may interfere with the emergency processing performed by the CPU. In addition, when transmitting priority packets, it is particularly important for data that requires real-time performance, in which it is important to transmit the packets at a constant interval while suppressing fluctuations in the transmission interval.

  Conventionally, the processing content on the network equipment side such as routers has been a major technical issue, but considering the higher functionality on the network equipment side, the quality of VoIP communication (Quality of Service: QoS) on the terminal side ) Is a key issue.

  Furthermore, today, there is a growing demand for security communications such as data encryption. For example, in IPv6 (Internet Protocol Version 6) of the next generation network, IPSec (IP Security), which was not popular in communications between IPv4 terminals, is the standard. It is adopted as.

  The present invention eliminates such drawbacks of the prior art, supports transmission / reception of encrypted emergency packets in communication with network devices, and processes emergency packets to be transmitted / received while maintaining high communication quality (QoS). It is an object of the present invention to provide a packet communication apparatus and a processing method thereof that are accelerated.

  In order to solve the above-mentioned problem, the present invention transfers main packet transmission / reception packets stored in the normal buffer to the normal buffer and transfers the received packets from the outside to the normal buffer. A medium access controller for transmitting to the memory, direct memory access control means for controlling transfer of these transmission / reception packets between the normal buffer and the media access controller, and direct memory access transfer without going through the main control means, and processing A packet communication device including an accelerator that decrypts and encrypts these transmission / reception packets stored in the buffer is configured by integrating the media access controller and the accelerator, and the media access controller Including first determination means for determining whether or not the packet is an urgent packet whose data should be urgently processed by the main control means, and as a result, if the packet is an urgent packet, the received packet is transferred to the processing buffer. Then, the first interrupt is sent to the main control means. Otherwise, the received packet is transferred to the normal buffer as a normal packet. The main control means responds to the first interrupt by Data processing is performed preferentially on received packets that are urgent packets.

  In addition, the main control means for processing the transmission / reception packet stored in the normal buffer, the media access controller for transferring the received packet from the outside to the normal buffer, and transmitting the transmission packet in the normal buffer to the outside, and the normal control The direct memory access control means for controlling the transfer of these transmission / reception packets between the buffer and the media access controller and direct memory access transfer without going through the main control means, and these transmission / reception packets stored in the processing buffer A packet communication apparatus including an accelerator that performs decryption and encryption processing is configured by integrating the media access controller and the accelerator, and the main control unit is an emergency packet that is an emergency packet that is to be subjected to data processing urgently. Second determination means for determining whether or not the packet is an urgent packet, the transmission packet is transferred to the processing buffer; otherwise, the transmission packet is transferred as a normal packet. Further, the transmission packet is preferentially processed, and a priority packet transmission command is sent to the media access controller. The media access controller sends the emergency packet transmission packet in response to the priority packet transmission command. The transmission is preferentially performed.

  Also, a first received packet transfer step for transferring a received packet received from the outside to the normal buffer by the media access controller, and a first control for processing the received packet stored in the normal buffer by the main control unit A data processing step, a transfer control step for controlling transfer of the received packet between the normal buffer and the media access controller by the direct memory access control unit, and direct memory access transfer without going through the main control unit; The packet processing including the decoding step of decoding the received packet stored in the buffer by the accelerator uses the integrated media access controller and the accelerator, and the received packet is urgently transmitted by the main control means. Urgent packet to be processed A second received packet transfer step of transferring the received packet to the processing buffer when the received packet is an urgent packet, as a result, A first determination step of sending an interrupt to the main control unit; otherwise, transferring the received packet as a normal packet to the normal buffer by a first received packet transfer step; and in response to the first interrupt And a second data processing step of preferentially processing the received packet, which is an emergency packet, in the main control unit.

  Also, a third data processing step for processing the transmission packet stored in the normal buffer by the main control unit, and a first transmission packet for transmitting the transmission packet in the normal buffer to the outside by the media access controller A transfer process, a transfer control process in which transfer of the transmission packet between the normal buffer and the media access controller is controlled by the direct memory access control unit, and direct memory access transfer is performed without going through the main control unit; A packet processing method including an encryption step of encrypting the transmission packet stored in the buffer with an accelerator, using the integrated media access controller and the accelerator, and a third data processing step includes: The transmitted packet must be processed urgently. A second determination step of determining whether or not the packet is an urgent packet, and as a result, a second transmission packet transfer step of transferring the transmission packet to the processing buffer if the packet is an urgent packet; In this case, the transmission packet is transferred to the normal buffer as a normal packet by the first transmission packet transfer step. Further, the method preferentially processes the transmission packet to perform a priority packet transmission command. Including a fourth data processing step to be sent to the media access controller, wherein the second transmission packet transfer step preferentially sends the urgent packet as a response to the priority packet transmission command in the media access controller. It is characterized by transmitting.

  According to the packet communication device of the present invention, it is determined whether or not the received packet is an urgent packet in the MAC, and if it is an urgent packet, the urgent packet is transferred to a processing buffer used in the encryption / decryption accelerator, Then, the MAC sends an interrupt to the main control unit to preferentially process the urgent packet, and the main control unit processes the urgent packet on the processing buffer, thereby giving priority to the packet transfer such as DMA transfer. Packets can be processed at different times.

  In this packet communication device, the data related to the priority packet is directly transferred between the MAC and the accelerator, and thus is not counted by the DMA transfer. In addition, it is possible to simplify the process in which the main control unit accesses the memory and transfers the received packet, omits bi-directional transfer of the priority packet between the normal buffer and the processing buffer, and can process the received packet at high speed. Further, since priority packets are processed not on the normal buffer but on the processing buffer, bus contention can be avoided and processing can be performed at an efficient speed. Further, since the accelerator processing buffer is used, encryption / decryption processing can be performed conveniently, and resource saving can be achieved.

  In addition, according to the packet communication apparatus of the present invention, it is determined whether the packet is a priority packet by referring to the priority of the received packet, so that a specific method for determining emergency processing is realized and a plurality of processing buffers are provided. Thus, by performing priority packet transfer and packet processing by buffering, even when priority packets are received consecutively, they can be processed efficiently, leaving room for accelerator and main controller processing time. The burden can be reduced and packet processing failures can be avoided.

  Embodiments of a packet communication apparatus according to the present invention will now be described in detail with reference to the accompanying drawings. For example, as shown in FIG. 1, the packet communication apparatus 10 of the present invention connects a main control unit 12 and a memory 14 via an internal bus 16, and a direct memory access (DMA) control unit 18 By controlling, the media access controller (MAC) 20 receives a packet from the outside and transfers it to the memory 14, while the packet in the memory 14 is transferred to the MAC 20 and transmitted to the outside. In particular, the packet communication device 10 integrates the MAC 20 with the encryption / decryption accelerator 22, and encrypts and decrypts the packet in the processing buffer 24 by the accelerator 22, and further uses the processing buffer 24. Efficiently process packets to be processed urgently. Note that portions not directly related to understanding the present invention are not shown and redundant description is avoided.

  The main control unit 12 has a function of controlling and supervising the operation of the entire apparatus and is configured by a CPU (Central Processing Unit) or the like. In this embodiment, the main control unit 12 executes packet transmission / reception processing according to a program. The DMA control unit 18 can be controlled.

  For example, when performing packet reception processing, the main control unit 12 notifies the DMA control unit 18 of a packet reception start command, and makes the DMA control unit 18 ready for packet reception. Further, the main control unit 12 starts data processing of the received packet transferred to the memory 14 in response to the interrupt request IRQ1 notified from the DMA control unit 18.

  Further, when performing packet transmission processing, the main control unit 12 processes the packet to be transmitted and stores it in the memory 14, and notifies the DMA control unit 18 of a packet transmission start command, Controls to transfer the packet in the memory 14 to the MAC 20 for transmission.

  When the main control unit 12 determines that decryption and encryption processing is necessary in the packet transmission / reception processing, the main control unit 12 notifies the encryption / decryption accelerator 22 of the decryption and encryption commands. At this time, if the main control unit 12 determines that decryption and encryption processing of the packet in the normal buffer 26 of the memory 14 is necessary, the main control unit 12 transfers the packet from the normal buffer 26 to the processing buffer 24 of the MAC 20. Then, the decryption and encryption command is notified, and when the decryption and encryption processing is completed, the DMA control unit 18 is controlled to transfer the processed packet from the processing buffer 24 to the normal buffer 26 again.

  In addition, the main control unit 12 responds to an interrupt request IRQ2 indicating completion of priority packet transfer supplied from the MAC 20 during packet reception processing, such as a packet to be urgently processed such as a priority packet stored in the processing buffer 24. Is preferentially processed. The main control unit 12 may perform data processing on the priority packet on the processing buffer 24. When the data processing is completed, the main control unit 12 controls the DMA control unit 18 to transfer the priority packet from the processing buffer 24 to the normal buffer 26. It is good to transfer.

  In addition, in the data processing of the received priority packet, the main control unit 12 refers to the encryption header of the priority packet, and if the priority packet is encrypted, the main control unit 12 notifies the accelerator 22 of the decryption command and decrypts it. Let the process.

  When the main control unit 12 receives the interrupt request IRQ2 during the normal packet data processing in the normal buffer 26, the main control unit 12 may start the data processing for the priority packet after the data processing for the normal packet being processed ends. The main control unit 12 may return to the data processing of the normal packet remaining in the normal buffer 26 after the data processing of the priority packet is completed.

  Further, the main control unit 12 determines whether or not it is a packet to be urgently processed when processing a transmission packet during packet transmission processing. In this embodiment, the main control unit 12 determines whether or not the packet is a priority packet. Determine. As a result, when the main control unit 12 determines that the packet is a priority packet, the main control unit 12 may transfer the priority packet from the normal buffer 26 to the processing buffer 24 and perform data processing on the priority packet on the processing buffer 24. Such an event for transmitting a priority packet occurs when an external interrupt from a peripheral device such as an audio device is sent to the main control unit 12, for example.

  Further, when the main control unit 12 determines in the data processing of the priority packet to be transmitted that the priority packet should be encrypted, the main control unit 12 notifies the accelerator 22 of the encryption command and performs the encryption process. Since the main control unit 12 actually transfers the priority packet that has not been packetized from the normal buffer 26 to the processing buffer 24, the priority packet before encryption may be packetized on the processing buffer 24.

  When the data processing of the priority packet to be transmitted is completed, the main control unit 12 notifies the MAC 20 of a priority packet transmission command so that the priority packet is transmitted with priority.

  The memory 14 includes a storage unit such as a RAM (Random Access Memory) and has a normal buffer 26 that temporarily stores packet data to be transmitted and received. Further, the memory 14 may include a structure 28 such as a descriptor used for DMA transfer of the DMA control unit 18, and at this time, the memory 14 may include a descriptor 28 for reception and transmission. . Further, the memory 14 may hold a program that constitutes a packet transmission / reception process executed by the main control unit 12.

  The normal buffer 26 of this embodiment stores normal packets, not emergency packets such as priority packets to be processed urgently.

  The internal bus 16 is also connected to the bus arbitration unit 30, and the bus arbitration unit 30 arbitrates the right to use the internal bus 16 between the main control unit 12 and the DMA control unit 18.

  The DMA control unit 18 is a memory control circuit that directly executes data transfer without going through the main control unit 12. In this embodiment, the DMA control unit 18 controls DMA transfer of packet data between the MAC 20 and the normal buffer 26.

  For example, the DMA control unit 18 enters a receivable state in response to a reception start command supplied from the main control unit 12. The DMA controller 18 in a receivable state receives a packet reception notification from the MAC 20 that has received the packet, and transfers the packet received by the MAC 20 to the normal buffer 26 of the memory 14 in response to this notification.

  The DMA control unit 18 of this embodiment reads a transmission / reception descriptor from the memory 14 and controls DMA transfer of packets in the MAC 20 based on this descriptor. Further, the DMA control unit 18 itself may include this transmission / reception descriptor.

  The MAC 20 is controlled by the DMA control unit 18 to transfer a received packet received from the outside via, for example, a high-speed LAN to the normal buffer 26 of the memory 14 via the internal bus 16, and on the other hand, via the internal bus 16. The transmission packet transferred from the normal buffer 26 is transmitted to the outside. The MAC 20 may include a FIFO memory and temporarily hold received and transmitted packets before transferring and transmitting each. Further, the MAC 20 may perform packet transfer with the normal buffer 26 in accordance with the descriptor array delivered from the DMA control unit 18.

  Particularly in this embodiment, the MAC 20 is integrated with the encryption / decryption accelerator 22, and in FIG. 1, the MAC 20 is configured to include the accelerator 22, but is configured as one processing circuit together with the accelerator 22. Or may be directly connected to a separate accelerator 22. In FIG. 1, the MAC 20 is configured to include a processing buffer 24 used in encryption / decryption processing by the accelerator 22, and stores emergency packets such as priority packets using the processing buffer 24. In this embodiment, the MAC 20 and the encryption / decryption accelerator 22 operate in unison.

  The MAC 20 of this embodiment determines whether the received packet is an urgent packet, and for example, determines whether it is a priority packet. As a result, the MAC 20 transfers it to the processing buffer 24 if it is a priority packet, and transfers it to the normal buffer 26 otherwise. For example, the MAC 20 can determine whether or not the received packet is a priority packet by referring to the packet header of the received packet stored in the FIFO memory.

  For example, according to IEEE802.1Q, to construct a VLAN (Virtual LAN) across multiple hubs, the Ethernet frame is expanded, and the packet includes a VLAN ID, ie, a VLAN tag in the expanded 4-byte portion VLAN tag can be used as a priority definition. The MAC 20 of the present embodiment can refer to a 3-bit CoS (Class of Service) value stored in the “user priority” field in the VLAN tag as the priority of the packet. Further, according to IPv6, a priority field in which 16-step numerical values can be set is provided in the packet header, so the MAC 20 can refer to this priority.

  When transferring the received priority packet, the MAC 20 receives a response signal from the accelerator 22 or the processing buffer 24 that is the transfer destination, and transfers the priority packet to the processing buffer 24 according to the response signal, and then the main control. An interrupt request IRQ2 indicating a priority packet reception notification is sent to the unit 12.

  Further, when the transmission packet is a priority packet, the MAC 20 transfers the priority packet supplied from the normal buffer 26 via the internal bus 16 to the processing buffer 24, and receives a priority packet transmission command from the main control unit 12. The priority packet in the processing buffer 24 is transmitted to the outside.

  The encryption / decryption accelerator 22 decrypts and encrypts a packet based on the decryption and encryption processing conditions such as the common key and initial vector set by the main control unit 12, and includes hardware. These processes are performed at high speed. The accelerator 22 may use, for example, an encryption / decryption method such as a DES (Data Encryption Standard) method.

  The encryption / decryption accelerator 22 of the present embodiment decrypts and encrypts the packet in the processing buffer 24 according to the decryption and encryption command notified from the main control unit 12, and decrypts and encrypts the packet. After completing the processing, a processing completion notification IRQ3 is sent to the main control unit 12.

  The processing buffer 24 is a buffer for decryption and encryption processing. In the present embodiment, the processing buffer 24 is also used for transferring emergency packets such as priority packets.

  Next, the operation of the packet communication apparatus 10 in this embodiment will be described with reference to the sequence chart of FIG.

  In the packet communication device 10 of this embodiment, first, the main control unit 12 executes a packet reception processing program, and a reception start command is notified from the main control unit 12 to the DMA control unit 18 (S102).

  The DMA control unit 18 enters a receivable state (S104) in response to the reception start command, and the MAC 20 enters a state in which external packet reception is possible.

  Next, the MAC 20 in the receivable state receives the first normal packet from the outside, for example, via the high-speed LAN (S106). In MAC 20, the packet received in step S106 is temporarily stored in the FIFO, and the priority of this packet is referenced to determine whether it is a priority packet, and here it is determined to be a normal packet. In response to reception of the first normal packet S106, a packet reception notification is notified from the MAC 20 to the DMA control unit 18 (S108).

  The DMA control unit 18 executes DMA transfer according to the packet reception notification S106, and according to this DMA transfer, a normal packet transfer instruction is notified to the MAC 20 (S110), and the first normal packet received by the MAC 20 is received. Is transferred to the normal buffer 26 (S112).

  Further, in the MAC 20, a transfer completion notification corresponding to the packet transfer S112 is notified to the DMA control unit 18 (S114), and the DMA control unit 18 generates an interrupt request IRQ1 indicating a reception event in response to the transfer completion notification S114. Is sent to the main control unit 12.

  In the main control unit 12, the data processing of the received packet is executed in response to the interrupt request IRQ1 (S116). For example, the normal packet is sequentially read from the normal buffer 26 and processed. Normal packets are read and data processed. At this time, if the first normal packet is encrypted, the first normal packet may be transferred to the processing buffer 24 of the accelerator 22 and decrypted, and the decrypted packet may be processed.

  In the MAC 20 of the present embodiment, the second normal packet is received during the first normal packet data processing S116 (S118). At this time, the MAC 20 notifies the DMA control unit 18 of the packet reception notification in response to the second normal packet reception S118 (S120), and the DMA control unit 18 performs the DMA transfer in response to the packet reception notification S120. The normal packet transfer instruction is notified to the MAC 20 (S122), and the second normal packet received by the MAC 20 is transferred to the normal buffer 26 (S124).

  In the present embodiment, the MAC 20 receives the priority packet before the data processing S116 of the first normal packet is completed (S126). In MAC 20, the packet received in step S106 is temporarily stored in the FIFO, and the priority of this packet is referred to to determine whether it is a priority packet. Here, it is determined to be a priority packet. Although not shown, the MAC 20 notifies the transfer of the priority packet to the processing buffer 24, and the priority packet received according to the response signal from the processing buffer 24 is transferred to the processing buffer 24 of the accelerator 22 (S128). ).

  Further, in the MAC 20, when the priority packet transfer S128 is completed, an interrupt request IRQ2 indicating completion of the priority packet transfer is sent to the main control unit 12.

  In this embodiment, since the interrupt request IRQ2 is sent before the data processing S116 of the first normal packet is completed in the main control unit 12, the priority packet is processed before the data processing of the second normal packet. Is preferentially processed (S130).

  By the way, in the MAC 20 of this embodiment, the third normal packet is received during the priority packet data processing S130 (S132). At this time, the MAC 20 notifies the DMA control unit 18 of a packet reception notification in response to the third normal packet reception S132 (S134), and the DMA control unit 18 performs DMA transfer in response to the packet reception notification S134. The normal packet transfer instruction is notified to the MAC 20 (S136), and the third normal packet received by the MAC 20 is transferred to the normal buffer 26 (S138).

  In the priority packet data processing S130 by the main control unit 12, if the priority packet is encrypted, a decryption command is issued and notified to the accelerator 22 (S140). At this time, the priority packet in the processing buffer 24 is decoded in the accelerator 22 in accordance with the decoding command S140, and the decoded priority packet is transferred to the normal buffer 26 (S142).

  At this time, the third normal packet transfer S138 and the priority packet transfer S142 are performed at the same time, and the internal bus 16 may compete. In this case, the DMA control unit 16 or the bus arbitration unit 30 And may be transferred to the normal buffer 26 so as to flow simultaneously.

  By the way, in the competition between the third normal packet transfer S138 and the priority packet transfer S142, the third normal packet has a lower priority than the priority packet. The packet transfer may be suspended, and the third normal packet transfer may be performed after the priority packet transfer ends. Here, in the packet transfer with a low priority, the priority may be changed according to the holding time, and when the holding time is long, the priority may be temporarily increased. Further, the transfer unit may be changed according to the priority, and the priority packet having a high priority may be transferred in a large unit, and the third packet having a low priority may be transferred in a small unit. These transfer methods in the case of transfer competition may be performed not only at the time of reception but also at the time of transmission.

  In the main control unit 12, when the priority packet data processing S130 ends, the second normal packet and the third normal packet are sequentially processed according to the order of the normal packets stored in the normal buffer 26 (S144 and S146).

  On the other hand, the operation of the packet communication apparatus 10 in this embodiment will be described with reference to the sequence chart of FIG.

  In the packet communication apparatus 10 of this embodiment, first, the main control unit 12 executes a packet transmission processing program to perform data processing of the transmission packet. Here, the first normal packet, the second normal packet, Data processing of the third normal packet is performed (S202, S204, and S206).

  The main control unit 12 determines whether or not the transmission packet is a priority packet in the data processing in steps S202, S204, and S206. Here, it is determined that all are normal packets. After the data processing in steps S202, S204, and S206, the main control unit 12 notifies the DMA control unit 18 of a transmission start command (S208).

  In the DMA control unit 18, a transfer instruction is notified to the MAC 20 in response to the transmission start command S208 (S210). In the MAC 20, normal packets are sequentially transferred from the normal buffer 26 in response to the transfer instruction S210. Then, the first normal packet is transferred (S212).

  Further, in MAC 20, the first normal packet transferred in S212 is transmitted to the outside via, for example, a high-speed LAN (S214), and a transmission notification is sent to the DMA control unit according to the transmission S214 of the first normal packet. It is sent to 18 (S216).

  Next, the DMA control unit 18 notifies the MAC 20 of a transfer instruction according to the transmission notification S216 of the first normal packet (S218), and the MAC 20 from the normal buffer 26 according to the transfer instruction S218. The second normal packet is transferred (S220), and the second normal packet transferred in S220 is transmitted to the outside (S222).

  By the way, in the main control unit 12 of this embodiment, a transmission packet having a high priority is processed between the second normal packet transfer S220 and the second normal packet transmission S222 (S224). In the data processing of step S224, the main control unit 12 determines whether or not the transmission packet is a priority packet, and here determines that it is a priority packet.

  Further, in the priority packet data processing S224, the main control unit 12 sends a priority packet transfer instruction to the accelerator 22 (S226). In the accelerator 22, the priority packet is transferred from the normal buffer 26 to the processing buffer 24 in response to the transfer instruction S226 (S228).

  After the priority packet transfer S228, the data processing S224 by the main control unit 12 is performed on the priority packet on the processing buffer 24. In the data processing S224, the priority packet needs to be encrypted and transmitted. If it is determined, the encryption command is sent to the accelerator 22 (S230). In the accelerator 22, the priority packet in the processing buffer 24 is encrypted in response to the encryption command S230.

  Further, the main control unit 12 sends a priority packet transmission command to the MAC 20 after the transmission of the second normal packet S222 and before the transfer of the third normal packet (S232).

  In the present embodiment, in particular, in the MAC 20, in response to the transmission command S232, the transmission notification to the DMA control unit 18 in response to the transmission S222 of the second normal packet is made to wait without being sent, and the priority packet Is preferentially transmitted. Here, the priority packet is transferred from the processing buffer 24 (S234), and the priority packet transferred in S234 is transmitted to the outside (S236). In this way, even when the third normal packet remains in the transmission descriptor, the priority packet is transmitted with priority.

  Next, in the MAC 20, after the transmission S236 of the priority packet is completed, a transmission notification corresponding to the transmission S222 of the second normal packet is sent to the DMA control unit 18 (S238).

  In the DMA control unit 18, a transfer instruction is notified to the MAC 20 in response to the second normal packet transmission notification S238 (S240). In the MAC 20, the third buffer 26 receives a third instruction from the normal buffer 26 in response to the transfer instruction S240. The normal packet is transferred (S242), and the third normal packet transferred in S242 is transmitted to the outside (S244).

  Further, as another embodiment, the packet communication device 10 includes a processing buffer 24 having a plurality of buffers in the MAC 20, and performs buffering using these buffers, whereby the main control unit 12 Packet processing such as packet encryption or decryption processing, or priority packet data processing, and transfer of priority packets by the MAC 20 can be performed efficiently.

  According to this embodiment, for example, when a priority packet is transferred to one of the plurality of processing buffers 24 and the main control unit 12 performs data processing of the priority packet on this one buffer, The MAC 20 can transfer the newly received priority packet to the other buffer.

  After that, when the main control unit 12 finishes the data processing on one buffer and the MAC 20 completes the priority packet transfer on the other buffer, the main control unit 12 creates a new priority packet on the other buffer. Data processing can be started immediately.

  In this embodiment, the MAC 20 includes a buffer arbitration unit 50 that arbitrates the use of the plurality of processing buffers 24, and the buffer arbitration unit 50 may be configured by a logic circuit. The buffer arbitration unit 50 may include a buffer designating unit 52 that indicates which of the plurality of processing buffers 24 is used for priority packet transfer or which processing buffer is performing priority packet transfer. The buffer arbitration unit 50 and the buffer designation unit 52 have a function of performing exclusive control so that the MAC 20 and the main control unit 12 do not access the same processing buffer at the same time.

  For example, when a new priority packet is received, the MAC 20 refers to the buffer designating unit 52 to determine a buffer to which the priority packet is to be transferred, and transfers the priority packet to the determination result buffer.

  The MAC 20 notifies the buffer arbitration unit 50 of a priority packet transfer completion notification when the newly received priority packet is transferred to one of the plurality of processing buffers 24 and completed.

  Further, when performing packet processing such as normal packet encryption or decryption processing, or priority packet data processing, the main control unit 12 determines a buffer to be subjected to packet processing with reference to the buffer designating unit 52, Packet processing is performed on the packet in the buffer of the determination result.

  The main control unit 12 sends a packet processing end notification to the buffer arbitration unit 50 when the normal packet encryption or decryption processing or the priority packet data processing ends in any of the plurality of processing buffers 24. Notice. At this time, the main control unit 12 may control the DMA control unit 18 to transfer the priority packet for which data processing has been completed from the processing buffer to the normal buffer.

  In addition, the buffer arbitration unit 50 of the present embodiment converts and updates the buffer indicated by the buffer specifying unit 52 when receiving a packet processing end notification from the main control unit 12 or a priority packet transfer completion notification from the MAC 20. To do.

  In the packet communication apparatus 10 of this embodiment, for example, the MAC 20 may include two processing buffers 54 and 56 as the plurality of processing buffers 24, and the buffer arbitration unit 50 may include a buffer designation flag as the buffer designation unit 52.

  When two processing buffers are used, the buffer designation flag 52 may be a 1-bit flag, and the processing buffers 54 and 56 will receive priority packets when the value of the buffer designation flag 52 is 0 and 1, respectively. Used as a buffer to be transferred. When three or more processing buffers are used, the buffer designation flag 52 is a multi-bit flag corresponding to the number of processing buffers. In this case, the burden on the main control unit 12 can be further reduced.

  Next, the operation of receiving packets using the two processing buffers 54 and 56 in the packet communication apparatus 10 in the present embodiment will be described with reference to the flowchart of FIG.

  In the packet communication device 10 of the present embodiment, first, when the packet reception process starts (S302), the two processing buffers 54 and 56 become empty, and the value of the 1-bit buffer designation flag 52 becomes zero.

  Next, proceeding to step S304, when the MAC 20 receives the first priority packet, the buffer arbitration unit 50 refers to the buffer designation flag 52, where the value of the buffer designation flag 52 is 0. Therefore, the buffer to which the priority packet is to be transferred is determined to be the processing buffer 54, and the first priority packet is transferred to the buffer 54 by the MAC 20.

  In this way, when the transfer of the first priority packet is completed, an interrupt request IRQ2 indicating the completion of the priority packet transfer is sent from the MAC 20 to the main control unit 12. At this time, the buffer arbitration unit 50 receives a priority packet transfer completion notification from the MAC 20 and updates the value by setting the value of the buffer designation flag 52 to 1.

  Next, proceeding to step S306, the main control unit 12 starts preferential data processing of the transferred priority packet in response to the interrupt request IRQ2 from the MAC 20. At this time, in the main control unit 12, the buffer to be subjected to packet processing is indicated from the buffer arbitration unit 50. In the buffer arbitration unit 50, the buffer designation flag 52 is referred to. Is 0, it is determined that the buffer to be subjected to packet processing is the processing buffer 54 to which the first priority packet is transferred, and the main control unit 12 performs packet processing on this buffer 54.

  By the way, in the present embodiment, the second priority packet is received by the MAC 20 while the first priority packet is being processed. At this time, the buffer arbitration unit 50 refers to the buffer designation flag 52. Here, since the value of the buffer designation flag 52 is 1, the buffer to which the priority packet is to be transferred is determined as the processing buffer 56. In the MAC 20, the second priority packet is transferred to the buffer 56.

  As described above, the second priority packet can be transferred to the processing buffer 56 while the data processing of the first priority packet is being performed on the processing buffer 54. When the transfer of the second priority packet is completed, an interrupt request IRQ2 indicating the completion of the priority packet transfer is sent from the MAC 20 to the main control unit 12, and the buffer arbitration unit 50 receives a priority packet transfer completion notification from the MAC 20. Thus, the value of the buffer designation flag 52 is set to 0 again and updated.

  Next, proceeding to step S308, the main control unit 12 has received the interrupt request IRQ2 from the MAC 20, so after updating the data processing of the first priority packet, without updating the value of the buffer designation flag 52, Preferential data processing of the second priority packet is started. At this time, in the main control unit 12, the buffer designation flag 52 having a value of 0 is referred to by the buffer arbitration unit 50 for the data processing target buffer, so that the process in which the second priority packet is transferred It is determined that the buffer 56 is used, and the main control unit 12 performs packet processing on the buffer 56.

  If the main control unit 12 has not received a new interrupt request IRQ2 from the MAC 20 when the data processing of the second priority packet is completed, a packet processing end notification is notified to the buffer arbitration unit 50. In the buffer arbitration unit 50, the value of the buffer designation flag 52 is set to 1 again and updated.

  In step S310, the MAC 20 receives the third priority packet. At this time, since the buffer specifying flag 52 having a value of 1 is referred to by the buffer arbitration unit 50, the buffer to which the priority packet is to be transferred is determined as the processing buffer 54. In the MAC 20, the third priority packet is transferred to the buffer 54.

  As described above, when the transfer of the third priority packet to the processing buffer 54 is completed, the interrupt request IRQ2 indicating the completion of the priority packet transfer is sent from the MAC 20 to the main control unit 12, and the buffer arbitration unit 50 starts from the MAC 20. Upon receipt of the priority packet transfer completion notification, the value of the buffer designation flag 52 is set to 0 again and updated.

  Next, proceeding to step S312, the main control unit 12 starts preferential data processing of the third priority packet in response to the interrupt request IRQ2 from the MAC 20. At this time, in the main control unit 12, the buffer to be processed is referred to the buffer designation flag 52 having a value of 0 in the buffer arbitration unit 50. Therefore, the process in which the third priority packet is transferred The buffer 54 is determined, and the main control unit 12 performs packet processing on the buffer 54.

  If the main control unit 12 has not received a new interrupt request IRQ2 from the MAC 20 when the data processing of the third priority packet is completed, a packet processing end notification is notified to the buffer arbitration unit 50, and the buffer arbitration is performed. In the unit 50, the value of the buffer designation flag 52 is set to 1 again and updated.

  Further, the packet communication device of the present invention, when applied to a network device, does not include a plurality of processing buffers, and is complicated such as expensive hardware such as a dual port memory or a circular (ring-shaped) buffer. By combining various data structure parts, a configuration accessible from both the MAC 20 and the main control part 12 can be realized.

  The packet communication device of the present invention can be applied not only to a high-speed LAN but also to all wired or wireless network systems that use a device that performs packet transfer and processing according to priority.

  For example, the packet communication apparatus of the present invention can be applied to a VoIP terminal with a WEB browser function. In such a terminal, the configuration of the present invention is effective when the voice packet for call is encrypted and used for a secret story, or when a WEB browser is used during a call.

  In this VoIP terminal, the packet encrypted for the secret story can suppress the occurrence of delay and fluctuation, and can achieve high sound quality. Also, when receiving an encrypted voice packet while receiving data to be displayed on the web browser, the web browser data is received as a normal packet, and the voice packet encrypted for a secret story is received as a priority packet. be able to.

  In the VoIP terminal according to the present invention, the configuration of the present invention is effective when providing WEB service to other terminals.

  If you want to connect to this VoIP terminal using the WEB browser of another terminal and realize a function that refers to information such as the address book held by this VoIP terminal, Data can be used as normal packets, and packets for VoIP calls can be encrypted and used as priority packets.

It is a block diagram which shows one Example of the packet communication apparatus of this invention. It is a sequence chart explaining the operation | movement procedure of the packet reception process of the packet communication apparatus shown in FIG. It is a sequence chart explaining the operation | movement procedure of the packet transmission process of the packet communication apparatus shown in FIG. It is a block diagram which shows the media access controller in the other Example of the packet communication apparatus of this invention. It is a flowchart explaining the operation | movement procedure of the packet communication apparatus shown in FIG.

Explanation of symbols

10 Packet communication equipment
12 Main control unit
14 memory
16 Internal bus
18 DMA controller
20 MAC
22 Encryption / Decryption Accelerator
24 processing buffers
26 Normal buffer
28 descriptors
30 Bus mediation department

Claims (19)

Main control means for data processing of transmission / reception packets stored in a normal buffer;
A media access controller that forwards externally received packets to the normal buffer, and transmits transmission packets in the normal buffer to the outside;
Direct memory access control means for controlling transfer of the transmission / reception packet between the normal buffer and the media access controller, and causing direct memory access transfer without going through the main control means;
In a packet communication device including an accelerator that decrypts and encrypts the transmission / reception packet stored in a processing buffer,
The apparatus is configured by integrating the media access controller and the accelerator,
The media access controller includes first determination means for determining whether or not the received packet is an urgent packet to be subjected to data processing urgently by the main control means. Transfer the received packet to the processing buffer, send a first interrupt to the main control means, otherwise transfer the received packet as a normal packet to the normal buffer,
The main control means preferentially processes the received packet, which is the emergency packet, in response to a first interrupt.   2. The packet communication device according to claim 1, wherein the first determination unit determines whether or not the received packet is a priority packet based on the priority, so that the received packet is the emergency packet. A packet communication device that determines whether or not.   2. The packet communication apparatus according to claim 1, wherein the main control means processes the received packet, which is the emergency packet, on the processing buffer.   2. The packet communication device according to claim 1, wherein when the main control unit receives a first interrupt during data processing of the normal packet in the normal buffer, the data processing of the normal packet being processed is completed. Then, the data processing of the emergency packet is started, and after the data processing of the emergency packet is finished, the packet communication device returns to the data processing of the normal packet remaining in the normal buffer. The packet communication device according to claim 1, wherein the processing buffer includes a plurality of buffers.
The packet communication apparatus, wherein the media access controller continuously transfers the emergency packet by using the plurality of buffers alternately. 6. The packet communication device according to claim 5, wherein the media access controller includes a buffer designating unit that indicates which of the plurality of buffers is used for emergency packet transfer;
A packet communication apparatus comprising buffer arbitrating means for arbitrating use of the plurality of buffers with reference to the buffer specifying means. The packet communication device according to claim 6, wherein the plurality of buffers include a first buffer and a second buffer,
The buffer designating means is a flag indicating a value of 0 when the first buffer is used for urgent packet transfer, a value of 1 when the second buffer is used, and a value of 0 in the initial state.
When the media access controller newly receives an emergency packet, it refers to the buffer designating unit to determine a buffer to be used for the emergency packet transfer, transfers the emergency packet to the buffer of the determination result, When the transfer of the emergency packet is completed, a priority packet transfer completion notification is notified to the buffer arbitration means,
When performing packet processing such as urgent packet data processing, the main control unit determines a buffer to be subjected to the packet processing with reference to the buffer specifying unit, and performs packet processing on the packet in the determination result buffer. When the packet processing is finished, a packet processing end notification is notified to the buffer arbitration means,
The buffer arbitration unit converts and updates the value indicated by the buffer designating unit when receiving the packet processing end notification from the main control unit or the priority packet transfer completion notification from the media access controller. A packet communication device. The packet communication device according to claim 1,
The main control means includes second determination means for determining whether or not the transmission packet is an urgent packet to be subjected to data processing urgently, and as a result, if the transmission packet is an urgent packet, the processing is performed on the transmission packet. Transfer to the buffer, otherwise transfer the transmission packet as a normal packet to the normal buffer,
Further, the transmission packet is preferentially processed, and a priority packet transmission command is sent to the media access controller,
The media access controller preferentially transmits a transmission packet that is the emergency packet in response to the priority packet transmission command. Main control means for data processing of transmission / reception packets stored in a normal buffer;
A media access controller that forwards externally received packets to the normal buffer, and transmits transmission packets in the normal buffer to the outside;
Direct memory access control means for controlling transfer of the transmission / reception packet between the normal buffer and the media access controller, and causing direct memory access transfer without going through the main control means;
In a packet communication device including an accelerator that decrypts and encrypts the transmission / reception packet stored in a processing buffer,
The apparatus is configured by integrating the media access controller and the accelerator,
The main control means includes second determination means for determining whether or not the transmission packet is an urgent packet to be subjected to data processing urgently, and as a result, if the transmission packet is an urgent packet, the processing is performed on the transmission packet. Transfer to the buffer, otherwise transfer the transmission packet as a normal packet to the normal buffer,
Further, the transmission packet is preferentially processed, and a priority packet transmission command is sent to the media access controller,
The media access controller preferentially transmits a transmission packet that is the emergency packet in response to the priority packet transmission command.   10. The packet communication apparatus according to claim 9, wherein the main control unit processes the transmission packet that is the emergency packet on the processing buffer. A first received packet transfer step of transferring a received packet received from the outside to the normal buffer by a media access controller;
A first data processing step of processing data received packets stored in the normal buffer in the main control unit;
A transfer control step of controlling transfer of the received packet between the normal buffer and the media access controller by a direct memory access control unit, and direct memory access transfer without the main control unit;
A packet processing method including a decoding step of decoding the received packet stored in the processing buffer with an accelerator, the method comprising:
Using the integrated media access controller and the accelerator;
The media access controller determines whether the received packet is an urgent packet that should be urgently processed by the main control means. As a result, if the received packet is an urgent packet, the received packet is A second received packet transfer step of transferring to the processing buffer, and sending a first interrupt to the main control unit; otherwise, the received packet is converted into a normal packet by the first received packet transfer step. A first determination step of transferring to a normal buffer;
And a second data processing step of preferentially processing the received packet, which is an emergency packet, in a main control unit in response to a first interrupt.   12. The packet processing method according to claim 11, wherein the first determination step determines whether or not the received packet is a priority packet based on the priority, so that the received packet is the emergency packet. A packet processing method characterized by determining whether or not.   12. The packet processing method according to claim 11, wherein the second data processing step processes the received packet that is the emergency packet on the processing buffer.   12. The packet processing method according to claim 11, wherein in the second data processing step, when the first interrupt is received during data processing of the normal packet in the normal buffer in the main control unit, After the data processing of the normal packet is finished, the data processing of the emergency packet is started, and after the data processing of the emergency packet is finished, the processing returns to the data processing of the normal packet remaining in the normal buffer. A packet processing method. 12. The packet processing method according to claim 11, wherein the method uses the processing buffer having a plurality of buffers,
In the second received packet transfer step, the media access controller uses the plurality of buffers alternately to continuously transfer the emergency packet.   16. The packet processing method according to claim 15, wherein the method refers to a buffer designating unit that indicates which of the plurality of buffers is used for urgent packet transfer. A packet processing method comprising a buffer arbitration step of arbitrating in an arbitration unit. 17. The packet processing method of claim 16, wherein the method uses the plurality of buffers having a first buffer and a second buffer;
A flag indicating a value of 0 when the first buffer is used for urgent packet transfer, a flag indicating a value of 1 when the second buffer is used, and the buffer designating unit indicating a value of 0 in the initial state is used. ,
In the second received packet transfer step, when a new emergency packet is received by the media access controller, a buffer used for the emergency packet transfer is determined by referring to the buffer designating unit, and the determination result is buffered. And, when the emergency packet is transferred and the transfer of the emergency packet is completed, a priority packet transfer completion notification is notified to the buffer arbitration unit,
In the first or second data processing step, when performing packet processing such as urgent packet data processing in the main control unit, the buffer designation unit is referred to determine a buffer to be subjected to the packet processing, Packet processing is performed on the packet in the buffer of the determination result, and when the packet processing is ended, a packet processing end notification is notified to the buffer arbitration unit,
When the buffer arbitration step receives the packet processing end notification from the main control unit or the priority packet transfer completion notification from the media access controller in the buffer arbitration unit, the value indicated by the buffer designation unit A packet processing method characterized by converting and updating. A third data processing step of processing the transmission packet stored in the normal buffer in the main control unit;
A first transmission packet transfer step of transmitting a transmission packet in the normal buffer to the outside by the media access controller;
A transfer control step of controlling transfer of the transmission packet between the normal buffer and the media access controller by a direct memory access control unit, and direct memory access transfer without the main control unit;
A packet processing method including an encryption step of encrypting the transmission packet stored in the processing buffer with an accelerator.
Using the integrated media access controller and the accelerator;
The third data processing step includes a second determination step of determining whether or not the transmission packet is an urgent packet that should be urgently processed. As a result, if the transmission packet is an urgent packet, the transmission packet is Including a second transmission packet transfer step of transferring to the processing buffer; otherwise, the transmission packet is transferred to the normal buffer as a normal packet by the first transmission packet transfer step;
Further, the method includes a fourth data processing step of preferentially processing the transmission packet and sending a priority packet transmission command to the media access controller.
In the second transmission packet transfer step, the media access controller preferentially transmits a transmission packet that is the emergency packet in response to the priority packet transmission command. 19. The packet processing method according to claim 18, wherein in the fourth data processing step, the transmission packet that is the emergency packet is processed on the processing buffer.

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