JP2008257393A - Data input/output control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data input/output control circuit absorbing synchronization deviation by a clock speed difference between different systems to keep a buffer use amount stable. <P>SOLUTION: This data input/output control circuit has: a buffer memory (20) performed with reading and writing of data interfaced with another device according to a clock of the other device; a clock error detection part (23) detecting a clock error between a clock of its own device and the clock of the other device; a buffer memory use amount calculation part (41) calculating the use amount of the buffer memory based on respective count values of the clock of the own device and the clock of the other device; a comparison part (43) comparing the use amount of the buffer memory with a prescribed threshold value; and an operation clock control part controlling an operation clock of the writing and the reading of the data to the buffer memory performed in the own device according to the clock error and a comparison result between the use amount of the buffer memory and the prescribed threshold value. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data input / output control circuit, and more particularly to a data input / output control circuit suitable for controlling input / output of data between its own device and another device.

  When performing asynchronous transmission of data between devices, a buffer memory or the like is provided to absorb the speed difference of asynchronous transmission. However, even if the clock frequency between the devices is the same, if the source oscillation (original oscillator) used for each device is different, a clock error (phase difference shift) may occur gradually. There is. When data is written to and read from the buffer memory according to the clock of each device, the clock error appears as an error in the number of data (the number of data sampling), which may cause a problem such as missing data. Also, if the data writing and reading clock speeds differ from each other in the buffer memory, the amount of use of the buffer memory may not be kept stable, and the delay time from data input to output may vary.

Therefore, for example, the technique disclosed in Patent Document 1 proposes to read data with a read clock having a frequency higher than the frequency of the write clock with respect to buffer memories having different write and read clock speeds.
JP 2000-173260 A (FIG. 1)

  The technique described in Patent Document 1 described above is applicable only when the read clock is faster than the write clock. Therefore, the read side is suitable only for bursty processing and leaves room for improvement. It was.

  Accordingly, an object of the present invention is to prevent the occurrence of problems such as data loss even if an error occurs in the clock of each device when data is transmitted between devices having different original vibrations. An object of the present invention is to provide a data input / output control circuit that keeps the amount of use stable and prevents fluctuations in delay time.

In order to solve the above problems, the data input / output control circuit of the present invention is a data input / output control circuit for controlling input / output of data between its own device and another device.
A buffer memory for writing and reading the data interfaced to the other device according to the clock of the other device;
A clock error detection unit for detecting a clock error between the clock of the device itself and the clock of the other device;
A buffer memory usage calculating unit that calculates the usage of the buffer memory based on the count values of the clock of the own device and the clock of the other device;
A comparison unit that compares the usage amount of the buffer memory with a predetermined threshold;
An operation clock controller that controls an operation clock for reading and writing the data to and from the buffer memory performed by the device according to a comparison result between the usage amount of the buffer memory and the predetermined threshold value and the clock error; ,
It comprised so that it might be equipped with.

  According to the data input / output control circuit of the present invention, even if an error occurs in the clock of each device, it is possible to prevent problems such as data loss and to stabilize the use amount of the buffer memory. It is possible to prevent the fluctuation of the delay time.

  FIG. 1 is a block diagram showing an embodiment of a data input / output control circuit of the present invention.

  The present invention provides a data input / output control for controlling data input / output between the device B (I / O board) (100) (own device) and the device A (radio device) (200) (other device). Device B (100) which is a circuit and is synchronized with data such as speech encoded data as input / output on the terminal side of device A (200), and interfaced with this data and clock (input / output connection control) The data input / output control circuit (2) of the device B (100) is provided with a function for controlling the clock cycle error with respect to the clock cycle error (clock error) generated between the clock and the clock. It is.

  The configuration will be described below with reference to the block diagrams of FIGS. The device A (200) includes a clock generation unit A (3) and functions as a radio unit, which is not shown, but is not described in detail.

  FIG. 1 shows that a data input / output control circuit (2) which is its own device when the present invention is implemented is a main part of the device A (200) according to the clock of the device A (200) which is another device. ) Is a circuit having a function of controlling writing and reading of data with respect to the buffer memory (20). The operation will be described.

  The clock A is generated by a clock generation unit A (3) included in the device A (200), and is externally input to the device B (100) from the device A (200) as viewed from the device B (100). In the buffer memory unit (20), input data A, which is input information data from the device A (200), is written to the buffer memory (20), and is output information data to the device A (200). It is used as a clock for reading the output data A from the buffer memory (20).

  The clock B is an internal clock generated by the clock generator B (1) included in the device B (100), and the input data A stored in the buffer memory unit (20) is input to, for example, a D / A converter. It is used as a clock for reading out as output data B, which is output information data, and for writing as input data B, which is input information data from an A / D converter, for example.

  The clock A output from the terminal b3 of the device A (200) and the input data A output from the terminal b1 in synchronization with the clock A are connected to the terminals c3 and c1 of the device B (100), respectively. The data is input to the buffer memory unit (20). The input data A is received data received wirelessly by the device A (200).

  Furthermore, the output data A output from the terminal c2 of the device B (100) is read from the buffer memory unit (20) by the clock A, and is synchronized with the clock A to the terminal b2 of the device A (200). Entered. The output data A becomes transmission data of the device A (200).

  The line format of data transmission between the terminals b1 and c1 and the terminals b2 and c2 to which the input data A and the output data A are transmitted may be either serial transmission or parallel transmission.

  On the other hand, the clock B generated by the clock generator B (1) in the device B (100) is input to the data input / output control circuit (2) and the like.

  The data is output from the buffer memory unit (20 (1)) to the terminal d1 and transferred to the D / A converter operating in synchronization with the clock B. Although not shown, the output of the D / A converter is connected to a voice input / output device. As described above, the sound signal received by the device A (200) is output from the speaker of the sound input / output device via the device B (100).

  Further, for example, although not shown, the sound input from the microphone of the sound input / output device is input to the A / D converter that operates in synchronization with the clock B, and the output of the A / D converter is the data input. Input data B is input from the terminal d2 to the output control circuit 2 and written to the buffer memory unit (20 (2)). The data written in the buffer memory unit (20 (2)) is read by the clock A to become output data A, which is wirelessly transmitted from the device A (200) to the outside via the terminals c2 and b2.

  Next, the clock A is input to the counter A (21), and the clock B is input to the counter B (22). Each clock count is the number of rising edges of the clock. .) Is performed.

  Here, although the maximum number of counts and the reset timing (predetermined period) in each of the counter A (21) and the counter B (22) are not shown, arbitrary values can be set from the outside. The maximum number of counts is set according to the memory storage capacity of data in the buffer memory unit (20).

  The outputs of the counter A (21) for calculating the count of the clock A of the device A (200) and the counter B (22) for calculating the count of the clock B of the device B (100) The error is added to the error adder (25) and the clock error calculator (23). First, the clock error calculator (23) calculates (detects) and outputs the count difference between the two clock count values as the clock error (30). The

  The obtained clock error value (30), which is the output of the count difference between the two clock count values, is numerical information that can be either plus or minus sign. As a result including the sign information, the next block Is input to the thinning frequency coefficient table (24).

  The thinning frequency coefficient table (24) uses the value of the clock error value (30) as a reference value, creates an output count value (31) that is a weight count output as a conversion value corresponding to the reference value, and The output of the block.

  On the other hand, the outputs of the counter A (21) and the counter B (22) are also input to the clock error adder (25), and here, the cumulative calculation of the clock error value obtained from the difference between the two clock count values is performed. . This cumulative calculation result represents the memory usage of the buffer memory unit (20).

  Further, the threshold value information (40) stored in the memory of the threshold value information unit (26) is input to the clock error adding unit (25).

  In the clock error adding unit (25), the value of the threshold information (40) is compared with the cumulative calculation result of the clock error value representing the memory usage of the buffer memory unit (20) to obtain a comparison result.

  Further, when the memory usage of the buffer memory unit (20) exceeds the threshold information (40), the threshold excess information is sent to the next thinning frequency calculation unit (27) as information indicating that the memory usage has been exceeded. (44) is transmitted.

  The decimation frequency calculation unit (27) receives the threshold value excess information (44) as the output of the clock error addition unit (25) and the information of the output count value (31) as the output of the decimation frequency coefficient table (24). As a result, a thinning frequency value (32) is obtained and output. This decimation frequency value (32) is transferred to the clock control unit (28) which issues a control command (33) for performing decimation control on either or both of the output data B and the input data B which are actual information data. The

  The clock control unit (28) controls (generates) read and write operation clocks for the terminal side (B side) of the buffer memory unit (20) according to the calculated thinning frequency value (32). At this time, the clock A created and transferred from the device A (200) is not controlled but fixed.

  From the point of view of such a control operation, if the speed of the clock B generated by the device B (100) is faster than the speed of the clock A generated by the device A (200), Tav ( The clock B is thinned at a frequency according to the value of the clock thinning frequency value (32). On the contrary, if the speed of the clock A is faster, the number of clocks of the clock B is increased at a frequency corresponding to the value of Tav.

  As described above, when a clock error occurs between devices, the data input / output control circuit of the present invention absorbs a transmission speed difference between input information data and output information data by thinning out or increasing the clock, and The memory usage amount of the information data in the buffer memory unit is optimized, and the variation in delay time from the input information data to the output information data can be suppressed as much as possible.

  In the embodiment applied to apparatus A (200), the data transfer system of input data A → output data B functions as a reception demodulation output, and the data transfer system of input data B → output data A functions as a transmission modulation input.

  Next, as an example of the operation in the thinning frequency counting table (24) and the clock error adding unit (25), detailed processing contents will be described with reference to FIGS.

  FIG. 2 shows an example of the thinning frequency coefficient table stored in the internal memory of the thinning frequency counting table (24). Although not shown, each numerical value of this table can be set from a CPU provided in the apparatus or an external PC, and the setting may be dynamically changed. By selecting each numerical value in this table, it is possible to change the setting to speed up or slow down the time for the clock error value (30) to converge to zero clock error.

  Each coefficient value of the embodiment set as the table shown in FIG. 2 is such that the numerical value in the left column is a clock error value (from the values measured at the reset timing of the counters A (21) and B (22) ( 30) is an output value of the clock error calculation unit (23), which is information (symbol; ΔCLK) input to the thinning frequency coefficient table (24).

  The numerical value in the right column is a value set corresponding to each numerical value information of the clock error value (30), and this is obtained as the output count value (31) output from the thinning frequency coefficient table (24). Information (symbol: Tin).

  In this table example, a large value is set so as to achieve a fast convergence time. For this reason, even when a large error occurs, the tracking speed becomes faster and effective.

  When the clock error value (30) is 0, that is, when the output count value (31) is 0, the convergence state is reached, and this convergence keeps the data amount in the buffer memory unit (20) constant. It is.

  It should be noted that the function of the thinning frequency coefficient table (24) is omitted, the output value of the clock error calculation unit (23) is directly input to the thinning frequency calculation unit (27), and the conversion value by the thinning frequency coefficient table is not used. Alternatively, the clock error value (30) may be used as it is in the calculation process in the thinning frequency calculation unit (27).

  FIG. 3 is a block diagram showing a detailed configuration example of the clock error adder (25) of the data input / output control circuit (2) of the present invention.

  As an input to this block, information on the output of the counter A, which is the count value of the clock A created by the clock generator A (3) of the device A (200), is generated at the terminal e and the clock generated by the device B (100). The information of the counter B output, which is the count value of the clock B created by the part B (1), is inputted to the terminal f, and the threshold value information (40) which is the output of the threshold information part (26) is inputted to the terminal g. The

  Each information of the counter A output and the counter B output is input to the buffer usage calculation unit (41), and the input data stored in the memory in the buffer memory unit (20) is calculated by accumulating the respective count values. The data amount of A and input data B can be grasped.

  Since the count values of the counter A (21) and the counter B (22) are reset every predetermined period, the buffer usage calculation unit (41) counts the count values (buffer usage) obtained every predetermined period. The accumulated data amount of the input data A and the input data B accumulated in the memory in the buffer memory unit (20) is calculated, and the increase / decrease for each predetermined period can be grasped.

  That is, the buffer usage calculation unit (41) is a buffer memory usage calculation unit that calculates the buffer memory usage based on the count values of the clock of the device B (100) and the clock of the device A (200). is there.

  The data amount increase / decrease value (42), which is the output of the buffer usage calculation unit (41), is a plus sign indicating the direction toward the upper limit (upper threshold) of the buffer usage, or the lower limit (lower threshold) of the buffer usage. One of the minus signs indicating the direction of the input data A is given, and if it is positive, the data accumulation amount of the input data A is in the increasing direction, that is, newly stored in the buffer memory unit (20 (1)). The possible memory capacity indicates a decreasing direction.

If it is negative, the data storage amount of the input data A is decreasing, that is, the newly storable memory capacity in the buffer memory unit (20 (1)) is increasing (see FIG. 4).
The same holds for the amount of data stored in the input data B in the buffer memory unit (20 (2)).

  The threshold information (40) and the data amount increase / decrease value (42) are input to the comparison unit (43), and the two values are compared. At this time, if the data amount increase / decrease value (42) is a plus sign, the threshold information (40) has a minus sign so that the data amount increase / decrease value (42) is compared with the upper limit value (upper threshold value). For example, it operates so as to be compared with the lower limit value (lower threshold value). That is, the comparison unit (43) is a comparison unit that compares the usage amount of the buffer memory with a predetermined threshold value.

  Note that the threshold information (40) is, for example, between an upper limit value (upper threshold value) and a lower limit value (lower threshold value) as long as it is a parameter capable of comparing and determining the memory capacity that can be newly stored in the buffer memory unit (20). Any value may be added as threshold information.

  Further, although not shown, parameter values such as threshold information (40) may be set from a CPU or an external PC provided in the apparatus and dynamically changed.

  The value of the threshold information (40) may be a value that matches the data amount of the input data A and the input data B stored in the memory in the buffer memory unit (20) with a system request or a user request.

  If the width between the upper limit value (upper threshold value) and the lower limit value (lower threshold value) of the threshold information (40) is narrowed, the variation in the input / output data transfer time of the memory included in the buffer memory unit (20) is reduced and the delay is reduced. Time can be stabilized.

  Further, if the value of the threshold information (40) itself is reduced, the capacity of the memory in the buffer memory unit (20) can be reduced, the input / output data transfer time can be shortened, and the buffer memory unit (20) The resulting data delay time is shortened and the system can operate at high speed.

  Furthermore, by selecting the value of the threshold information (40) as an appropriate setting value, it is possible to control the convergence operation speed of the thinning frequency calculation unit (27) so as to be adapted to the system.

  Regarding the above control, FIG. 5 is a flowchart showing an example of a procedure for setting parameter values of the data input / output control circuit.

  The threshold excess information (44), which is the output of the comparison unit (43), is set so that the buffer memory usage exceeds the upper limit (upper threshold) or falls below the lower limit (lower threshold). ), Control information for converging the buffer memory usage in the buffer memory unit (20) within a range (including 0) between the upper limit value and the lower limit value of the threshold information (40).

This threshold excess information (44) causes the thinning frequency calculation unit (27) to perform clock thinning, that is, data thinning control so as to increase the memory usage of the buffer memory, or to advance the accumulation of data and use the memory. It becomes a command to control to decrease the amount, and the command information is output from the terminal h.
This means that the sampling interval is changed when data is sampled with a clock.

  As described above, the use of the thinning frequency coefficient table (24) that receives the clock error value (30) that is the output of the clock error calculator (23) and the buffer memory that is the output of the clock error adder (25). Thinning frequency calculation unit (27) which receives threshold excess information (44) as a comparison result between the amount (data amount increase / decrease value (42)) and a predetermined threshold (40) output from threshold information unit (26) And the clock control unit (28), the control command for controlling the operation clock for reading the output data B and writing the input data B to the buffer memory unit (20) performed in the device B (100). This is an operation clock control unit that outputs (33).

  Next, as a continuation of the detailed processing described above, the embodiment of the thinning frequency calculation unit (27) will be described in detail with reference to FIG.

  The decimation frequency calculation unit (27) receives the output coefficient value (31) as the output of the decimation frequency coefficient table (24) and the threshold excess information (44) as the output of the clock error addition unit (25). The The processing in this block has a function of calculating and outputting a thinning frequency value (32) from these two pieces of input information according to the following averaging calculation formula.

Tav = α × Tav + β × (Tin + L) (1)
Tav: Clock thinning frequency value (32)
[Output value of thinning frequency calculation unit (27)]
Tin: Output coefficient value (31)
[Output value of thinning frequency coefficient table (24)]
L; threshold excess information (44)
[Output value of clock error adder (25)]
α: Arbitrary coefficient value of α <1 β; 1−α

With respect to the calculation formula (1), the main items will be described in detail.
Tav is set to 0 as an initial value. As a result of the calculation, when this value exceeds 0, the clock is thinned out, and when it falls below 0, the clock is increased. The frequency of thinning or increasing increases as the distance from 0 increases.
As shown in the table of FIG. 2, Tin is set to take a larger value in the positive direction than 0 as ΔCLK (the number of clocks B in any period-the number of clocks A) becomes larger than 0. On the contrary, the output coefficient value is set to take a larger value in the minus direction than 0 as ΔCLK becomes smaller than 0.

  As a result, if the speed of the clock B is faster than the speed of the clock A, Tav changes in the direction of thinning out the clock B, and if the speed of the clock B is slower than the speed of the clock A, the clock B is increased. Tav changes in the direction to be changed.

  L is a negative value if the device A (radio device) (200) is in the reception mode and the data amount increase / decrease value of the input data A exceeds the upper threshold value, and falls below the lower threshold value. If it is, it becomes a positive value. As a result, when the buffer memory usage of the buffer memory unit (20 (1)) exceeds the upper threshold, Tav changes in the direction of increasing the clock B, and the buffer memory unit (20 (1)) When the buffer memory usage amount falls below the lower threshold, Tav changes in the direction in which the clock B is thinned out.

  On the other hand, if the device A (radio device) (200) is in the transmission mode and the data amount increase / decrease value of the input data B exceeds the upper threshold value, the value becomes a positive value and is lower than the lower threshold value. Negative value. As a result, when the buffer memory usage of the buffer memory unit (20 (2)) exceeds the upper threshold, Tav changes in the direction of thinning out the clock B, and the buffer of the buffer memory unit (20 (2)) When the memory usage is below the lower threshold, Tav changes in the direction of increasing clock B.

  In the equation (1), an arbitrary coefficient value α is a clock included in the clock generator A (3) and the devices B (I / O board) and (100) included in both devices (device A (radio device) (200)). With respect to the clock generated and input by the generator B (1)), the count value of the clock A, which is the number of clocks of the counter A (21) output, and the count value of the clock B, which is the number of clocks of the counter B (22) output, Is a parameter that determines the speed at which the value of Tav [decimation frequency value (32)] is decreased at the time when becomes equal.

  Although this value is a predetermined fixed value, although not shown, it may be set and dynamically changed by a CPU or an external PC provided in the system.

The value of α is smaller than 1, and Tav [decimation frequency value (32)] decreases (converges) at a faster rate as the value becomes smaller than 1.
In other words, the response speed increases when an abnormality occurs where the clock error is large.
α is a value that approximates to 1 as a normal coefficient value that does not cause a clock error.
β is a fixed value (set value) and is set to 1−α.

  The buffer memory usage in the buffer memory unit (20) is converged to the buffer memory usage in the buffer memory unit (20) within the range (including 0) between the upper limit value and the lower limit value of the threshold information (40). In this state, the value of L [threshold excess information (44)] is always 0.

An embodiment in which specific numerical values are applied will be described below.
When the value of the count α is set to 0.98 and the value of the count β is set to 0.02, Equation (1) is Tav = 0.98 × Tav + 0.02 × (Tin + L).
If no clock error is detected, L [threshold excess information (44)] may be regarded as zero, 0.02 × Tin in equation (1) is also regarded as zero (Tin = 0 according to FIG. 2), and Since both sides can be regarded as 1Tav, the thinning operation is not performed.
If the buffer memory usage is a convergence operation from an area where the range between the upper limit value and the lower limit value of the threshold information (40) is exceeded, the upper limit value and lower limit value as the calculation result of the clock error adding unit (25) are calculated. The value L [threshold excess information (44)] indicating the excess amount out of the range enters equation (1), and a new value of Tav [decimation frequency value (32)] is generated when an abnormality occurs with a large clock error. Is obtained.

  In this way, by using the averaging method of adding and averaging a plurality of clock error values at each clock error detection timing using the two coefficients α and β, the obtained averaged result value is set as Tav. Calculated.

  By changing the Tav value, the buffer memory usage is converged within a desired threshold range.

  By averaging the thinning frequency values as in the equation (1), the error obtained from the speed difference between the clock A and the clock B is gradually converged, and the deterioration of the data quality due to the data thinning is suppressed as much as possible. The buffer memory usage in the buffer memory unit (20) is controlled to be stable, that is, converged to the desired buffer memory usage that has been set, and the fluctuation of the data transfer delay time in the buffer memory usage And data transmission between the systems (device A and device B) is stabilized.

  In addition, since the data can be transferred while absorbing the clock error, it is possible to prevent problems such as a large loss of data during the data transfer process.

It is a block diagram which shows embodiment of the data input / output control circuit of this invention. It is a table figure which shows the Example of the thinning-out frequency count table of the data input / output control circuit of this invention. It is a block diagram which shows the clock error addition part of the data input / output control circuit of this invention. It is a characteristic view which shows the buffer usage-amount and time passage of the data input / output control circuit of this invention. It is a flowchart which shows the procedure which sets the parameter value of the data input / output control circuit of this invention.

Explanation of symbols

1 Clock generator B
2 Data input / output control circuit 3 Clock generator A
20 Buffer memory section 21 Counter A
22 Counter B
23 clock error calculation unit 24 decimation frequency coefficient table 25 clock error addition unit 26 threshold information unit 27 decimation frequency calculation unit 28 clock control unit 41 buffer usage calculation unit 43 comparison unit 100 device B (I / O board)
200 Device A (radio device)

Claims (1)

In a data input / output control circuit that controls input / output of data between its own device and another device,
A buffer memory for writing and reading the data interfaced to the other device according to the clock of the other device;
A clock error detection unit for detecting a clock error between the clock of the device itself and the clock of the other device;
A buffer memory usage calculating unit that calculates the usage of the buffer memory based on the count values of the clock of the own device and the clock of the other device;
A comparison unit that compares the usage amount of the buffer memory with a predetermined threshold;
An operation clock controller that controls an operation clock for reading and writing the data to and from the buffer memory performed by the device according to a comparison result between the usage amount of the buffer memory and the predetermined threshold value and the clock error; ,
A data input / output control circuit comprising:

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