JP2008256657A - Encoder for motor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent wrong counting in an encoder for a motor. <P>SOLUTION: This encoder 1 for the motor has an encoder substrate 3 stored in the motor, and a driver 5 connected by a cable 4 and is arranged outside the motor. The encoder substrate 3 has differential A/D converters 12, 14 for converting the analog signal of pseudo-sine wave output from an optical pick-up 11 into a digital signal, to be output serially, and comparators 13, 15 for detecting a code change of the pseudo-sine wave. Signals serially output from the differential A/D converters 12, 14 and the comparators 13, 15 are subjected to multiplication processings in a multiplication-dedicated IC 22 in the driver 5. The multiplication dedicated IC 22 has an error correction circuit 35 and corrects the combined value of counted values of the differential A/D converters 12, 14 and the counted values of the signals from the comparators 13, 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a motor encoder.

  For example, an encoder may be used as a sensor for detecting the rotational position of the rotor when controlling the rotation of the motor. In an encoder used for this kind of application, an analog signal composed of a periodic function is generated according to the rotation of the rotor. Therefore, a digital pulse signal is created by an analog / digital (hereinafter referred to as A / D) converter to generate a stator signal. The timing which switches energization of a coil is calculated (for example, refer to patent documents 1).

Here, the conventional encoder has a configuration in which an encoder board used in a motor is connected to a driver by a cable. The encoder board includes an optical pickup that detects rotation of a scale fixed to the rotor, an A / D converter that receives a pseudo sine wave output output from the optical pickup, and an A / D that receives a pseudo cosine wave output. A D converter, an IC (integrated circuit) for multiplying a digital signal from each A / D converter by 4 and a level conversion circuit are mounted. Here, in order to create a quadruple pulse signal, it is necessary to always detect a sign change of a pseudo sine wave or a pseudo cosine wave (hereinafter collectively referred to as a pseudo sine wave). For this reason, the capability required of the A / D converter needs to be able to perform A / D conversion at a frequency larger than the cycle for calculating the timing for switching the energization to the motor. For example, when using a scale with 1024 slits in one circle and rotating at 6000 rpm (100 Hz), a frequency of 100 Hz × 1024 × 4 = 409.6 kHz or more is necessary to correctly determine the change in sign. A / D conversion is required. For this reason, the conventional motor encoder uses a high-speed differential A / D converter, and employs parallel communication for communication with the multiplication IC.
Japanese Utility Model Publication No. 61-82216

However, when the motor encoder generates a signal multiplied by using a plurality of signals, the count value may be greatly shifted if the timing at which the signal is output is shifted.
Further, since the high-speed differential A / D converter has a large circuit size, the encoder board cannot be miniaturized. In addition, as shown in Patent Document 1, it is necessary to perform parallel connection between the high-speed differential A / D converter and the multiplication-dedicated IC using a large number of wires. Such wiring has been a cause of hindering miniaturization of the encoder board. Furthermore, the multiplication-dedicated IC is also difficult to miniaturize because a large number of terminals are required for parallel communication. For these reasons, it has conventionally been difficult to reduce the size of the encoder board, and it has also been difficult to reduce the size of the motor incorporating the encoder board.
The present invention has been made in view of such circumstances, and a main object thereof is to prevent erroneous counting of a motor encoder.

The invention according to claim 1 of the present invention that solves the above-described problem includes a detection unit that is attached to a motor, and a driver that is disposed outside the motor and is connected to the detection unit so as to enable data communication. A motor encoder, a pickup that outputs a pseudo sine wave analog signal as the motor rotates, an analog / digital converter that converts the analog signal output from the pickup into a digital signal and serially outputs the digital signal; A comparator that generates a pulse-like sign change signal whose signal level changes with a sign change of the analog signal with respect to a reference potential, and a digital signal output from the analog / digital converter and the comparator, and performs multiplication processing A multiplier, and the multiplier is output from the analog / digital converter. A first multiplication circuit for calculating a first multiplication count value from the digital signal, and a second multiplication circuit for generating a second multiplication count value by counting the code change of the code change signal output from the comparator And a synthesis circuit for synthesizing the first multiplied count value and the second multiplied count value to generate a synthesized multiplied count value, and a difference between the previous synthesized multiplied count value and the current synthesized multiplied count value is predetermined. The motor encoder is characterized by having an erroneous count correction circuit that corrects the deviation of the count value when the value becomes equal to or greater than.
When the output timing of the analog / digital converter is different from the output timing of the comparator, the current value of the combined multiplication count value is greatly different from the previous value. Therefore, correction is performed according to the difference between the current value and the previous value so that a correct count value is obtained.

According to a second aspect of the present invention, in the motor encoder according to the first aspect, the erroneous count correction circuit is configured such that the difference between the previous combined multiplied count value and the current combined multiplied count value exceeds a first threshold value. A composite multiplication count value corrected by 2 counts of the second multiplication count value is generated, and if it is less than the first threshold and greater than or equal to the second threshold, the composite multiplication count value corrected by 1 count of the second multiplication count value It is characterized by producing | generating.
When the difference between the previous combined multiplication count value and the current combined multiplication count value is large, the motor encoder corrects the second multiplied count value by one count or two counts. When the current combined multiplied count value is larger than the first and second threshold values with respect to the previous combined multiplied count value, 2 counts and 1 count are respectively subtracted. When the current combined multiplication count value is smaller than the first and second threshold values with respect to the previous combined multiplication count value, 2 counts and 1 count are added respectively.

According to a third aspect of the present invention, in the motor encoder according to the second aspect, the first threshold value is a value corresponding to 1.5 counts of the second multiplied count value, and the second threshold value is It is a value corresponding to 0.5 count of 2 multiplied count value.
The motor encoder pays attention to the fact that the error of the combined multiplied count value becomes large when the timing of counting up or counting down the second multiplied count value is shifted, and corrects it in association with the second multiplied count value. .

According to a fourth aspect of the present invention, in the motor encoder according to any one of the first to third aspects, the pickup outputs a pseudo sine wave signal and a pseudo cosine wave signal having a period different by ¼. The analog / digital converter and the comparator include a first analog / digital converter and a first comparator to which a pseudo sine wave signal is input, and a second analog / digital conversion to which the pseudo cosine wave signal is input. And a second comparator.
In this motor encoder, the pickup generates two types of analog signals having different phases. For this reason, two analog / digital converters and two comparators are provided in the detection unit, respectively, and corresponding digital signals are sent to a driver outside the motor and multiplied.

According to a fifth aspect of the present invention, in the motor encoder according to any one of the first to fourth aspects, the analog / digital converter and the comparator are provided in the detection unit, and the multiplication unit is the driver. It is characterized by being provided in.
In this motor encoder, a multiplication unit that performs multiplication processing is arranged outside the motor. The digital data serially output from the analog / digital converter is sent to the driver and processed. Since the change in the sign of the analog signal output from the detection unit can be checked by referring to the output of the comparator, the signal output frequency of the analog / digital converter can be lowered.

  According to the present invention, since the combined multiplication count value is created using the analog / digital converter and the comparator, the rotation of the motor can be detected with a simple configuration. At this time, if the signal output timings of the analog / digital converter and the comparator are shifted, the combined multiplication count value is corrected by the erroneous count correction circuit, so that a correct count value can be obtained.

The best mode for carrying out the invention will be described in detail with reference to the drawings.
The encoder 1 includes a scale 2 fixed to the rotation shaft of the rotor of the motor, and includes an encoder board 3 mounted in the motor and a driver 5 connected via a cable 4.

  The scale 2 has a configuration in which slit rows are provided in an opaque disk. The slit row is provided with slits in the circumferential direction in order to output a pseudo sine wave. The slit has a large number of, for example, 1024 first slit rows provided in the circumferential direction, and a second slit provided only at one location in the circumferential direction. The first slit row is used to detect the rotation angle of the rotor. The second slit is used when measuring the number of rotations of the motor or resetting the count value of the encoder 1. Note that the scale 2 may have a configuration in which a portion that reflects light and a portion that does not reflect light on a disk such as glass are provided at equal intervals in the circumferential direction.

  The encoder board 3 is a detection unit having an optical pickup 11 arranged close to the scale 2. The output of the optical pickup 11 is sent to the first differential A / D converter 12, the first comparator 13, the second differential A / D converter 14 and the second comparator 15 mounted on the encoder board 3. It is connected. Furthermore, a level conversion circuit 16 used when transmitting and receiving signals is also mounted.

  If the optical pickup 11 is a transmissive type, the light emitting element and the light receiving element are arranged with the slit of the scale 2 interposed therebetween, and if the optical pickup 11 is a reflection type, the light emitting element and the light receiving element are arranged on the same side of the scale 2 In this case, an analog signal that periodically changes corresponding to the first slit row is output. In this embodiment, as an analog signal, a pseudo sine wave signal that is a pseudo sine wave signal and a pseudo cosine wave signal that is a pseudo sine wave signal whose phase is shifted by ¼ period from the pseudo sine wave signal are generated. Is configured to do. The optical pickup 11 outputs a pseudo sine wave signal and a pseudo cosine wave signal as differential outputs with respect to the reference potential. Specifically, the pseudo sine wave signal is output as a pseudo sine plus signal Asin1 that is a plus component from the reference potential and a pseudo sine minus signal Asin2 that is a minus component from the reference potential. Similarly, the pseudo sine wave signal is output as a pseudo cosine plus signal Acos1 that is a plus component from the reference potential and a pseudo cosine minus signal Acos2 that is a minus component from the reference potential. Further, an index signal Ix that is output once corresponding to the second slit is output to the level conversion circuit 16 every time the scale 2 rotates once.

The first differential A / D converter 12 performs A / D conversion on the pseudo sine plus signal Asin1 and the pseudo sine minus signal Asin2 output from the optical pickup 11, and digitizes the analog pseudo sine wave signal. The digital signal Dsin is serially output.
The second differential A / D converter 14 performs A / D conversion on the pseudo cosine plus signal Acos1 and the pseudo cosine minus signal Acos2 output from the optical pickup 11, and digitizes the analog pseudo cosine wave signal. The digital signal Dcos is serially output.
Each of the differential A / D converters 12 and 14 receives the control signal AD1 and the clock signal AD2 from the level conversion circuit 16, and outputs the first and second digital signals Dsin and Dcos in synchronization with each other at a predetermined time. It has come to be.

The first comparator 13 serially outputs a sign change signal Csin of a pseudo sine wave signal from the pseudo sine plus signal Asin1 and the pseudo sine minus signal Asin2 output from the optical pickup 11. The sign change signal Csin is a signal indicating whether the pseudo sine wave signal is a positive value or a negative value with respect to the reference potential.
The second comparator 15 serially outputs a sign change signal Ccos of a pseudo sine wave signal from the pseudo cosine plus signal Acos1 and the pseudo cosine minus signal Acos2 output from the optical pickup 11. The sign change signal Ccos is a signal indicating whether the pseudo cosine wave signal is a positive value or a negative value with respect to the reference potential.

  The level conversion circuit 16 receives the digital signals Dsin, Dcos, Csin, Ccos serially output from the differential A / D converters 12 and 14 and the comparators 13 and 15, and the index signal Ix, and the signal of the cable 4 It is configured to output to the driver 5 through a line. The level conversion circuit 16 improves the noise resistance by converting the differential signal according to the standard to RS-422, LVDS (Low Voltage Differential Signaling), etc., and transmitting the data from the cable 4 to the driver 5. Yes. Further, power is supplied to each circuit of the encoder board 3 via the cable 4.

Here, the number of terminals required for receiving digital signals from the differential A / D converters 12 and 14 is two. Similarly, the number of terminals necessary for receiving the sign change signals Csin and Ccos from the comparators 13 and 15 is two. Even if the terminal for outputting the control signal AD1 and the clock signal AD2 and the terminal for the index signal Ix are combined, the number of terminals required for data input of the level conversion circuit 16 is only seven. On the other hand, when performing parallel communication like a conventional A / D converter, for example, in 12-bit data output, a total of 15 terminals including 12 terminals and 3 terminals for signals AD1, AD2, and Ix. A terminal was required.
When transmitting 12-bit data output in parallel via the cable 4, 12 signal lines are required, and when using differential signals, 12 × 2 = 24 signal lines are required. become. On the other hand, the level conversion circuit 16 needs only 4 × 2 = 8 signal lines even when a differential signal is used.

The driver 5 includes a level conversion circuit 21, a multiplication-dedicated IC 22 that is a multiplication unit, and a control CPU (central processing unit) 23.
The multiplication-dedicated IC 22 includes an interface circuit 31 to which a signal output from the encoder board 3 is input, a first multiplication circuit 32 that multiplies the A / D converted digital signals Dsin and Dcos, and code conversion signals Csin and Ccos. A two-phase encoder counter 33 that is a second multiplication circuit that creates a multiplied pulse signal and counts up or down, a combined multiplied count value generation circuit 34, and an erroneous count correction circuit 35 that corrects erroneous counting. Have.

The synthesized multiplication count value generation circuit 34 synthesizes the first multiplication count value generated by the first multiplication circuit 32 and the second multiplication count value generated by the counter 33 for the two-phase encoder, thereby synthesizing the multiplication count value. Is generated.
As shown in FIG. 2, the erroneous count correction circuit 35 includes a subtraction circuit 41 and a correction circuit 42 to which the count value before correction is input, and is configured to output the count value corrected by the correction circuit 42. . The corrected count value is stored in the storage register 43, and the corrected count value can be input to the subtraction circuit 41 as necessary. The output of the subtraction circuit 41 is connected to the input of the correction circuit 42.

Next, processing for detecting rotation of the motor by the encoder 1 of this embodiment will be described.
When the rotor of the motor rotates, the scale 2 fixed to the rotating shaft rotates together. Light emitted from the light emitting element of the optical pickup 11 is transmitted or reflected through the scale 2 and input to the light receiving element. An optical signal is output from the optical pickup 11 in accordance with the amount of light received by the light receiving element. The analog signal has a pseudo sine waveform, and a first pseudo signal and a second pseudo signal whose phases are shifted by 90 degrees depending on the arrangement of the scale 2, the light emitting element, and the light receiving element are output. Hereinafter, the first pseudo signal is a pseudo sine wave signal and the second pseudo signal is a pseudo cosine wave signal. Since the optical pickup 11 is configured to output a differential signal from a reference potential, as shown in FIG. 3, the pseudo sine wave signal is a pseudo sine plus signal composed of a component having a higher potential than the reference potential. Asin1 and a pseudo sign minus signal Asin2 composed of a component whose potential is lower than the reference potential are output. Similarly, the pseudo cosine wave signal outputs a pseudo cosine plus signal Acos1 composed of a component having a higher potential than the reference potential and a pseudo cosine minus signal Acos2 composed of a component having a potential lower than the reference potential.

The pseudo sine plus signal Asin1 and the pseudo sine minus signal Asin2 are input to the differential A / D converter 12 and the first comparator 13, respectively. The differential A / D converter 12 receives the command of the control signal AD1 and digitally converts the pseudo sine plus signal Asin1 and the pseudo sine minus signal Asin2 at regular intervals to create a first digital signal Dsin, and performs level conversion. Serial output to the circuit 16. The frequency of generating the first digital signal Dsin may be a frequency equal to or lower than the frequency of the pseudo sine wave.
The first comparator 13 compares the pseudo sine plus signal Asin1 and the pseudo sine minus signal Asin2 to create a sign change signal Csin and serially outputs it. As a result, as shown in FIG. 3, a pulse signal in which the high level and the low level are switched in accordance with the change in the pseudo sine wave signal is obtained.

The pseudo cosine plus signal Acos 1 and the pseudo cosine minus signal Acos 2 are input to the differential A / D converter 14 and the second comparator 15, respectively. In the same manner as described above, the differential A / D converter 14 receives the command of the control signal AD 1, converts the analog signal into a second digital signal Dcos at a predetermined time, and generates a second digital signal Dcos. Output. The second digital signal Dcos is generated in synchronization with the first digital signal Dsin.
The second comparator 15 generates a sign change signal Ccos for the pseudo cosine wave signal and serially outputs it. As a result, as shown in FIG. 3, a pulse signal in which the high level and the low level are switched in accordance with the change in the pseudo cosine wave signal is obtained. The sign change signal Ccos is a pulse signal that is shifted from the sign change signal Csin by a quarter of the period of the pseudo sine wave.

Digital signals output from the differential A / D converters 12 and 14 and the comparators 13 and 15 are transmitted to the driver 5 via the level conversion circuit 16 and the cable 4. In the driver 5, the digital signal is transferred from the level conversion circuit 21 to the multiplication-dedicated IC 22. The multiplication dedicated IC 22 performs data processing under the control of the CPU 23.
The two-phase encoder counter 33 checks the sign change of the sign change signals Csin and Ccos and detects the rotation direction from the sign change. For example, like the code change signals Csin and Ccos in FIG. 3, the combination of the signal level of the code change signal Ccos for the pseudo cosine wave signal and the code change signal Csin for the pseudo sine wave signal with the passage of time is (Hihg, High). Is switched to (Low, High), that is, when the sign change signal Ccos changes prior to the sign change signal Csin, the motor is considered to be counterclockwise and is counted up each time the sign is switched.

  For example, when the count number at the start of counting is “n”, every time the sign of the sign change signal Csin, Ccos changes, “n + 1”, “n + 2”, “n + 3”, “n + 4”, A quadruple count value that counts up as “n + 5”, “n + 6”, and “n + 7” is calculated as the second multiple count value.

Further, the first multiplication circuit 32 calculates a first multiplication count value from digital signals Dsin and Dcos obtained by A / D converting the pseudo sine wave signal and the pseudo cosine wave signal. The first multiplication count value is calculated from the phase tan ⁻¹ of the pseudo sine wave (value of the first digital signal Dsin / second digital signal Dcos). In this embodiment, as indicated by the line L1, the signal is reset after being counted up to 1024 counts corresponding to the number of slits of the scale 2.

  The first and second multiplied count values are synthesized by the synthesized multiplied count value generation circuit 34, and as indicated by the line L2, the value counted up stepwise by the quadruple pulse signal (see the line L2a) is 1 A combined multiplication count value that linearly complements between the two count values is obtained. As an example of calculating the combined multiplication count value, in this embodiment, a value obtained by multiplying the second multiplication count value by 256 is added to the lower 8-bit signal (see line L3) of the first multiplication count value. ing.

On the other hand, when the motor rotates in reverse, a pseudo sine wave signal and a pseudo cosine wave signal as shown in FIG. 4 are obtained. At this time, the combination of the signal levels of the code change signals Csin and Ccos changes the code change signal Csin prior to the code change signal Ccos. The driver 5 assumes that the motor is rotating clockwise, and counts down every time the code is switched.
For example, when the count number at the start of counting is “n”, every time the sign of the sign change signal Csin, Ccos changes, “n−1”, “n-2”, “n-3” ”,“ N−4 ”,“ n−5 ”,“ n−6 ”, and“ n−7 ”, the second multiplied count value is obtained.

The first multiplication circuit 32 calculates the phase tan ⁻¹ of the pseudo sine wave from the digital signals Dsin and Dcos and generates a first multiplication count value. As indicated by the line L4, the signal counts down from 1024 corresponding to the number of slits of the scale 2 and is reset when the count value becomes zero. The combined multiplication count value generation circuit 34 linearly complements between one count value when counting down step by step with the second count value multiplied by four (see line L5a), as indicated by line L5. A composite multiplication count value is generated. Also in this case, a value obtained by multiplying the second multiplied count value by 256 is added to the lower 8 bits of the first multiplied count value (see line L6).

  Further, the combined multiplication count value is input to the erroneous count correction circuit 35 and is corrected when there is an erroneous count. The processing of the erroneous count correction circuit 35 is shown in the flowchart of FIG. The erroneous count correction circuit 35 stores the previous combined multiplication count value in the storage register 43 in advance (step S101). When the current combined multiplication count value is newly input, the subtraction circuit 41 calculates a difference between the previous combined multiplication count value and the newly input current combined multiplication count value (step S102). The result of the subtraction is input to the correction circuit 42. When the difference is larger than 1.5 counts of the 4th count value that is the second multiplied count value (Yes in step S103), the correction circuit 42 decreases the 4th count value by 2 counts (step S104). When the difference is less than 1.5 counts of the quadruple count value (No in step S103) and larger than 0.5 counts of the quadruple count value (Yes in step S105), the quadruple count value is one count. Decrease (step S106).

  On the other hand, when the difference is less than −1.5 counts of the 4-fold count value (Yes in step S107), the 4-fold count value is increased by 2 counts (step S108). When the difference is larger than the -1.5 count of the quadruple count value (No in step S107) and smaller than the -0.5 count of the quadruple count value (Yes in step S109), the quadruple count value is set to 1. The count is increased (step S110). In other cases, the count value is not corrected. In other words, the difference between the current combined multiplication count value and the previous combined multiplication count value stored in the storage register 43 is examined, and the difference is the first threshold value (1.5 counts for each difference of plus or minus). Or a different correction value is selected depending on whether the difference is between the first threshold value and the second threshold value (0.5 counts for each of plus and minus differences).

Here, when the difference between the previous combined multiplied count value and the current combined multiplied count value is larger than 0.5 count of the 4 multiplied count value and not more than 1.5 count (corresponding to Yes in step S105), FIG. It demonstrates concretely with reference to.
The sign change signals Csin and Ccos are supposed to change in sign at a position where the pseudo cosine wave signal or the pseudo sine wave signal crosses the reference potential as shown in part by broken lines. An error may occur between the detection timing of the cross point of the first and second comparators 13 and 15 and the sample / hold timing of the A / D conversion due to a delay of the circuit. For example, when it is determined that a sign change has occurred at a timing before the actual cross point as indicated by the sign change signals Csin and Ccos indicated by the solid line, the count value at the corresponding position is discontinuous as indicated by the line L2. Become bigger. This is because the quadruple count value that is the second multiple count value is counted up to “n + 2” at an early timing as indicated by the line L2a, and the value obtained by adding the first multiple count value to this increases. .
Therefore, in this case, if the combined multiplied count value is calculated by reducing the multiplied count value by one count in step S106, a continuous count value can be obtained as indicated by a line L7 partially shown by a broken line. become.

Also, when it is considered that the sign change has occurred behind the actual cross point, such as when counting up from “n + 4” to “n + 5” with the second multiplication count value, as shown in line L2, The count value at the position to be reduced becomes discontinuously small. The quadruple count value, which is the second multiple count value, is counted up to “n + 5” at a delayed timing as shown by the line L2a, and the value obtained by adding the first multiple count value to this becomes small. is there.
Therefore, in this case, if the combined multiplication count value is calculated by increasing the quadruple count value by one count in step S110, a continuous count value can be obtained as indicated by a line L7 partially shown by a broken line. become.

In this embodiment, since the multiplication-dedicated IC 22 is mounted on the driver 5 side, it is not necessary to mount a large IC on the encoder board 3 accommodated in the motor, and the encoder board 3 can be reduced in size.
Since the serial output A / D converters 12 and 14 are used, the number of signal lines between the A / D converters 12 and 14 and the level conversion circuit 16 can be reduced, and the encoder board 3 can be downsized. The fact that the A / D converters 12 and 14 can be downsized as compared with the type that performs high-speed processing also contributes to downsizing of the encoder board 3. Since the number of signal lines required for the cable 4 can be reduced by using the serial output, the cable 4 can be made thinner. Since the number of signal lines of the cable 4 is reduced, the connector for connecting the cable 4 to the encoder board 3 can be reduced, and the encoder board 3 can be further reduced in size.
In the A / D converters 12 and 14 that output serially, the frequency of data conversion may be lower than the frequency of the sign change of the pseudo sine wave. However, since the sign change can be determined from the outputs of the comparators 13 and 14, the second An accurate count value can be obtained by adding the count values obtained when A / D conversion is performed based on the multiplied count value. For this reason, even if the frequency of data conversion of the A / D converters 12 and 14 is small, the rotation detection of the motor can be reliably performed.

  Further, in this embodiment, the erroneous count correction circuit 35 compares the previous value of the combined multiplication count value with the current value, and when the difference is equal to or greater than a predetermined value, it is determined that the count is abnormal and correction is performed. Therefore, erroneous counting is prevented. For example, when a motor rotation encoder with a resolution of one rotation is 20 bits and the sampling period is 50 μsec, a change of 128 in the combined multiplication count value corresponds to a rotation speed of 100 rpm. impossible. Therefore, when the difference between the count values exceeds 128 (corresponding to 0.5 count of the second multiplied count value), 256 (corresponding to 1 count of the second multiplied count value) is subtracted to obtain the correct count value. It can be corrected.

Note that the present invention can be widely applied without being limited to the above-described embodiment.
For example, the output signal of the optical pickup 11 and the data transmitted / received via the cable 4 need not use a differential output.
The optical pickup 11 may output one type of analog signal and generate a rotation detection count value based on the analog signal.
The values of the first threshold value and the second threshold value are values suitable for correcting a shift of 1 count by 2 counts of the second multiplied count value not limited to 1.5 counts and 0.5 counts. I just need it.

It is a block diagram of the encoder for motors concerning an embodiment of the invention. It is a block diagram which shows the detail of an erroneous count correction circuit. It is a figure explaining the relationship between the pseudo sine wave at the time of forward rotation, and a count value. It is a figure explaining the relationship between the pseudo sine wave at the time of reverse rotation, and a count value. It is a flowchart explaining an erroneous count correction process. It is a figure which shows the example which an erroneous count generate | occur | produces.

Explanation of symbols

1 Motor encoder 2 Scale 3 Encoder board (detector)
4 Cable 5 Driver 11 Optical Pickup 12 First Differential A / D Converter 13 First Comparator 14 Second Differential A / D Converter 15 Second Comparator 16, 21 Level Conversion Circuit 22 Dedicated Multiplication IC ( Multiplication unit)
23 CPU
32 First multiplication circuit 33 Counter for two-phase encoder (second multiplication circuit)
34 Composite Multiplication Count Value Generation Circuit 35 Error Count Correction Circuit 41 Subtraction Circuit 42 Correction Circuit 43 Encoder Value Saving Register

Claims (5)

A motor encoder having a detection unit attached to a motor and a driver disposed outside the motor and connected to the detection unit so as to be able to perform data communication,
A pickup that outputs a pseudo sine wave analog signal as the motor rotates,
An analog / digital converter that converts an analog signal output from the pickup into a digital signal and serially outputs the comparator, and a comparator that generates a pulse-like code change signal whose signal level is switched in accordance with a change in the sign of the analog signal relative to a reference potential And a multiplier for receiving and multiplying the digital signals output from the analog / digital converter and the comparator,
The multiplication unit counts a sign change of a sign change signal output from a first multiplication circuit that calculates a first multiplication count value from a digital signal output from the analog / digital converter and a comparator. A second multiplication circuit for generating a second multiplied count value; a combining circuit for combining the first multiplied count value and the second multiplied count value to generate a combined multiplied count value; and a previous combined multiplied count value. And an erroneous count correction circuit that corrects the deviation of the count value when the difference between the current and the combined multiplication count value exceeds a predetermined value.   The erroneous count correction circuit generates a combined multiplied count value corrected by 2 counts of the second multiplied count value when the difference between the previous combined multiplied count value and the current combined multiplied count value exceeds the first threshold value. The composite multiplied count value corrected by one count of the second multiplied count value is generated when the value is less than the first threshold value and greater than or equal to the second threshold value. Motor encoder.   The first threshold value is a value corresponding to 1.5 counts of the second multiplied count value, and the second threshold value is a value corresponding to 0.5 counts of the second multiplied count value. The motor encoder according to claim 2.   The pickup outputs a pseudo sine wave signal and a pseudo cosine wave signal having a period different by ¼, and the analog / digital converter and the comparator are a first analog / digital converter to which the pseudo sine wave signal is input. And a first comparator, a second analog / digital converter to which a pseudo cosine wave signal is input, and a second comparator. Encoder for motor.   The motor encoder according to any one of claims 1 to 4, wherein the analog / digital converter and the comparator are provided in the detection unit, and the multiplication unit is provided in the driver.

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