JP2008252535A - Wiretap detector and clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiretap detector which automatically and periodically detects the presence/absence of wiretapping, and to provide a clock. <P>SOLUTION: A radio wave modification clock 1 has the wiretap detector 2 for detecting wiretapping, and a clock part 3. The wiretap detecting part 2 has a wiretap detecting part 4 inside and shares a sound generating part 5 held by the clock part 3 with the clock part 3. In addition, the radio wave modification clock 1 has an alarm (alarm clock) function of notifying the time by raising predetermined sound (alarm sound), when a set time (alarm (alarm clock) time) preset by a user is reached. Furthermore, the radio wave modification clock 1 has a function of receiving radio wave signal, containing standard time signal transmitted from a standard radio wave broadcasting station 7, to correct the time counted by an internal clock. The wiretap detector 2 detects the wiretap 6 at the alarm time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an eavesdropper detector and a timepiece for detecting an eavesdropper.

An eavesdropper detector that detects the presence or absence of an eavesdropper by detecting the radio signal emitted by the eavesdropper, or a sound wave signal that is emitted from the speaker is emitted as a radio signal from the eavesdropper. An eavesdropper detector that detects whether or not an eavesdropper is detected is known (see, for example, Patent Documents 1 and 2).
JP-A-49-24089 JP 2000-332635 A

  In any of the above-described bug detectors, the user (user) must search for the bug by operating the bug detector.

  In addition, immediately after searching for a wiretap by the wiretap detector, the reliability of the detection result by the wiretap detector is high, but the reliability of the detection result decreases with time. For example, even if a wiretap is installed in a house by a third party and the user detects and removes the wiretap by using the wiretap detector, the wiretap is detected by a person entering or leaving the house or an intruder afterwards. May be installed again. Therefore, the user has to search for the eavesdropper again.

  Furthermore, wiretap detectors are not easy to buy for everyone, including women.

  An object of the present invention is to provide a wiretap detector and a watch that automatically and periodically detect the presence of a wiretap.

  The wiretap detector according to the first aspect of the present invention includes a wiretap detector that emits a specific sound and determines whether the received sound is a specific sound generated by itself and detects the wiretap, and at least the specific sound. And a watch including a sound generation unit for emitting a sound including the sound, and the wiretap detection unit shares the sound generation unit of the watch.

  Preferably, the timepiece has a function of sounding at a set time, and the wiretap detector detects the wiretap using a specific sound sounded by the sounding unit of the timepiece at the set time.

  Preferably, the eavesdropper detection unit includes an informing unit for informing a detection result of the eavesdropper.

  Preferably, the eavesdropper detection unit includes a detection unit that detects a reception level of the radio signal, a scan unit that scans the frequency of the radio signal, and a switching unit that switches a scan speed of the scan unit, The switching unit switches the scanning speed of the scanning unit according to the reception level.

  A timepiece according to a second aspect of the present invention includes a wiretap detector that detects a wiretap by determining whether or not a received sound is a sound generated by itself, and a sound including the sound specified above. A sound generation unit for generating sound and a function of sounding at a set time, and the wiretap detection unit shares the sound generation unit.

  Preferably, it has a clock receiver for receiving a radio signal including a standard time signal, and the clock receiver receives the radio signal and corrects the time of the internal clock.

  According to the present invention, the presence of an eavesdropper can be detected automatically and periodically.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a main part of each component in one embodiment of a radio wave correction timepiece according to this embodiment.

  In FIG. 1, only the main parts of the wiretap detector 2 and the clock unit 3 are illustrated in order to briefly explain the outline of the present embodiment. Details of the wiretap detector 2 and the clock unit 3 will be described later.

  A radio-controlled timepiece 1 shown in FIG. 1 has a wiretap detector 2 for detecting a wiretap and a clock unit 3. In addition, the radio-controlled timepiece 1 has an alarm (alarm) for notifying a predetermined sound (alarm sound) when a preset time set by the user in advance (hereinafter, this set time is referred to as an alarm (alarm) time). ) Has a function. Furthermore, the radio-controlled timepiece 1 has a function of receiving a radio signal including a standard time signal transmitted from the standard radio broadcast station 7 and correcting the time measured by the internal clock.

  The wiretap detector 2 has a wiretap detector 4 inside thereof, and shares the sounding unit 5 of the clock unit 3 with the clock unit 3.

  The eavesdropper detection unit 4 includes, for example, a reception antenna 41, a reception circuit 42, a reception frequency scanning system 43, a signal processing system 44, a microcomputer 45, and a notification unit 46.

  The timepiece unit 3 includes, for example, a timepiece receiving unit 31, a timepiece display unit 32, and a control circuit 33 including a timepiece receiving antenna 311 and a long wave receiving circuit 312. Further, the clock unit 3 has a sound generation unit 5 and is shared with the wiretap detector 2.

  The sound generation unit 5 includes, for example, a signal generator 51 and a speaker 52, and is shared by the wiretap detector 2 and the clock unit 3.

  Next, each component of the radio-controlled timepiece 1 according to this embodiment will be described.

  For example, the radio-controlled timepiece 1 shown in FIG. 1 notifies an alarm time with an alarm sound. The radio-controlled timepiece 1 receives a standard radio signal including a standard time signal, and corrects the time measured internally based on the reception result.

  The wiretap detector 2 shown in FIG. 1 causes a specific sound having a predetermined frequency (for example, an audible frequency) to be generated using the sounding unit 5 at an alarm time, and the sounding sound signal is transmitted from the wiretap 6. The presence or absence of the wiretapping device 6 is determined by checking whether or not it is being carried by a certain radio wave. In addition, the bug detector 2 is switched on and off by, for example, a bug detection switch to be described later. For example, the wiretap detector 2 detects the wiretap 6 when the wiretap detection switching switch is on, and the wiretap detector 2 detects the wiretap 6 when the switch is off. Absent.

  The receiving antenna 41 receives a sound wave signal from the microphone 62 of the bug 6 and receives a radio wave signal transmitted via the antenna 61.

  The receiving circuit 42 includes, for example, an amplifier that amplifies a high-frequency signal or an intermediate frequency signal, a mixer that multiplies two signals having different frequencies, a detector that performs detection, and the like. The sound signal is output to the signal processing system 44. The reception circuit 42 has a detection unit that detects the reception level of the signal, for example, performs a process such as amplification on the received radio wave signal, detects the reception level of the reception signal, and outputs it to the microcomputer 45.

  The reception frequency scanning system 43 includes, for example, a scanning unit that scans a tuning frequency, a switching unit that switches a scanning speed, a voltage controlled oscillator (VCO; Voltage Controlled Oscillator, hereinafter referred to as VCO) that oscillates at a frequency according to an input voltage, and the like. The tuning unit continuously scans the tuning frequency at a scanning speed according to the control of the microcomputer 45, generates a signal having an oscillation frequency according to the scanning result by the VCO, and outputs the signal to the receiving circuit 42. .

  The signal processing system 44 includes, for example, a bandpass filter that passes only a signal having a predetermined frequency component, a detector that performs detection, and the like, and extracts a signal having a predetermined frequency component from the audio signal input from the receiving circuit 42. Detection is performed and an audio signal is output to the microcomputer 45.

  The microcomputer 45 receives the audio signal from the signal processing system 44, the reception level of the reception signal from the reception circuit 42, and the control signal from the control circuit 33 of the clock unit 3 at the alarm time, and receives the reception frequency according to these signals. The scanning system 43, the notification unit 46, and the signal generator 51 are controlled.

  Based on the control of the microcomputer 45, the notification unit 46 notifies information such as the detection result of the bug 6 for example. Note that the configuration of the notification unit 46 is not particularly limited, and for example, a lamp, a display for displaying image or character information, or the like can be employed.

  Next, each component of the timepiece unit 3 according to the present embodiment will be described.

  The timepiece unit 3 shown in FIG. 1 performs time measurement, time display, correction of timekeeping time of an internal timepiece using a standard radio signal, notification of alarm time, and the like.

  The watch receiving antenna 311 of the watch receiving unit 31 is, for example, a long-wave burn antenna or a coreless antenna, and receives a long-wave standard radio wave including a standard time signal transmitted from the standard radio wave broadcasting station 7, for example.

  The long wave receiving circuit 312 includes, for example, a detector, a rectifier circuit, an RF amplifier, an integrating circuit, and the like. Signal processing is performed, and the processing result is output to the control circuit 33 as a pulse signal, for example.

  The clock display unit 32 is configured by, for example, a liquid crystal panel, and displays a time display including an alarm time, a reception state of a standard radio wave signal, and the like based on the control of the control circuit 33, for example. In the clock display unit 32 according to the present embodiment, the display method such as analog or digital, the display content, and the like are not particularly limited. For example, it is possible to employ a dial having a minute hand and an hour hand and engraved with seconds, minutes, hours and the like according to the rotational positions of these hands.

  The control circuit 33 is, for example, based on a pulse signal including standard time information input from the long wave receiving circuit 312 or an external operation by a user switch (not shown in FIG. 1). 1, for example, the long wave receiving circuit 312, the clock display unit 32, the microcomputer 45 of the bug detector 4, and the sound generator 5 are controlled. For example, the control circuit 33 corrects the time measurement time to display the time measurement time on the clock display unit 32, and controls the sound generation unit 5 to notify the alarm time or the like with an alarm sound. Further, the control circuit 33 controls the microcomputer 45 at the alarm time, so that the bug detector 2 detects the bug 6.

  The sound generation unit 5 is shared by the bug detector 2 and the clock unit 3 and generates a sound wave signal having an audible frequency such as an alarm sound.

  The signal generator 51 is controlled by the control circuit 33 and the microcomputer 45, for example, when the bug detection switch is on, and is controlled by the control circuit 33 when the switch is off. The signal generator 51 converts the input audio signal into a sound wave signal and outputs the sound wave signal via the speaker 52. The sound wave signal is a sound having an audible frequency including, for example, an alarm sound or a melody sound.

  The speaker 52 outputs a sound wave signal having an audible frequency including, for example, an alarm sound or a melody sound.

  The wiretap 6 shown in FIG. 1 receives a sound wave signal with the microphone 62, modulates the high frequency of the carrier wave with this sound wave signal, and transmits the radio wave signal via the antenna 61.

  In addition, the standard radio broadcast station 7 transmits a standard radio signal including a standard time signal.

  Here, the standard time signal transmitted by the standard radio broadcast station 7 will be described.

  FIG. 2 is a diagram showing a specific example of the standard time signal included in the standard radio signal received by the radio-controlled timepiece shown in FIG.

  FIG. 2A shows a specific example of the standard radio signal. FIG. 2B shows an output waveform when the reception state is good. FIG. 2C is a diagram showing a specific example of an output waveform when the reception state is not good and the reception intensity of the radio wave is very weak. FIG. 2D is a diagram showing a specific example of an output waveform when the radio wave reception state is not good.

  For example, a long wave Japanese standard radio wave JJY that conveys the Japanese standard time with high accuracy is sent in a form as shown in FIG.

  Specifically, the standard time signal (also called time code) of JJY is composed of three types of signal patterns: “1” signal, “0” signal, and “P” signal, and each signal pattern is 1 second. They are distinguished by the 100% amplitude period width in (s). In the case of representing a “1” signal, a signal having a predetermined 100% amplitude period of a predetermined frequency is transmitted for 500 ms (0.5 s) in one second (s), and in the case of representing a “0” signal. When a signal having a predetermined frequency is transmitted for 800 ms (0.8 s) in 1 second (s) and represents a “P” signal, only 200 ms (0.2 s) in 1 second (s) A signal having a predetermined frequency is transmitted.

When the reception state is good and reception is successful, for example, a pulse signal corresponding to the waveform of the standard time signal is output to the control circuit 33 as shown in FIG.
In this case, the control circuit 33 considers that the received state of the received standard radio wave is within a normal reference range defined in advance.

  On the other hand, when the reception state is considered to be out of the reference range, the radio wave is weak or there is a lot of noise. When the radio wave is very weak, for example, as shown in FIG. 2C, the pulse signal remains at a low level (L) or a high level (H) for several signals. When there is a lot of noise, for example, as shown in FIG. 2D, the level of the pulse signal changes regardless of the waveform of the received radio wave.

  The Japan Standard Radio JJY is operated under the National Institute of Information and Communications Technology (NICT). The amplitude of the pulse signal that is a modulated wave is 100% at the maximum and 10% at the minimum.

  Next, transmission data (time code) of the standard radio signal will be described.

  FIGS. 3A and 3B are part of the time code of the standard radio signal.

  For example, as shown in FIGS. 3A and 3B, the time code is divided into one minute and one period (one frame), divided into 60 seconds, and 1-bit information is allocated and transmitted every second. ing.

  The information transmitted by the time code is the binary number (BCD (Binary coded decimal notation) positive logic) for the hour, minute, day of the month, January 1st, year (last 2 digits), and day of the week. ) Send as represented. Therefore, sometimes it takes 6 bits to represent the time of the 24-hour JST, 7 bits for the minutes, 10 bits for the day of the week, 8 bits for the year, and 3 bits for the day of the week.

  As for the second signal, the second is the rising edge of the radio wave pulse signal, and 55% (the center of the 10% value and the 100% value) of the rising edge of the pulse is synchronized with the 1 second signal of the standard time.

  The P signal is transmitted 7 times in one frame, and the one corresponding to the minute (0 second) is called the marker M, and the one corresponding to 9 seconds, 19 seconds, 29 seconds, 39 seconds, 49 seconds, It is called position markers P1 to P5. Note that the other position marker P0 normally corresponds to a rise of 59 seconds (in the case of non-leap seconds).

  The P signal continues to appear once in one frame, and when it continues for 59 seconds and 00 seconds, that is, when it continues with the position markers P0 and M, the position where it continues appears as the minute position. That is, the time data such as the minute / hour data are determined in the frame based on the position of the minute part, so the position of the minute part is detected and the time data is taken out.

  However, the format of the standard radio wave frame is not the same every minute. For example, as shown in FIG. 3A, formats other than 15 minutes and 45 minutes every hour, and as shown in FIG. The time format of 15 minutes and 45 minutes per hour is different. The spare bits named SU1 and SU2 and the leap second information named LS1 and LS2 are in a format other than 15 minutes and 45 minutes per hour, as shown in FIG. It appears only in the format of 15 minutes per hour and 45 minutes shown in FIG.

  As described above, the standard time information can be obtained by receiving the standard radio wave including the time signal (time code) and decoding the pulse signal obtained therefrom. The control circuit 33 corrects the measured time based on the obtained standard time signal.

  As described above, in this embodiment, the timepiece has an alarm function and employs a radio wave correction timepiece that corrects the time measured by the internal timepiece. Furthermore, in this embodiment, an eavesdropper detector for detecting an eavesdropper is provided in this watch.

  Next, a specific configuration example of the wiretap detector 2 will be described in detail with reference to FIG.

  FIG. 4 is a block diagram illustrating a specific configuration example of the wiretap detector according to the present embodiment.

  4 has a reception circuit 42, a reception frequency scanning system 43, a signal processing system 44, a microcomputer 45, and a notification unit 46 that constitute the wiretap detection unit 4 shown in FIG. . The wiretap detector 2 shares the sound generator 5 of the clock unit 3 shown in FIG.

  More specifically, the reception circuit 42 includes a high frequency amplifier 421, a mixer 422, an intermediate frequency amplifier 423, a detection unit 424, and a first detector 425.

  The reception frequency scanning system 43 includes a scanning unit 431, a VCO 433, and a switching unit 432.

  Further, the signal processing system 44 includes a band pass filter 441 and a second detector 442.

  Next, each component of the wiretap detector 2 will be described.

  The receiving antenna 41 of the receiving circuit 42 receives the radio signal transmitted from the wiretap 6 and outputs the radio signal to the high frequency amplifier 421 of the receiving circuit 42.

  The high frequency amplifier 421 receives a radio signal received by the receiving antenna 41, amplifies a high frequency signal (for example, about 400 MHz), and outputs the amplified signal to the mixer 422.

  The mixer 422 receives a signal amplified by the high frequency amplifier 421 and a signal having a predetermined frequency oscillated by the VCO 433, multiplies and mixes two signals having different frequencies, and outputs the mixed signal to the intermediate frequency amplifier 423.

  The intermediate frequency amplifier 423 amplifies only the intermediate frequency component (for example, 10.7 MHz) in the signal input from the mixer 422, and outputs the amplified signal to the first detector 425.

  The first detector 425 demodulates the signal input from the intermediate frequency amplifier 423, extracts the audio signal, and outputs the audio signal to the bandpass filter 441 constituting the signal processing system 44.

  The detection unit 424 detects the reception level of the signal in the intermediate frequency amplifier 423 and outputs it to the microcomputer 45.

  The band pass filter 441 extracts a specific frequency component (for example, 1 kHz) from the audio signal input from the first detector 425 of the reception circuit 42 and outputs the specific frequency component to the second detector 442.

  The second detector 442 receives the audio signal from the bandpass filter 441, detects the amplitude of the specific frequency from this audio signal, and outputs it to the microcomputer 45.

  The microcomputer 45 receives the audio signal from the second detector 442, the reception level of the signal from the detection unit 424, and the control signal from the scanning unit 431, and the scanning unit 431 according to these signals and the reception level. Each of the switching unit 432 and the notification unit 46 is controlled. Further, the microcomputer 45 is connected to the control circuit 33 of the timepiece unit 3 shown in FIG. 1, and when the wiretap detection switch is turned on, the signal generator 51 of the sound generation unit 5 is turned on by a control signal from the control circuit 33. Control. Control of the scanning unit 431 and the switching unit 432 performed by the microcomputer 45 will be described later.

  The scan unit 431 is connected to a first current source (configured by the transistor TR3, resistors R5 to R7 and nodes ND4 to ND5 in FIG. 6), and a current supply node (NDI in FIG. 6). A capacitor (C1 in FIG. 6) charged by the current generated by the current source, a switch (transistor TR4 in FIG. 6) for resetting the voltage of the current supply node to a predetermined voltage (for example, ground potential), and current supply A voltage comparison unit (CPN in FIG. 6) that compares the voltage of the node with a predetermined voltage and determines whether or not the voltage of the current supply node has reached the predetermined voltage. Details of the components of the scanning unit 431 will be described later with reference to FIG.

  The scan unit 431 is switched on and off with the first current source, and the second current source (transistor TR5, resistors R8 to R10 and nodes ND7 to ND8 in FIG. To charge the capacitor. The scan unit 431 compares the voltage of the current supply node with the reference voltage in the voltage comparison unit, and when the voltage of the current supply node reaches the reference voltage, the voltage of the capacitor is set to a predetermined voltage (for example, ground potential). Reset to. The scan unit 431 outputs the voltage of the current supply node to the VCO 433 until the capacitor voltage is reset to a predetermined voltage.

  The switching unit 432 includes a second current source (the transistor TR5 in FIG. 6, resistors R8 to R10, and the node ND7) for charging the capacitor (C1 in FIG. 6) connected to the current supply node (NDI in FIG. 6). ~ ND8). The second current source is connected to a switch (transistor TR6 in FIG. 6) that is switched on or off in accordance with a control signal from the microcomputer 45. Details of the components of the switching unit 432 will be described later with reference to FIG.

  When the control signal is input from the microcomputer 45 and the reception level detected by the detection unit 424 is equal to or lower than a predetermined value, the switching unit 432 switches the switch on. If the reception level is above a certain value, the switch is turned off.

  The VCO 433 receives the voltage of the current supply node (NDI in FIG. 6) from the scan unit 431, and the frequency corresponding to the input voltage from the scan unit 431 in order for the bug detector 2 to stably receive the radio signal. And a signal having a predetermined frequency is output to the mixer 422.

  The signal generator 51 of the sound generation unit 5 generates an audio signal having a predetermined frequency (for example, an audible frequency band) at the alarm time, for example, under the control of the microcomputer 45 when the bug detection switch is on. Further, the signal generator 51 generates a sound signal such as an alarm sound or a melody sound by the control circuit 33 of the clock unit 3 (see FIG. 1). Note that the signal generator 51 is controlled only by the control circuit 33 of the timepiece unit 3 when the wiretap detection switch is off.

  The speaker 52 transmits a sound wave signal based on the audio signal input from the signal generator 51.

  The notification unit 46 receives a control signal from the microcomputer 45 and notifies predetermined information. For example, the notification unit 46 notifies information such as the detection result of the bug 6 using a display device (for example, a lamp, a display that displays image information, character information, or the like), a buzzer, or the like.

  Next, the operation of the wiretap detector 2 will be described. In the following description, it is assumed that the eavesdropper detection change-over switch is set to ON and the eavesdropper detector 2 detects the eavesdropper 6.

  The microcomputer 45 of the wiretap detector 2 receives a control signal from the control circuit 33 of the timepiece unit 3 at the time of an alarm, and transmits a sound wave signal (alarm sound) having a specific frequency via the speaker 52. To control. The eavesdropper 6 acquires the sound wave signal from the eavesdropper detector 2 with the microphone 62, modulates the high frequency of the carrier wave with the sound wave signal, and sends it out via the antenna 61.

  The wiretap detector 2 demodulates the radio signal received by the receiving antenna 41 from the radio signal to an audio signal by the receiving circuit 42. The wiretap detector 2 detects the reception level of the radio signal.

  Next, the operation of the receiving circuit 42 will be described.

  The high frequency amplifier 421 amplifies the high frequency signal, and the mixer 422 multiplies the amplified high frequency signal and a signal of a predetermined frequency output from the VCO 433.

  The VCO 433 generates a signal having a predetermined frequency based on the control signal of the scan unit 431.

  Here, an operation until the scanning unit 431 scans under the control of the switching unit 432 and the VCO 433 outputs a signal having a predetermined frequency to the mixer 422 will be described.

  The switching unit 432 switches the switch on or off based on a control signal from the microcomputer 45.

  When the reception level detected by the detection unit 424 is equal to or less than a certain value, the switching unit 432 switches on the switch. When the reception level of the radio signal is equal to or higher than a certain value, the switching unit 432 switches the switch off.

  The scanning unit 431 scans at a low speed or a normal scanning speed according to the control signal of the microcomputer 45 and the switching of the switch of the switching unit 432.

  When the switch of the switching unit 432 is on, the scan unit 431 charges the capacitor with the first and second current sources (normal scan speed). When the switch of the switching unit 432 is off, the scan unit 431 charges the capacitor with only the first current source (low speed scan).

  The scan unit 431 performs scanning until the voltage of the current supply node (not shown) reaches a predetermined voltage, and outputs the voltage of the current supply node to the VCO 433.

  The VCO 433 generates a signal having a predetermined frequency according to the output voltage of the scan unit 431 and outputs the signal to the mixer 422.

  In this way, the VCO 433 outputs a signal having a predetermined frequency to the mixer 422.

  The intermediate frequency amplifier 423 receives the signal of the intermediate frequency component from the signal input from the mixer 422 and multiplied, and outputs the signal to the first detector 425 and the detection unit 424.

  The first detector 425 demodulates the intermediate frequency signal, extracts the audio signal, and outputs it to the bandpass filter 441. The detection unit 424 detects the reception level of the intermediate frequency signal and outputs the detection result to the microcomputer 45.

  Subsequently, the band pass filter 441 extracts a specific frequency component from the audio signal detected by the first detector 425 and outputs the specific frequency component to the second detector 442. Then, the second detector 442 detects the amplitude of the specific frequency included in the audio signal and outputs it to the microcomputer 45.

  The microcomputer 45 determines the presence / absence of the wiretap 6 based on the voltage output from the second detector 442. When the wiretap 6 is detected by this voltage, the microcomputer 45 controls the notification unit 46 so as to notify the detection. When the wiretap 6 is not detected, the microcomputer 45 controls the scanning unit 431 and the switching unit 432 so as to continuously scan.

  As described above, the eavesdropper detector 2 performs scanning while continuously changing the tuning frequency transmitted from the speaker 52. For this reason, the oscillation frequency of the VCO 433 need not be fixed.

  However, in the present embodiment, there is a problem in that scanning is affected if the time width for extracting a specific frequency component from the audio signal by the bandpass filter 441 is not sufficient. This is because a predetermined time is required until the amplitude of the audio signal reaches a certain value.

  Next, problems in the bandpass filter 441 described above will be described.

  FIG. 5 is a diagram for explaining a change in waveform when an audio signal passes through the bandpass filter according to the present embodiment. 5A and 5C show the waveform of the input signal before passing through the band-pass filter 441, and FIGS. 5B and 5D show the input signal of FIGS. 5A and 5C. The waveforms of the output signals after passing through the band pass filter 441 are shown. The passing frequency of the bandpass filter 441 is 1 kHz, and the frequency of the audio signal output from the first detector 425 (see FIG. 4) of the receiving circuit 42 is 1 kHz.

  In the wiretap detector 2, when the frequency of the received radio wave signal is scanned, it is demodulated into an audio signal only during a period in which the scan frequency passes through the oscillation frequency of the wiretap 6. Therefore, the waveform of the audio signal output from the first detector 425 is in a burst shape.

  The radio signal emitted from the wiretapping device 6 is demodulated into a 1 kHz audio signal by the receiving circuit 42, passes through a 1 kHz band-pass filter 441, and from the amplitude of the audio signal, the microcomputer 45 generates a 1 kHz audio signal. Determine the presence or absence of audio components.

  When an input signal having a waveform as shown in FIG. 5A is input, the band pass filter 441 outputs a signal having a waveform as shown in FIG. At this time, the output signal waveform becomes dull. Such a dull waveform becomes more prominent as the frequency selectivity of the bandpass filter 441, that is, the performance of the bandpass filter 441 increases. If the time width of the input signal is sufficient as shown in FIG. 5A, the bandpass filter 441 generates a signal having a constant amplitude (1 kHz in FIG. 5) as shown in FIG. Output. However, in the case of an input signal having a short time width as shown in FIG. 5C, the bandpass filter 441 outputs a signal having a waveform as shown in FIG. 5D, and the amplitude of the signal is a constant value ( The input signal ends before reaching 1 kHz in FIG.

  As described above, when the input time width of the signal input to the band pass filter 441 is not sufficient, the microcomputer 45 cannot obtain the amplitude necessary for the frequency determination. As the speed of scanning the frequency in the constant frequency band increases, the time width of the signal input to the bandpass filter 441 becomes shorter.

  On the contrary, if a sufficient time width of the input signal described above is to be secured, the time required for one scan becomes longer.

  Next, a specific example will be described. As for the intermediate frequency, since the wiretap 6 is a narrow-band transmitter, the intermediate frequency amplifier 423 has an intermediate frequency passband width of ± 20 kHz, and the wiretap detector 2 is often used for wiretap from 139 MHz to 400 MHz. Suppose we have scanned for a frequency of.

Assuming that the 1 kHz band-pass filter 441 reaches the constant value for 50 waveforms of 1 kHz, the time width is 50 ms at 50/1000 = 50 × 10 ⁻³ . In order to pass the pass band ± 20 kHz of the intermediate frequency in 50 ms, 50 × 10 ⁻³ × (400 × 10 ⁶ −139 × 10 ⁶ ) / 40 × 10 ³ = 326.25 s. This means that the eavesdropper detector 2 scans the frequency band from 139 MHz to 400 MHz over 326.25 s, and one scan requires approximately 5.4 minutes.

  The wiretap detector 2 includes a second detector 442, a scanning unit 431, and a switching unit 432 in order to solve the problems in the bandpass filter 441 described above.

  Next, circuit configuration examples of the scanning unit 431 and the switching unit 432 will be described.

  FIG. 6 is a circuit diagram illustrating a configuration example of the scanning unit and the switching unit according to the present embodiment.

  The scan unit 431 includes pnp type transistors TR1 and TR2, resistors R1 to R4, and nodes ND1 to ND3, a voltage comparison unit CPN, a pnp type transistor TR3, resistors R5 to R7, and nodes ND4 and ND5. A first current source configured to generate a current IC3, a capacitor C1, a current supply node NDI, a current supply node NDI is reset to a predetermined voltage, and an npn transistor TR4 operating as a switch and a node ND6 are provided. Have.

  The resistors R1 and R2 of the voltage comparison unit CPN are connected in series between the power supply potential VDD and the ground potential GND.

  The transistor TR1 has a base connected to the node ND1, an emitter connected to the node ND2, and a collector connected to the node ND3. The transistor TR2 has a base connected to the node ND4, an emitter connected to the node ND2, and a collector connected to the ground potential GND.

  Resistor R3 is connected between power supply potential VDD and node ND2, and resistor R4 is connected between ground potential GND and node ND3. The node ND3 is connected to the end signal line ENDL.

  The resistors R5 and R6 are connected in series between the power supply potential VDD and the ground potential GND, and the resistor R7 is connected between the power supply potential VDD and the emitter of the transistor TR3. Capacitor C1 is connected between current supply node NDI and ground potential GND. Further, the current supply node NDI is connected to the VCO 433 by the VCO control signal line VCNTL via the nodes ND6 and ND8.

  The transistor TR3 has a base connected to the node ND5, an emitter connected to the resistor R7, and a collector connected to the node ND4. The transistor TR4 has a base connected to the microcomputer 45 via the reset signal line RSTL, an emitter connected to the ground potential GND, and a collector connected to the node ND6.

  The switching unit 432 includes a pnp transistor TR5, nodes ND7 and ND8, and resistors R8 to R10, and determines whether to supply a second current source that generates the current IC4 and the current of the second current source. It has an npn transistor TR6 that operates as a switch.

  The transistor TR5 has a base connected to the node ND7, an emitter connected to the resistor R8, and a collector connected to the node ND8.

  The resistor R8 is connected between the power supply potential VDD and the emitter of the transistor TR5. The resistors R9 and R10 are connected in series between the power supply potential VDD and the collector of the transistor TR6.

  The transistor TR6 has a base connected to the microcomputer 45 via the switching signal line CNTL, an emitter connected to the ground potential GND, and a collector connected to the resistor R10.

  The VCO control signal line VCNTL has a voltage VCNT of the current supply node NDI, the reset signal line RSTL has a reset signal RST, the switching signal line CNTL has a switching signal CNT, and the end signal line ENDL has an end signal END. Are propagated respectively.

  Next, operations of the scanning unit 431 and the switching unit 432 will be described.

  FIG. 7 is a timing chart for explaining operations of the switching unit and the scanning unit according to the present embodiment. 7A shows the voltage VCNT of the current supply node NDI, FIG. 7B shows the end signal END, FIG. 7C shows the reset signal RST, and FIG. 7D shows the detection unit 424. 7E shows the switching signal CNT, and LEV in FIG. 7D shows a constant value of the reception level.

(First step ST1 of wiretap detector)
At the start of scanning, as shown in FIG. 7C, the microcomputer 45 propagates a high level reset signal RST to the reset signal line RSTL, whereby the transistor TR4 is turned on, and the voltage of the current supply node NDI is set to the ground potential. It is reset to GND and the charge of the capacitor C1 becomes zero.

  Thereafter, as shown in FIG. 7C, the microcomputer 45 propagates the low level reset signal RST to the reset signal line RSTL, so that the transistor TR4 is turned off, and the capacitor C1 is turned on as shown in FIG. 7A. Charging starts.

(Second step ST2 of wiretap detector)
(Normal scan)
The microcomputer 45 monitors the output of the detection unit 424. As shown in FIG. 7D, the reception level output by the detection unit 424 is below a certain value (hereinafter referred to as LEV in the description of FIG. 7). In this case, as shown in FIG. 7E, the high-level switching signal CNT is propagated to the switching signal line CNTL, whereby the transistor TR6 is turned on, and the current IC4 generated by the second current source becomes the current supply node. The voltage is supplied to the capacitor C1 via NDI.

  At this time, the capacitor C1 is charged by the currents IC3 and IC4 generated by the first and second current sources, and the voltage VCNT of the current supply node NDI rises as shown in FIG. 7A.

  The voltage VCNT is propagated to the VCO control signal line VCNTL and output to the VCO 433.

(Low speed scan)
As shown in FIG. 7D, when the reception level output from the detector 424 is equal to or higher than a certain value, the microcomputer 45 sends a low level switching signal to the switching signal line CNTL as shown in FIG. By propagating CNT, the transistor TR6 is switched off, and the current IC4 generated by the second current source is not supplied to the capacitor C1 via the current supply node NDI.

  At this time, the capacitor C1 is charged only by the current IC3 generated by the first current source, and the voltage VCNT rises as shown in FIG. The rise in voltage VCNT at this time rises more slowly than during normal scanning in which capacitor C1 is charged with current IC3 and current IC4.

  The voltage VCNT is propagated to the VCO control signal line VCNTL and output to the VCO 433.

(Normal scan)
As shown in FIG. 7D, since the reception level output from the detection unit 424 is again switched to a predetermined value or less, as shown in FIG. 7E, the microcomputer 45 is again set to the switching signal line CNTL at the high level. The switching signal CNT is propagated, the transistor TR6 is turned on, and the output of the second current source is turned on.

  At this time, the capacitor C1 is charged by the currents IC3 and IC4 generated by the first and second current sources, and the voltage VCNT of the current supply node NDI rises as shown in FIG. 7A.

  The voltage VCNT is propagated to the VCO control signal line VCNTL and output to the VCO 433.

(Third step ST3 of wiretap detector)
The voltage comparison unit CPN compares the voltage of the current supply node NDI with the voltage of the node ND1. When the voltage VCNT of the current supply node NDI reaches the voltage VB1 divided by the resistors R1 and R2 (the voltage of the node ND1), the potential of the node ND3 rises as shown in FIG. The end signal END of the line ENDL is switched to the high level, and the high level end signal END is output to the microcomputer 45.

(Fourth Step ST4 of Wiretap Detector)
As shown in FIG. 7C, the microcomputer 45 propagates the reset signal RST of high level to the reset signal line RSTL again, whereby the voltage of the current supply node NDI is reset to the ground potential GND.

  Thereafter, the first step ST1 to the fourth step ST4 of the bug detector are repeated, and the frequency scan is continuously performed.

  As described above, the wiretap detector 2 according to the present embodiment employs the detection unit 424, the scan unit 431, and the switching unit 432, and when the reception level is equal to or less than a certain value, the switching unit 432 TR6 is switched on, and the capacitor C1 is charged with currents IC3 and IC4 (normal scan). When the reception level is greater than or equal to a certain value, the switching unit 432 switches off the transistor TR6 and charges the capacitor C1 with only a smaller current IC3 than when the reception level is less than or equal to the certain value (low speed scan).

  In other words, when the reception level is equal to or lower than a certain value, the switching unit 432 switches on the second current source, so that the capacitor C1 is charged in a short time and the frequency band in which the wiretap 6 is not transmitting is normally set. Scan faster than usual.

  In this way, the wiretap detector 2 according to the present embodiment secures sufficient time for performing signal processing to determine whether specific information is included in the radio signal, reduces noise, and scans. The speed is increased and the detection time of the wiretap is shortened.

  Further, in the bug detector 2 according to the present embodiment, the scanning unit and the switching unit can be realized with inexpensive electronic components such as a resistor, a capacitor, and a transistor. Furthermore, the receiving circuit 42 shown in FIG. 4 is included in a general high-frequency receiving integrated circuit, and it is not necessary to newly provide a detection unit 424 for detecting the reception level of the radio signal. For this reason, there is an advantage that the circuit configuration is simplified.

  The transistors TR1 to TR3 and TR5 constituting the scan unit 431 and the switching unit 432 according to this embodiment can use npn transistors by devising a circuit configuration. Furthermore, as the transistors TR4 and TR6 constituting the scan unit 431 and the switching unit 432 according to the present embodiment, a pnp type transistor can be used by devising a circuit configuration.

  Next, a specific configuration example of the timepiece unit 3 will be described in detail with reference to FIG.

  FIG. 8 is a block diagram illustrating a specific configuration example of the timepiece unit according to the present embodiment.

  8 includes, for example, a clock receiving unit 31, a clock display unit 32, a control circuit 33, an oscillation circuit 34, a switch group 35, a clock microphone 36, an optical sensor 37, a photoelectric conversion unit 38, and a clock detection. Unit 39, reception state display unit 310, and sound generation unit 5. The clock unit 3 shares the sound detector 5 with the wiretap detector 2 shown in FIG.

  Specifically, the timepiece receiving unit 31 includes a timepiece receiving antenna 311 and a long wave receiving circuit 312.

  The control circuit 33 includes an internal clock 331 including, for example, an hour counter, a minute counter, a second counter, and a buffer (memory) 332.

  Next, each component of the timepiece unit 3 will be described.

  The timepiece receiving unit 31 shown in FIG. 8 is the same as the timepiece receiving unit 31 shown in FIG.

  The clock display unit 32 performs a predetermined display according to a display control signal from the control circuit 33, for example. When the display control signal based on the time being measured is input from the control circuit 33, the clock display unit 32 performs time display according to the display control signal. In addition, the clock display unit 32 has a function (reception status display unit 310 to be described later) that displays a reception status according to the evaluation of the reception status of the standard time signal by the clock reception unit 31 under the control of the control circuit 33. .

  In the clock display unit 32 according to the present embodiment, a liquid crystal (LCD) panel is adopted as an example of a display device. The clock display unit 32 has a drive circuit 322 for driving the liquid crystal panel 321. Hereinafter, the case where the clock display unit 32 is a liquid crystal panel will be described with reference to FIG.

  FIG. 9 is a diagram showing a specific example of the clock display unit according to the present embodiment.

  The liquid crystal panel 321 shown in FIG. 9 includes, for example, an hour / minute display unit DPA1 for displaying the hour / minute, a second display unit DPA2 for displaying the second, a month / day display unit DPA3 for displaying the month / day, and a day of the week display unit DPA4 for displaying the day of the week. , An alarm time display unit DPA5 for displaying the alarm time, and a radio wave reception display unit DPA6 for displaying a plurality of display items of the reception state display of the clock receiving unit 31. The liquid crystal panel 321 can display an image, a character, a symbol, or the like in addition to the display content described above depending on its configuration.

  In the radio-controlled timepiece 1, the clock display unit 32 and the reception status display unit 310 that displays the reception status of the clock reception unit 31 are provided on the same display device, for example, the liquid crystal panel 321.

  In the example of FIG. 9, the hour / minute display portion DPA1 is assigned to an area of the upper half or more of the display area of the liquid crystal panel 321. The display form of the hour / minute display portion DPA1 can display a digital display of the hour and hour larger, and the second display portion DPA2 is arranged in the lower right side portion in the figure of the minute display. In addition, a radio wave reception display unit DPA6 is arranged at the upper left horizontal portion of the hour / minute display unit DPA1 in the drawing. Under the control of the control circuit 33, the radio wave reception display unit DPA6 blinks when receiving the standard radio wave by the timepiece reception unit 31 to notify that the radio wave is being received. In the area below the lower half of the display area of the liquid crystal panel 321, a date display unit DPA3, a day display unit DPA4, and an alarm time display unit DPA5 are arranged in parallel.

  The drive circuit 322 of the timepiece display unit 32 outputs a drive signal to the liquid crystal panel 321 based on the display control signal input from the control circuit 33 and controls it.

  The control circuit 33 is connected to a predetermined power supply potential VDD (for example, power supply voltage), and is connected to the microcomputer 45 shown in FIG. The control circuit 33 receives a pulse signal S11 from the long wave reception circuit 312, a predetermined clock from the oscillation circuit 34, an audio signal from the timepiece microphone 36, and a predetermined signal from the optical sensor 37 and the timepiece detection unit 39. Entered. In response to these input signals and the operation of the switch group 35 by the user, the control circuit 33 synchronizes with the clock of the oscillation circuit 34, and the long wave reception circuit 312, the clock display unit 32, the clock detection unit 39, the reception state. The display 310, the microcomputer 45, and the signal generator 51 of the sound generator 5 are controlled.

  The control circuit 33 outputs a sound signal such as an alarm sound or a melody sound to the signal generator 51 at the alarm time, and a control signal for detecting the wiretapping device is detected by the microcomputer so that the wiretap detector 2 detects the wiretap. Output to 45.

  For example, when a predetermined standard radio wave reception time, a reset switch 351, which will be described later, or the like is operated, the control circuit 33 supplies driving power to the timepiece reception unit 31 to receive a standard radio wave signal, and pulse When the signal S11 is output, the reception state of the standard radio wave signal is evaluated, and the display indicating the reception state according to the evaluation is displayed on the clock display unit 32 or the reception state display unit 310. Based on the standard time signal included in the received standard radio signal, the time received by the internal clock 331 is corrected.

  In the present embodiment, the control circuit 33 displays a 10-stage evaluation value indicating the reception state on the reception state display unit 310 at a set time, for example, approximately every 10 seconds, and displays the reception state every 1 second in the reception state display unit. 310 is displayed.

  In the present embodiment, for example, as shown in FIG. 9, the control circuit 33 has ten steps indicating the reception state on the minute digits (minute display portion DPA12) of the hour / minute display portion DPA1 of the liquid crystal panel 321 of the clock display portion 32. The evaluation value is displayed, and the time digit (hour display unit DPA11) is displayed according to the reception state every second. More specifically, for example, the reception state such as a display “0” indicating that the reception state is good or a display “−” indicating that the reception state is not good is displayed.

  For example, when the control circuit 33 displays a 10-step display of the reception state displayed on the minute digit (minute display unit DPA12), for example, 0 to 3, it indicates that the reception state of the radio wave is not very good. 7 indicates that there is a possibility of reception, and 8-10 indicates that the radio wave reception state is good.

  For example, the display according to the reception state every second displayed on the hour digit (hour display unit DPA11) by the control circuit 33 is performed by sampling the pulse signal S11 at 32 Hz at the time of reception, and 32 high levels per second. Is stored in the buffer 332, the state of the pulse waveform is determined every second, and the reception state is displayed on the basis of the result. To display.

  The internal clock 331 has, for example, an hour counter, a minute counter, a second counter, etc., measures the time, and is controlled by the control circuit 33.

  The buffer 332 stores various data such as various settings such as an alarm time by the user.

  The oscillation circuit 34 includes, for example, a crystal oscillator CRY and capacitors C2 and C3, generates a basic clock having a predetermined frequency, and supplies the basic clock to the control circuit 33.

  The switch group 35 includes, for example, a reset switch 351, a correction switch 352, an up switch 353, a down switch 354, an eavesdropper detection changeover switch 355, and a setting switch 356. The switch group 35 is operated by the user, and a signal corresponding to the operation is output to the control circuit 33. The control circuit 33 performs predetermined processing according to the signal.

  The reset switch 351 is turned on when various states of the control circuit 33 are returned to the initial state. When the reset switch 351 is operated or when a battery (not shown) is set, the control circuit 33 returns the various states to the initial state, forcibly causes the watch receiver 31 to receive the standard radio signal, and receives it. Correct the time based on the condition.

  The correction switch 352 is operated, for example, when setting an alarm time. When the correction switch 352 is operated, the control circuit 33 enters, for example, an alarm time setting mode, corrects the alarm time based on a signal corresponding to the operation of the up switch 353 or the down switch 354, and the correction switch 352 is operated again. If it is, set the corrected alarm time.

  The up switch 353 and the down switch 354 are operated, for example, when the alarm time is set as described above or when various settings are made. The control circuit 33 sets various information based on, for example, signals according to operations of the up switch 353 and the down switch 354.

  An eavesdropper detection changeover switch 355 is operated, for example, when the function of the eavesdropper detector 2 is switched on / off. The control circuit 33 is controlled based on a signal corresponding to the operation of the eavesdropper detection changeover switch 355.

  Specifically, for example, when the eavesdropper detection changeover switch 355 is on, the control circuit 33 outputs a control signal to the microcomputer 45 so that the eavesdropper detector 2 detects the eavesdropper. When the wiretap detection switch 355 is off, the signal generator 51 is controlled so as to emit a normal alarm sound or the like. In addition, installation of the function which switches the bug detector 2 on / off is arbitrary, and installation of a switch etc. is not specifically limited.

  The setting switch 356 has, for example, a plurality of modes such as a reception mode, a display mode, and an alarm notification mode, and is operated when setting various modes. When the setting switch 356 is operated, the control circuit 33 sets a mode corresponding to the operation.

  The timepiece microphone 36 converts sound waves into electrical signals and outputs them to the control circuit 33.

  The optical sensor 37 is, for example, a CdS optical sensor, detects light, and outputs a detection signal to the control circuit 33.

  For example, the photoelectric conversion unit 38 outputs electric energy to a secondary power source (not shown) to charge the secondary power source.

  The clock detection unit 39 outputs a detection signal corresponding to the voltage of the electrical energy output from the photoelectric conversion unit 38 to the control circuit 33, for example.

  The reception state display unit 310 displays the reception state of the standard time signal by the timepiece reception unit 31 evaluated by the control circuit 33.

  The sound generation unit 5 is shared with the main clock unit 3 and the bug detector 2 (see, for example, FIG. 1). The signal generator 51 generates an audio signal including an alarm sound by the control circuit 33 regardless of whether the wiretap detection switch 355 is turned on or off. Further, as described above, when the bug detector detection switch 355 is on, an audio signal having a predetermined frequency (for example, an audible frequency band) is generated under control of the microcomputer 45, for example, at an alarm time.

  FIG. 10 is a diagram illustrating an example of the appearance of the radio-controlled timepiece according to the present embodiment.

  As shown in FIG. 10, the main body 100 of the radio-controlled timepiece 1 is provided with a switch group 35 at the lower part of the main body 100, for example. Specifically, an up switch 353, a down switch 354, and a (mode) setting switch 356 are provided side by side below the main body 100. For example, switches such as a reset switch 351, a correction switch 352, and an eavesdropper detection changeover switch 355, and a speaker 52 are provided on the back surface of the main body 100 not shown.

  For example, a display area 110 is provided at the center of the main body 100. In this display area 110, for example, a clock display unit 32, a reception state display unit 310 that displays a reception state, and a notification unit 46 of the bug detector 2 are provided.

  In the present embodiment, the clock display unit 32 and the reception status display unit 310 are provided on the liquid crystal panel 321, but the notification unit 46 is provided on the same display device (for example, the liquid crystal panel 321) as these display units. The display method, display content, display position, and the like are not limited to those of the present embodiment.

  Next, the operation of the radio-controlled timepiece 1 will be described using a flowchart with reference to FIG.

  FIG. 11 is a flowchart for explaining the operation of the radio-controlled timepiece according to this embodiment.

(First step S1)
In the first step S1, the user sets an alarm time.

  Specifically, the user operates the switch group 35 of the timepiece unit 3, for example, the correction switch 352, the up switch 353, the down switch 354, the setting switch 356, etc., and sets the alarm time such as hour information and minute information. At this time, it is assumed that the eavesdropper detection change-over switch 355 is turned on. A signal corresponding to the operation of the switch group 35 by the user is output to the control circuit 33, and the setting by the user is stored in the buffer 332 of the clock unit 3 and reflected in the alarm time display unit DPA5 of the liquid crystal panel 321.

(Second step S2)
In the second step S2, the control circuit 33 corrects the time of the internal clock 331.

  Specifically, the clock receiver 31 of the clock unit 3 receives a standard radio signal including a standard time signal from the standard radio broadcast station 7. Then, the clock receiver 31 performs predetermined signal processing such as detection on the standard radio wave signal, and outputs time information including hour information, minute information, second information and the like to the control circuit 33 as a pulse signal S11.

  The control circuit 33 receives the pulse signal S11 and corrects the time counted by the internal clock 331 based on the time information. In addition, the control circuit 33 performs 10-level evaluation indicating the reception state.

(Third step S3)
In the third step S3, the control circuit 33 corrects the display time and the like.

  Specifically, the control circuit 33 corrects the time information and the like displayed on the clock display unit 32 based on the time information timed by the internal clock 331. Further, the control circuit 33 displays a 10-level evaluation value indicating the reception state on the reception state display unit 310 at a set time, for example, approximately every 10 seconds, and displays the reception state on the reception state display unit 310 every second. Let

(Fourth step S4)
The fourth step S4 relates to an operation performed by the control circuit 33 at the alarm time.

  Specifically, when the time measured by the internal clock 331 reaches a preset alarm time (in the case of YES), the control circuit 33 sends a control signal for detecting the eavesdropper to the micro of the eavesdropper detector 2. Output to the computer 45.

  When the alarm time has not been reached (in the case of NO), the control circuit 33 performs the process of the sixth step S6.

(5th step S5)
In the fifth step S5, the wiretap detector 2 detects the wiretap 6.

  Specifically, the microcomputer 45 of the wiretap detector 2 receives the control signal from the control circuit 33 of the timepiece unit 3 and controls the signal generator 51 of the sound generation unit 5 so as to transmit a sound wave signal having a predetermined frequency. .

  The wiretap detector 2 performs the first step ST1 to the fourth step ST4 of the wiretap detector described above to detect the wiretap 6, and notifies the notification unit 46 of the detection result.

(6th step S6)
The sixth step S6 relates to resetting of the alarm time by the user.

  Specifically, when the user resets the alarm time (in the case of YES), the radio-controlled timepiece 1 returns to the process of the first step S1, for example. When the user does not reset the alarm time (in the case of NO), the radio-controlled timepiece 1 returns to the process of the second step S2, for example.

  As described above, the radio-controlled timepiece according to the present embodiment has a bug detector and an alarm function for detecting a bug, and the bug detector is connected to the bug detector while emitting a specific sound at the alarm time. Perform detection.

  For this reason, in this embodiment, a user can automatically detect a bug, without operating the bug detector.

  Moreover, in this embodiment, since an eavesdropper is detected in conjunction with the alarm function, the presence of the eavesdropper can be constantly monitored and the eavesdropper can be detected periodically.

  Furthermore, in this embodiment, since the radio-controlled timepiece is provided with a wiretap detection function, the wiretap can be detected without a sense of incongruity in daily life. In addition, such a radio-controlled timepiece with an eavesdropper detection function has an advantage that it can be easily purchased by everyone.

  Note that the present invention is not limited to the present embodiment, and various suitable modifications can be made. For example, in the present embodiment, a radio wave correction timepiece is adopted as a timepiece as an example, but the configuration or the like is not particularly limited as long as the timepiece functions as a sound generator and an alarm. In the wiretap detector according to the present embodiment, the sounding unit is a wiretap detector that emits a specific sound and determines whether the received sound is a specific sound generated by itself and detects the wiretap. The configuration is not particularly limited as long as it can be shared with the sound generation unit included in the.

FIG. 3 is a block diagram illustrating a main part of each component in one embodiment of the radio-controlled timepiece according to the present embodiment. It is a figure which shows a specific example of the standard time signal contained in the standard radio signal received with the radio correction timepiece shown in FIG. It is a figure which shows a part of time code (time code) of a standard radio signal. It is a block diagram which shows one specific structural example of the wiretap detector which concerns on this embodiment. It is a figure for demonstrating the change of a waveform when an audio | voice signal passes the band pass filter which concerns on this embodiment. It is a circuit diagram which shows one structural example of the scanning part which concerns on this embodiment, and a switching part. It is a timing chart for demonstrating operation | movement of the switching part which concerns on this embodiment, and a scanning part. It is a block diagram which shows one specific structural example of the timepiece part which concerns on this embodiment. It is a figure which shows one specific example of the timepiece display part which concerns on this embodiment. It is a figure which shows an example of the external appearance of the radio wave correction timepiece concerning this embodiment. It is a flowchart for demonstrating operation | movement of the electromagnetic wave correction timepiece which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Radio correction clock, 2 ... Wiretap detector, 3 ... Clock part, 31 ... Clock receiving part, 32 ... Clock display part, 33 ... Control circuit, 34 ... Oscillation circuit, 35 ... Switch group, 36 ... Clock Microphone, 37 ... optical sensor, 38 ... photoelectric conversion unit, 39 ... clock detection unit, 310 ... reception status display unit, 311 ... clock reception antenna, 312 ... long wave reception circuit, 321 ... liquid crystal panel, 322 ... drive circuit, 331 ... Internal clock, 332 ... Buffer (memory), 351 ... Reset switch, 352 ... Correction switch, 353 ... Up switch, 354 ... Down switch, 355 ... Wiretap detection switch, 356 ... Setting switch, 4 ... Wiretap detection , 41 ... receiving antenna, 42 ... receiving circuit, 43 ... reception frequency scanning system, 44 ... signal processing system, 45 ... microcomputer, 46 ... notification part 421 ... High frequency amplifier, 422 ... Mixer, 423 ... Intermediate frequency amplifier, 424 ... Detection unit, 425 ... First detector, 431 ... Scanning unit, 432 ... Switching unit, 433 ... VCO, 441 ... Band pass filter, 442 2nd detector, 5 ... sound generator, 51 ... signal generator, 52 ... speaker, 6 ... wiretap, 61 ... (wiretap) antenna, 62 ... (wiretap) microphone, 7 ... standard radio broadcast Station: 100 (main body of radio-controlled clock) 110: Display area, C1 to C3: Capacitor, CNT ... Signal, CNTL ... Signal line, CPN ... Voltage comparator, CRY ... Crystal oscillator, DPA1 ... Hour / minute display , DPA2 ... second display part, DPA3 ... month and day display part, DPA4 ... day of week display part, DPA5 ... alarm time display part, DPA6 ... radio wave reception display part, DPA11 ... hour display part, D A12: minute display section, END: end signal, ENDL: end signal line, GND: ground potential, IC3: current, IC4 ... current, JJY: Japan standard radio wave, M ... marker, ND1 to ND10 ... node, NDI ... current supply Node, P0, P1 ... Position marker, R1-R10 ... Resistance, RST ... Reset signal, RSTL ... Reset signal line, S11 ... Pulse signal, TR1-TR6 ... Transistor, VCNT ... Voltage, VCNTL ... VCO control signal line, VDD ... Power supply potential.

Claims (6)

An eavesdropper detection unit that emits a specific sound and determines whether or not the received sound is a specific sound emitted by itself, and detects the eavesdropper;
A clock including a sound generation unit for emitting a sound including at least the specific sound,
The wiretap detector is
Wiretap detector that shares the sound generator of the above clock. The above watch
Has a function to sound at the set time,
The wiretap detector is
The wiretap detector according to claim 1, wherein the wiretap detector detects the wiretap using a specific sound generated by the sound generator of the clock at a set time. The wiretap detector is
The wiretap detector according to claim 1, further comprising a notification unit for notifying a detection result of the wiretap. The wiretap detector is
A detection unit for detecting the reception level of the radio signal;
A scanning unit that scans the frequency of the radio signal;
A switching unit for switching the scanning speed of the scanning unit,
The switching unit is
The wiretap detector according to any one of claims 1 to 3, wherein the scanning speed of the scanning unit is switched according to the reception level. An eavesdropper detection unit that emits a specific sound and determines whether or not the received sound is a specific sound emitted by itself, and detects the eavesdropper;
A sound generation unit for emitting a sound including the specific sound;
And a function to sound at the set time,
The wiretap detector is
A clock that shares the above sound generator. It has a clock receiver that receives radio signals including standard time signals,
The watch receiver is
The timepiece according to claim 5, wherein the time signal of the internal timepiece is corrected by receiving the radio wave signal.

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