JP2008251878A - Thin film mim capacitor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a manufacturing process without increasing element size, for shorter manufacturing period and improved yield. <P>SOLUTION: An SiO<SB>2</SB>film 12 of an Si substrate 10 is worked to form an island-like protruding part 14. Then, a lower electrode film 16, a dielectric film 18, and an upper electrode film 20 are sequentially film-formed by sputtering. An electrode film and a dielectric film on the SiO<SB>2</SB>film 12 are removed by CMP. After polishing, cleaning and annealing processes are applied. Since the height of the SiO<SB>2</SB>protruding part 14 agrees with the total thickness of the dielectric film 18 and the upper electrode film 20, the lower electrode film 16 is exposed from the SiO<SB>2</SB>protruding part 14 by a CMP process. Drawing for connection to the outside of the lower electrode film 16 is made from that portion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film MIM (Metal-Insulator-Metal) capacitor and a method for manufacturing the same, and more particularly to an improvement in the manufacturing process.

  The thin film MIM capacitor is formed by repeating film formation and processing using semiconductor technology and vacuum technology. FIG. 5 shows the basic manufacturing process. A lower electrode layer 102, a dielectric layer 104, and an upper electrode layer 106 are sequentially stacked on the main surface of the Si substrate 100 in FIG. (See FIG. 5B). Next, an upper electrode 106A (see FIG. 5C), a dielectric film 104A (see FIG. 5D), and a lower electrode 102A (see FIG. 5E) are sequentially formed.

Examples of the electrode material include metal materials such as Pt and Au, and oxide materials such as Ir oxide and Ru oxide. Examples of the dielectric material include BST ((Ba, Sr) TiO ₃ ), BT (BaTiO ₃ ), and the like, and are formed by a sputtering method, a sol-gel method, or the like. 5C is performed by dry etching or wet etching using a photolithography technique to form a resist mask. In this way, the thin film MIM capacitor is formed by repeating the film formation and processing.

On the other hand, a capacitor manufacturing method has been proposed in which the MIM multilayer film is processed by CMP (Chemical Mechanical Polishing) to simplify the process (see Patent Document 1 below). . FIG. 6 shows the cross-sectional structure, in which the dielectric layer 114 is patterned and etched on the workpiece 112 to form a stepped shape. Then, trenches defining first patterns 116 for a plurality of conductive lines and second patterns 118 for MIM capacitors are formed. Then, the second conductive layer 134, the first dielectric layer 136, and the third conductive layer 138 are sequentially stacked. Thereafter, CMP is performed on the main surface to remove the excessive material layer. By this planarization process, the MIM capacitor 142 is formed by the third conductive layer 138, the first dielectric layer 136, and the second conductive layer 134.
Special table 2006-500772 gazette

  However, in the background art of FIG. 5 described above, it is necessary to repeat film formation and processing using a photolithography technique, and there is a problem that the number of steps is large and the element formation process takes time. In addition, since the number of processes is large, the number of times of handling is increased, and there are problems that the surface of the substrate is scratched / debris, chipped element patterns are increased, and the yield is lowered. Furthermore, as the number of steps increases, the number of necessary masks also increases, which increases costs.

  On the other hand, in the method using the CMP technique as in the background art of FIG. 6, effects such as a reduction in the number of processes can be expected. However, when the MIM thin film capacitor is formed by forming a step shape in the insulating film on the substrate, the element size becomes large (see ΔA in FIG. 6). Further, from the viewpoint of electrical connection, it is necessary to make the thickness of the lower electrode thicker than the conventionally required thickness, and increasing the thickness of the lower electrode causes problems such as an increase in process time and cost.

  On the other hand, in electronic devices, there is a strong demand for miniaturization, lightening, and high performance of electronic components due to the miniaturization, and capacitor devices are required to have high capacities as well as thin films. Ingenuity from such a viewpoint is also necessary.

  The present invention focuses on the above points, and its purpose is to simplify the manufacturing process without increasing the element size. Another object is to shorten the manufacturing time and improve the yield.

  In order to achieve the above object, the present invention provides a method of manufacturing a thin film MIM capacitor in which a thin film dielectric and electrodes are alternately stacked on a substrate to form a capacitor, wherein the dielectric and the electrode are formed on the substrate. A step of forming at least one convex portion having a height in consideration of the laminated film thickness, a step of alternately laminating the dielectric and electrode thin films on the substrate on which the convex portion is formed, a substrate after the step And a step of exposing the electrode on the convex portion by subjecting the main surface to a CMP process.

  One of the main forms is that when the dielectric thin film is formed in a plurality of layers, a plurality of the convex portions are formed at different heights, and at least the electrodes other than the surface are any of the convex portions. It is exposed from the above. One of the other forms is characterized in that a convex portion exposing the lower electrode and a connecting portion for drawing out the upper electrode whose current direction is opposite to that of the lower electrode are arranged on the substrate adjacent to each other. To do.

  The thin film MIM capacitor of the present invention is manufactured by any one of the methods described above. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

  According to the present invention, a thin film MIM capacitor can be easily manufactured by forming a convex portion of a predetermined height on a substrate and performing CMP processing, thereby reducing the number of processing processes and reducing process time. In addition, the yield can be improved. Further, since the electrodes are drawn from the convex portions, the element size can be limited if the capacitance is the same. Further, by providing a plurality of convex portions having different heights, a desired electrode can be exposed, and the present invention can be applied to a thin film multilayer capacitor in which a plurality of layers of electrodes and dielectrics are alternately laminated. In addition, the magnetic field generated around the electrode or the connection part is offset by arranging the convex part that exposes the lower electrode and the connection part that draws out the upper electrode whose current direction is opposite to that of the lower electrode. Thus, ESL can be reduced.

  Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

  First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 shows a main manufacturing process and a cross-sectional structure of the multilayer MIM capacitor of this example. The manufacturing method of the present embodiment is roughly divided into a substrate processing process and a film formation / CMP removal process.

(1) Substrate processing process A Si substrate 10 on which a thermally oxidized SiO ₂ film 12 is formed is prepared (see FIG. 1A). A resist mask is patterned on the SiO ₂ film by photolithography, the SiO ₂ film 12 is processed by RIE (Reactive Ion Etching), and then the resist is removed by O ₂ ashing. As a result, a substrate having island-shaped convex portions 14 made of SiO ₂ as shown in FIG. Here, the SiO ₂ convex portion 14 is set to a height of, for example, 400 nm. This value is matched with, for example, the thickness of the upper electrode and dielectric described later. Of course, it may be 400 nm or more. In other words, when viewed in the cross section of FIG. 1B, the height of the SiO ₂ convex portion 14 is set lower than the outer peripheral portion 12a of the SiO ₂ film 12 by the thickness of the lower electrode.

(2) Film Formation / CMP Removal Process Subsequently, the lower electrode film 16, the dielectric film 18, and the upper electrode film 20 are sequentially formed on the above-described processed substrate (see FIG. 1C). The electrode material is, for example, Pt (thickness: 250 nm), and the dielectric material is, for example, BST (thickness: 150 nm). Next, the electrode film and the dielectric film on the SiO ₂ 0 film 12 are removed by CMP. As the CMP, for example, a “GRIND-XCMP apparatus” is used, and an alumina slurry is dropped at 90 ml / min, and polishing is performed at a table speed, a head speed, and a pressing pressure of 80 rpm, 80 rpm, and 0.02 MPa, respectively. At this time, the recess may be protected with a resist or an insulating film so as not to remove the film other than the protrusion of the SiO ₂ film 12. After polishing, cleaning and annealing are performed. The annealing process is performed in an O ₂ atmosphere at 600 ° C. for about 30 minutes, for example. Thereby, a thin film MIM capacitor as shown in FIG. 1D is obtained.

As described above, the height of the SiO ₂ convex portion 14 is set lower than the outer peripheral portion 12 a of the SiO ₂ film 12 by the thickness of the lower electrode film 16. For this reason, when processing by the CMP process is performed so that the outer peripheral portion 12 a of the SiO ₂ film 12 is exposed, the lower electrode film 16 is exposed on the SiO ₂ convex portion 14. Therefore, the lower electrode film 16 can be pulled out from this portion for external connection. Note that the upper electrode film 20 is exposed at a portion where the SiO ₂ convex portion 14 is not formed.

Next, the element sizes of the multilayer MIM capacitor of this example obtained as described above and the multilayer MIM capacitor of the background art of FIG. 6 described above will be compared. For example, it is assumed that a multilayer MIM capacitor having an upper and lower electrode thickness of 400 nm, a dielectric thickness of 200 nm, an element size of 100 μm ² , and a capacitance of 20 nF / mm ² per unit area is manufactured. Using this process, as shown in FIG. 1D, when the length of one side of the capacitor element is 10 μm and the length of one side of one SiO ₂ convex portion 14 is 0.1 μm, the capacitance area is 99. It is possible to manufacture a capacitor having a capacity of 999 μm ² and a total capacity of about ² pF.

On the other hand, in the method of Patent Document 1, as shown in FIG. 6, when the length of one side of the element size is 10 μm, the distance between the end portions indicated by ΔA is the first dielectric layer 136 and the second conductive layer. Since the thickness is the sum of 134, the area as a capacitor is reduced accordingly. Therefore, the length of one side of the capacitance area is 8.8 μm, the capacitance area is 77.44 μm ² , and the capacitance is about 1.5 pF. Comparing the two, if the same element size is used, a capacitor having a larger capacity than that of the prior art can be obtained in this embodiment. Conversely, if the same capacity is used, the element size can be limited. it can.

Next, measurement examples of the electrical characteristics of this example will be described. The element size of the sample was 0.16 mm ² , CV (capacitance voltage) characteristics were measured using an LCR meter, and a picoammeter was used for IV (current voltage) characteristics evaluation. As a result, the capacitance and tan δ were 22.3 nF / mm ² and 0.0128, respectively. On the other hand, in the case of the thin film MIM capacitor manufactured by the prior art shown in FIG. 5, the capacitance and tan δ are 21.6 nF / mm ² and 0.0129, respectively, with the same element size, which are almost equal. On the other hand, the measurement result of the IV characteristic of the sample of the present example is as shown in FIG. 4, and a result almost equal to that of the prior art is obtained. From these results, it was confirmed that according to this example, the thin film MIM capacitor can be easily manufactured by CMP, and characteristics equivalent to those of the conventional technique manufactured by the photolithography technique can be obtained.

As described above, according to this embodiment, there are the following effects.
(1) Since the SiO ₂ insulating film on the upper layer of the Si substrate is processed, and then the lower electrode / dielectric / upper electrode is formed, and CMP is performed to produce a thin film MIM capacitor. As a result, the manufacturing process is simplified, and shortening of manufacturing time, improvement of yield, and cost reduction can be expected.
(2) Since an island-like convex part is formed on the SiO ₂ insulating film on the upper layer of the Si substrate, and the lower electrode is drawn out from this convex part, if the capacitance area is the same, it is compared with the prior art. Thus, the element size can be reduced.
(3) It is not necessary to form the lower electrode thick, and from this point, manufacturing time and cost can be reduced.

Next, Example 2 will be described with reference to FIG. In addition, the same code | symbol is used for the component which is the same as that of the Example mentioned above, or respond | corresponds. In the embodiment shown in FIG. 1, there are two electrode layers and one dielectric layer. However, this embodiment is an example in which a plurality of layers are further laminated, and is a laminate comprising three electrodes and two dielectric layers. It is an example of a capacitor (substrate / insulator / lower electrode / lower dielectric / intermediate electrode / upper dielectric / upper electrode). In this case, SiO ₂ convex portions having different heights for extracting the lower electrode and the intermediate electrode may be formed.

The electrode thickness is 400 nm and the dielectric thickness is 200 nm. A Si substrate 10 on which the SiO ₂ film 12 as shown in FIG. 1A is formed is prepared, and at least two SiO ₂ convex portions 50 and 52 having different heights are formed by RIE processing (FIG. 2). (See (A)). In the figure, the step Ha needs to be at least 1600 nm which is the sum of the electrode and the dielectric. The level difference Ha may be set to 1600 + α nm, and α is a margin for over CMP. In this example, α = 200 nm.

A lower electrode is exposed on the surface immediately above the SiO ₂ convex portion 50 in a later CMP process. For this reason, the height Hb of the SiO ₂ convex portion 50 is set to 1400 nm (= upper electrode thickness + upper dielectric thickness + intermediate electrode thickness + lower dielectric thickness + α). Similarly, the intermediate electrode is exposed on the surface immediately above the SiO ₂ convex portion 52 in a later CMP process. For this reason, the height Hc of the SiO ₂ convex portion 52 is set to 800 nm (= upper electrode thickness + upper dielectric thickness + α).

On the SiO ₂ film 12 on which the SiO ₂ convex portions 50 and 52 as described above are formed, a lower electrode film 16, a lower dielectric film 18L, an intermediate electrode film 20M, an upper dielectric film 22, and an upper electrode film 24 are formed. The layers are sequentially formed (see FIG. 2B). Then, when removing excess electrode layer and the dielectric layer by CMP, as shown in FIG. 2 (C), the lower electrode film 16 is exposed on the SiO ₂ protrusions 50, the intermediate electrode on the SiO ₂ peaks 52 The film 20M is exposed (see FIG. 2C).

  As described above, according to the present embodiment, by controlling the height of the convex portion, even in a multilayer capacitor in which a plurality of electrodes and dielectrics are alternately laminated, the lower electrode and the intermediate electrode are satisfactorily surfaced. Can be exposed and pulled out.

Next, Example 3 will be described with reference to FIG. In this example, a plurality of SiO ₂ convex portions are provided. FIG. 3A shows a plan view of the element. In the rectangular region of the SiO ₂ film 12, a plurality of SiO ₂ convex portions 50 whose height is set to a predetermined value, and connection portions 54. However, they are arranged adjacent to each other so that the magnetic field generated around the electrode or the connection portion is canceled out. The lower electrode film 16 is exposed at the SiO ₂ convex portion 50, and the upper electrode film 20 is exposed at the connection portion 54. For example, if the current direction in the lower electrode film 16 is “+”, the current direction in the upper electrode film 20 is “−”. The current extraction of “+” and “−” is reversed, and the direction of current flow is reversed. For this reason, the magnetic field generated around the electrode or the connection portion is canceled, and the inductance cancels out to reduce the ESL. Thus, according to this example, a thin film capacitor having a multi-terminal structure characterized by low ESL can also be manufactured.

In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) The materials, shapes, and dimensions shown in the above embodiments are merely examples, and can be appropriately changed so as to achieve the same effect.
(2) In the above embodiment, the lower electrode and the intermediate electrode are exposed on the convex portion formed on the substrate. However, all the electrodes may be exposed on the convex portion. Moreover, a convex part may be made to continue with an outer peripheral part, and a convex part from which height differs may be made to continue. An example is shown in FIG. The convex portion 60 is continuous with the outer peripheral portion 61. The convex portion 62 includes two exposed surfaces 64 and 66 having different heights.
(3) The corners of the convex portions may be rounded so that the MIM structure has an acute angle and electric field concentration does not occur. Moreover, you may make it prevent the pressure | voltage resistant fall in a convex part side wall by setting it as the shape which gave the convex part the taper.

  The present invention is suitable for thin film MIM capacitors, laminated thin film MIM capacitors, low ESL thin film MIM capacitors, and the like.

It is a figure which shows the main processes and laminated structure of Example 1 of this invention. It is a figure which shows the main processes and laminated structure of Example 2 of this invention. (A) is a top view of Example 3 of this invention, (B) is a figure which shows the example of another convex part. 4 is a graph showing an example of measurement of IV characteristics of the sample of Example 1. It is a main process figure of the conventional manufacturing method of the thin film MIM capacitor using semiconductor technology and vacuum technology. It is a figure which shows the laminated structure of the thin film MIM capacitor produced by the conventional manufacturing method using CMP.

Explanation of symbols

10: Si substrate 12: SiO ₂ film 12a: Peripheral part 14: Convex part 16: Lower electrode film 18: Dielectric film 18L: Lower dielectric film 20: Upper electrode film 20M: Intermediate electrode film 22: Upper dielectric film 24 : Upper electrode film 50, 52: convex part 54: connection part 60, 62: convex part 61: outer peripheral part 64, 66: exposed surface 100: Si substrate 102: lower electrode layer 102A: lower electrode 104: dielectric layer 104A: Dielectric film 106: Upper electrode layer 106A: Upper electrode 112: Work piece 114: Dielectric layer 116: Pattern 118: Pattern 134: Conductive layer 136: Dielectric layer 138: Conductive layer 142: Capacitor

Claims (4)

A method of manufacturing a thin film MIM capacitor in which a thin film dielectric and electrodes are alternately stacked on a substrate to form a capacitor,
Forming at least one convex portion having a height in consideration of the thickness of the dielectric and the electrode on the substrate;
A step of alternately laminating the dielectric and electrode thin films on the substrate on which the convex portions are formed;
A step of exposing the electrode on the convex portion by subjecting the substrate main surface after this step to CMP processing;
A method of manufacturing a thin film MIM capacitor, comprising:   In the case where a plurality of dielectric thin films are formed, a plurality of the convex portions are formed at different heights, and at least the electrodes other than the surface are exposed from any of the convex portions. The method of manufacturing a thin film MIM capacitor according to claim 1.   3. The convex portion for exposing the lower electrode and the connecting portion for drawing out the upper electrode having a current direction opposite to that of the lower electrode are arranged adjacent to each other on the substrate. Manufacturing method of thin film MIM capacitor.   A thin film MIM capacitor manufactured by the method according to claim 1.

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