JP2008251732A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that allows impurities to be introduced into a desired part of the bottom face of a step even if a large step is formed on the device formation face of a semiconductor substrate, and its manufacturing method. <P>SOLUTION: The semiconductor device is configured as follows. Two MOS transistors having the same polarities share one impurity diffusion layer in their source-drain regions. The semiconductor device has a part where polysilicon gates of the two MOS transistors are adjacent to each other. Heights of polysilicon gates 11 of the two MOS transistors are ≥150 nm. A interval between the polysilicon gates adjacent to each other is ≤87 nm. The impurity diffusion layer 151 shared by the two MOS transistors is configured so that an impurity concentration at the surface of the diffusion layer is the highest in the diffusion layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of an impurity diffusion layer formed in a stepped region on a semiconductor substrate and an impurity introduction method, for example, a complementary semiconductor integrated circuit device having an insulated gate structure. (CMOS LSI).

  When manufacturing semiconductor devices such as CMOS LSIs, as the generation of CMOS transistors progresses, the result of improving the degree of integration of elements, or as a result of adopting a special element structure for the purpose of improving the characteristics, the semiconductor substrate In some cases, a large step (height difference) may occur on the element formation surface. When such a large level difference occurs, when impurities are introduced into the element formation surface, ion implantation that has been widely performed conventionally has strong anisotropy, and therefore, it may not be possible to introduce impurities into the target site.

In Patent Document 1, when manufacturing a CMOS image sensor, a trench is formed in a semiconductor substrate, a high-concentration impurity ion region is formed on a side surface of the trench, and an insulating film is provided in the trench to form an element isolation region. Thus, it is disclosed that the interface between the active region and the field region is not damaged by ion implantation.
JP 2005-197682 A

  The present invention has been made to solve the above-described conventional problems, and a semiconductor device capable of introducing an impurity into a desired portion on the bottom surface of a stepped portion even when a large step occurs on the element forming surface of the semiconductor substrate, and its manufacture It aims to provide a method.

  According to a first aspect of the semiconductor device of the present invention, two MOS transistors having the same polarity share one impurity diffusion layer of each source / drain region, and the polysilicon gates of the two MOS transistors are adjacent to each other. In a semiconductor device having a matching portion, the height of each polysilicon gate of the two MOS transistors is 150 nm or more, and the distance between adjacent polysilicon gates is 87 nm or less, and the impurities shared by the two MOS transistors The diffusion layer is characterized in that the impurity concentration on the surface of the diffusion layer is the highest inside the diffusion layer.

  According to a second aspect of the semiconductor device of the present invention, in the semiconductor device having a MOS transistor, the channel region of the MOS transistor has both ends in the channel width direction adjacent to the element isolation region of the trench structure, and impurities are generated by solid phase diffusion. The impurity concentration of the channel region is substantially equal in the central portion and the peripheral portion in the channel width direction.

  According to a first aspect of the method of manufacturing a semiconductor device of the present invention, a P well in an NMOS transistor formation region, an N well in a PMOS transistor formation region, and a depth formed to separate the P well and the N well. An isolation region having a trench structure with a width of 300 nm or less and a width of 100 nm or less, an N diffusion layer for the drain / source region of the NMOS transistor formed on the surface of the P well, and the PMOS formed on the surface of the N well A method of manufacturing a semiconductor device having a P diffusion layer for a drain / source region of a transistor, wherein a pattern for an etching mask is formed on the semiconductor substrate, and a depth of 300 nm or less and a width of 100 nm are formed on a surface layer portion of the semiconductor substrate A step of forming an element isolation region having a trench structure for well isolation described below, and depositing a first oxide film doped with a P-type impurity on the entire surface of the semiconductor substrate, A patterning process for leaving the first oxide film on the P well region, a second oxide film doped with an N-type impurity is deposited on the entire surface, and the second oxide film is left on the N well region. A patterning process, and an oxide film for suppressing diffusion of impurities to promote diffusion to the semiconductor substrate is deposited on the entire surface of the semiconductor substrate, followed by chemical mechanical polishing. Removing the oxide film on the semiconductor substrate and leaving the oxide film in the trench of the element isolation region; peeling the pattern for the etching mask; and ion implantation for forming the P well region And an ion implantation step for forming the N well region, and an impurity is diffused by annealing, and the periphery of the element isolation region is formed in each well. Impurity concentration than the other parts of the same depth is characterized by comprising a step of forming a high region.

  According to a second aspect of the method for manufacturing a semiconductor device of the present invention, there is provided a gate electrode of a MOS transistor, an impurity diffusion layer for source / drain regions, a gate sidewall, and a surface of the semiconductor substrate below the gate sidewall. A method of manufacturing a semiconductor device having a MOS transistor having an epitaxially grown diffusion layer epitaxially grown to a higher position, wherein after forming a gate electrode, an impurity diffusion layer for source / drain regions, a gate sidewall, the gate Etching the surface of the impurity diffusion layer using the sidewall as a protective film, and epitaxially growing SiGe from the surface of the semiconductor substrate below the gate sidewall to form an epitaxial growth diffusion layer at a position higher than the original semiconductor substrate surface And introducing impurities by solid phase diffusion below the gate sidewalls; Characterized by comprising.

  ADVANTAGE OF THE INVENTION According to this invention, even when a big level | step difference arises in the element formation surface of a semiconductor substrate, the semiconductor device which can introduce an impurity into the desired site | part of a step part bottom face, and its manufacturing method can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
In the first embodiment, a manufacturing process of a static semiconductor memory (SRAM) is taken as an example.

  In SRAMs, transistors with the same polarity may be arranged very close to each other as the elements are highly integrated. For example, in a 6-transistor SRAM cell, the gates of the storage node driving NMOS transistor and the transfer gate NMOS transistor are arranged very close to each other. The gate height of these transistors cannot be lowered to prevent ion penetration in an ion implantation (I / I) process. Therefore, for example, when forming a lightly doped drain (LDD) transistor, a low concentration shallow extension region is formed in the narrow substrate surface layer (shared drain region) between the polysilicon gates of two adjacent NMOS transistors. Therefore, when halo ion implantation (Halo I / I) is performed at a tilt angle of 30 degrees, shadowing by a polysilicon gate occurs. For example, if the gate height of a polysilicon gate is 150 nm high enough to prevent ion penetration, the Halo I / I cannot be performed if the distance between adjacent polysilicon gates is 87 nm or less. In such a case, in this embodiment, impurities are introduced by performing solid phase diffusion.

  1A to 1C are cross-sectional views schematically showing a part of the manufacturing process of the CMOS LSI according to the first embodiment of the present invention. First, as shown in FIG. 1A, a narrow substrate surface layer portion between adjacent polysilicon gates 11 of two transistors formed on a semiconductor substrate, in this example, a silicon substrate 10, in a shared drain region in this example. Perform solid phase diffusion. At this time, when solid phase diffusion is performed in the NMOS transistor region, a polysilicon film 13 doped with arsenic (As) or phosphorus (P) as an N-type impurity is deposited in a state where the PMOS transistor region is protected by the resist 12. To do. Further, in order to suppress the outward diffusion of impurities and promote the diffusion to the silicon substrate 10, as shown in FIG. 1B, the polysilicon film 13 is covered with a TEOS oxide film 14, and the impurities are diffused by annealing. As a result, a shallow impurity diffusion region (extension region) 151 having a low concentration is formed in the shared drain region.

  When solid phase diffusion is performed on the PMOS transistor region, a boron silicate glass (BSG) film doped with, for example, boron (B) as a P-type impurity is deposited with the NMOS transistor region protected with a resist. Then, in order to suppress the outward diffusion of the impurities and promote the diffusion to the silicon substrate, the polysilicon film is covered with a TEOS oxide film, and the impurities are diffused by annealing.

  Next, as shown in FIG. 1C, the TEOS oxide film 14 and the polysilicon film 13 are removed, and the resist 12 is further removed. Subsequently, a gate sidewall insulating film 16 is formed on the polysilicon gate 11, and ion implantation and annealing are performed using the gate sidewall insulating film 16 as a mask to form a high-concentration deep impurity diffusion region 152. Thereafter, an interlayer insulating film 17 is deposited on the substrate, a contact hole is opened on the high-concentration drain region 152 in the shared drain region, a contact plug 18 is embedded in the contact hole, and further on the interlayer insulating film 17. A predetermined connection wiring 19 is formed by patterning.

  According to the present embodiment, since the solid-phase diffusion is used when introducing impurities into the narrow substrate surface layer portion between the polysilicon gates 11 of two adjacent transistors, the height variation of the polysilicon gate 11 varies. Impurities can be introduced without being affected by the above. That is, even if the height of the polysilicon gate 11 varies, the variation in the characteristics of the MOS transistor can be reduced. As a result, it is possible to reduce the distance between the gate contacts (GC) while keeping the variation in characteristics of the MOS transistor within an allowable range, and to reduce the cell size of the SRAM.

<Second Embodiment>
In the second embodiment, when forming a MOS transistor on a semiconductor substrate, a case where impurities are doped by ion implantation into the channel region of the MOS transistor is taken as an example.

  In a conventional process, patterning is performed using a lithography method so that a region where doping is not desired is covered with a resist. For example, as shown in FIG. 2, a region including an insulating region (hereinafter referred to as an STI region) 22 having a shallow trench structure sandwiching a channel region of a MOS transistor is covered with a resist (indicated by a broken line R in FIG. 2). . Then, ion implantation (indicated by a broken line I in FIG. 2) is performed using the resist as a mask. In order to prevent channeling to the substrate, ion implantation is performed at an angle. In this case, the STI region 22 normally rises from the substrate surface, has a step with respect to the substrate surface, and further has a resist thereon. As a result, the end region A of the active region (active area) adjacent to the STI region 22 is not implanted with impurities regardless of the region to be doped, and has characteristics different from the desired electrical characteristics. Will be obtained. Thereafter, if the width of the gate of the MOS transistor formed on the active region adjacent to the STI region 22 is sufficiently larger than the end region A, the above characteristic variation is reduced.

  However, when the MOS transistor is miniaturized, the gate width naturally has to be reduced, and therefore the influence of the end region A on the characteristics cannot be ignored. In other words, when doping the impurity into the channel region of the MOS transistor, the step width of the STI region 22 adjacent to the channel region and the resist thereon become an obstacle as the gate width becomes narrower, and the influence of resist shadowing occurs. , The concentration of the impurity ion-implanted is reduced in the end region A.

  Since the size of the end region A is not constant and varies mainly due to misalignment of lithography, the presence of the end region A causes variation in characteristics. This characteristic variation depends on the maximum lithography misalignment amount and the gate width, and the relationship between the gate width and the threshold voltage variation with respect to the mask misalignment is as shown in FIG. 3, for example. Here, it can be seen that when the gate width W is smaller than 500 nm, the threshold voltage variation 3σVth increases rapidly.

  As described above, when the gate width W is smaller than 500 nm, in this embodiment, by introducing impurities by solid phase diffusion, the impurity concentration in the end region A is kept high, and the variation in threshold voltage of the MOS transistor is reduced. Reduce.

  FIG. 2 is a sectional view schematically showing a part of the manufacturing process of the MOS LSI according to the second embodiment of the present invention. First, when a MOS transistor is formed on a semiconductor substrate, in this example, a silicon substrate 20, in the case where solid phase diffusion is performed on the channel region 21 of the MOS transistor sandwiched between the STI regions 22, the PMOS transistor region is resisted (see FIG. A polysilicon film 24 doped with arsenic or phosphorus as an N-type impurity in a state protected by (not shown), and then a polysilicon film for suppressing the outward diffusion of the impurity and promoting the diffusion to the silicon substrate 20 24 is covered with a TEOS oxide film 25, and impurities are diffused by annealing. Thereafter, the TEOS oxide film 25 and the polysilicon film 24 are removed.

  When solid phase diffusion is performed on the PMOS transistor region, a boron silicate glass film doped with, for example, boron as a P-type impurity is deposited with the NMOS transistor region protected with a resist. Then, in order to suppress the outward diffusion of the impurities and promote the diffusion to the silicon substrate, the polysilicon film is covered with a TEOS oxide film, and thereafter, the impurities are diffused by annealing.

  When this embodiment is applied, the impurity diffuses up to the end region A (at the STI region) of the active region, so that the impurity concentration in the end region A can be kept high. This is advantageous in controlling the threshold voltage value of the MOS transistor, and variation in the threshold voltage of the MOS transistor can be reduced. Further, the impurity concentration of the active region can be controlled without being affected by the variation in the height of the step portion of the STI region 22.

  In addition, by applying this embodiment to a random gate portion of a device having a random gate, even a MOS transistor having a small gate width is not affected by the height of the STI region, so that device variations are reduced.

<Third Embodiment>
In the third embodiment, the manufacturing process of the peripheral portion of the STI region for separating the P well in the NMOS transistor formation region and the N well in the PMOS transistor formation region is taken as an example.

  When forming the CMOS transistor, as shown in FIG. 4G, the STI is used to separate the P well 411 in the NMOS transistor formation region and the N well 412 in the PMOS transistor formation region. Region 42 is formed. An N + diffusion layer 431 is formed as the drain / source region of the NMOS transistor on the surface of the P well 411, and a P + diffusion layer 432 is formed as the drain / source region of the PMOS transistor on the surface of the N well 412. To do.

  As the width of the STI region 42 (well separation width) is scaled, it is difficult to prevent punch-through between the diffusion layer and the well region with the conventional technique. In order to prevent punch-through, the depletion layer generated at the junction interface between the diffusion layer and the well region may be separated from the depletion layer generated at the well interface, or the width of the depletion layer may be reduced. For the former, the STI depth should be increased, and for the latter, the well impurity concentration should be increased.

  However, as described above, increasing the STI depth is as follows when the well region for making contact with the well region (well contact) is formed to have a depth greater than the STI depth. With serious problems. That is, due to lithography problems, it is necessary to reduce the thickness of the protective resist, and if ion implantation is performed at a high acceleration to form a deep well region, there is a high risk that ions will penetrate the protective resist. In other words, when ion implantation is used, punch-through reduction is not compatible with lithography technology.

  On the other hand, increasing the impurity concentration of the well as described above involves the problem that the junction capacitance Cj between the diffusion layer and the well region increases. As shown in FIG. 5B, the well breakdown voltage Vpt and the junction capacitance Cj are in a trade-off relationship when the well isolation width is used as a parameter. As the well breakdown voltage Vpt improves (increases), the junction capacitance Cj also increases. When the well separation width becomes smaller than 0.1 μm (100 nm), the Vj dependence of Cj increases rapidly.

  In order to solve such a problem, in this embodiment, a structure in which the impurity concentration in the periphery of the well separation STI region is higher than the impurity concentration in other portions of the same depth in each well by a solid phase diffusion process. Form.

  4A to 4G are cross-sectional views schematically showing a part of the manufacturing process of the CMOS LSI according to the third embodiment of the present invention. First, as shown in FIG. 4A, an SiN film pattern 46 for an etching mask is formed on a semiconductor substrate, in this example, a silicon substrate 40, and a well isolation trench 42a is formed in the surface layer portion of the silicon substrate 40. .

  Next, as shown in FIG. 4B, an oxide film 47 doped with, for example, boron (B) as a P-type impurity is deposited on the entire surface, and this oxide film 47 is left on the P well formation scheduled region. Pattern. Next, as shown in FIG. 4C, an oxide film 48 doped with, for example, phosphorus (P) as an N-type impurity is deposited on the entire surface.

  Next, an oxide film is deposited on the entire surface, and CMP is performed to remove the oxide films 48 and 47 and the SiN film pattern 46 on the silicon substrate 40. As shown in FIG. A well isolation STI region 42 is formed by burying an insulator in the trench 42a.

  Next, as shown in FIG. 4E, ion implantation for forming the P well region 411 is performed, and further, ion implantation for forming the N well region 412 is performed. Thereafter, the impurity is diffused by annealing as shown in FIG. At this time, since impurities diffuse from the oxide films 47 and 48 doped with impurities in the well isolation trench 42a to the side and bottom surfaces of the trench 42a, the well concentration increases only in the vicinity of the trench 42a.

  Thereafter, as shown in FIG. 4G, an N + diffusion layer 431 is formed as the drain / source region of the NMOS transistor on the surface of the P well 411, and the drain / source of the PMOS transistor is formed on the surface of the N well 412. A P + diffusion layer 432 is formed as a region.

  According to the manufacturing method of this embodiment, since the impurity concentration increases only around the well isolation STI region 42 in the well region of the CMOS LSI, the junction capacitance Cj does not change, and only the well breakdown voltage Vpt can be improved. .

FIG. 5A shows the relationship between the impurity concentration of the solid phase diffusion region around the STI region for well isolation and the well breakdown voltage Vpt in the CMOS LSI of this embodiment. When the STI depth is 300 nm or less and the well separation width is 100 nm or less, the well breakdown voltage Vpt is 5 V or more if the impurity concentration in the solid phase diffusion region is higher than 1 × 10 ¹⁸ / cm ³ . Therefore, a sufficient well breakdown voltage Vpt can be obtained without increasing the STI.

  Note that the black circles in FIG. 5B show the relationship between the well breakdown voltage Vpt and the junction capacitance Cj when the well isolation width is (0.04 μm) 40 nm in the CMOS LSI of this embodiment.

One example of the CMOS LSI of this embodiment is a depth of 300 nm or less and a width of 100 nm formed to separate the P well in the NMOS transistor formation region, the N well in the PMOS transistor formation region, and the P well and the N well. An element isolation region having the following trench structure, an N diffusion layer for the drain / source region of the NMOS transistor formed on the surface of the P well, and a drain / source of the PMOS transistor formed on the surface of the N well And a P diffusion layer for the region. In each well, an impurity is introduced into the periphery of the element isolation region by solid phase diffusion, the impurity concentration is higher than 1 × 10 ¹⁸ / cm ³ , and the impurity concentration is higher than that of other portions at the same depth. Is expensive.

<Fourth Embodiment>
In the fourth embodiment, an example of the structure and manufacturing process of an MOS transistor having an elevated structure in which the source / drain regions are made higher than the substrate surface is taken.

  When forming an elevated structure MOS transistor, as shown in FIG. 6B, the boundary between the gate sidewall 73 and the epitaxial growth diffusion layer 74 is a very narrow depression. If a Halo I / I layer is formed in the back of this recess by the same process as before, impurities can be introduced only from one side by ion implantation, and the tilt angle is limited. It is difficult to form a Halo I / I layer. In such a case, in this embodiment, impurities are introduced by performing solid phase diffusion.

  6A to 6C are cross-sectional views schematically showing a part of the manufacturing process of the MOS LLSI according to the fourth embodiment of the present invention. When forming an MOS transistor with an elevated structure, first, as shown in FIG. 6A, a gate insulating film 71, a gate electrode 72, After the gate sidewall 73 is formed, the substrate surface is etched using the gate sidewall 73 as a protective film. Thereafter, as shown in FIG. 6B, SiGe is epitaxially grown from the silicon surface below the gate side wall 73 to form a diffusion layer (epitaxial growth diffusion layer) 74 at a position higher than the original silicon surface. At this time, the boundary between the gate side wall 73 and the epitaxial growth diffusion layer 74 is like a very narrow depression.

  Next, impurities are introduced below the gate side wall 73 by solid phase diffusion. At this time, when solid phase diffusion is performed on the NMOS transistor region, the PMOS transistor region is protected with a resist. Then, after depositing a polysilicon film 76 doped with arsenic (As) or phosphorus (P) as an N-type impurity, on the polysilicon film 76 in order to suppress the outward diffusion of the impurity and promote the diffusion to the silicon substrate. Is covered with a TEOS oxide film 77, and impurities are diffused by annealing. At this time, since the solid phase diffusion is isotropic diffusion, the impurity 75 a can be introduced below the gate side wall 73. Note that in order to control the movement distance of impurities, it is necessary to appropriately set (tune) the annealing temperature and time. Thereafter, the TEOS oxide film 77 and the polysilicon film 76 are removed. Then, as shown in FIG. 6C, for example, source / drain regions 75 of a MOS transistor having an LDD structure are formed by ion implantation and annealing.

  When solid phase diffusion is performed in the PMOS transistor region, after depositing a boron silicate glass (BSG) film doped with, for example, boron (B) as a P-type impurity in a state where the NMOS transistor region is protected with a resist, Impurities are diffused by annealing.

  According to the manufacturing method of the present embodiment, the impurity 75a can be introduced below the gate sidewall 73 into the epitaxially grown SiGe transistor in which the boundary between the gate sidewall 73 and the epitaxial growth diffusion layer 74 is recessed in the CMOS LSI. it can. Also, according to the present embodiment, unlike the conventional ion implantation, the impurity concentration in the LDD portion can be realized to be the highest on the outermost surface of the silicon layer, so that the effect of suppressing the junction leakage current is obtained. It is done.

  An example of the present embodiment is an epitaxial growth from a gate electrode, an impurity diffusion layer for source / drain regions, a gate sidewall, a semiconductor substrate surface below the gate sidewall to a position higher than the surface, and the gate sidewall In a semiconductor device having a CMOS transistor including an epitaxially grown diffusion layer having a depression at the boundary thereof, impurities are introduced by solid phase diffusion below the gate sidewall.

Sectional drawing which shows schematically the manufacturing process of the CMOS LSI which concerns on 1st Embodiment of this invention. Sectional drawing which shows schematically the manufacturing process of MOS LSI concerning 2nd Embodiment of this invention. The characteristic view which shows the relationship between the gate width of a MOS transistor, and the dispersion | variation in threshold voltage at the time of using the conventional process in MOS LSI of 2nd Embodiment. Sectional drawing which shows schematically the manufacturing process of the CMOS LSI which concerns on 3rd Embodiment of this invention. The figure which shows the relationship between the impurity density | concentration of the solid-phase diffusion area | region of STI area | region surrounding a STI area | region in 3rd Embodiment, and a well breakdown voltage, and the relationship between a well breakdown voltage and junction capacitance. Sectional drawing which shows schematically the manufacturing process of LSI which concerns on 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 20, 40, 70 ... Semiconductor substrate, 11 ... Polysilicon gate, 12 ... Resist, 13 ... Polysilicon film, 14 ... TEOS oxide film, 151 ... Low concentration shallow impurity diffusion region, 152 ... High concentration deep impurity Diffusion region, 16 ... gate side wall insulating film, 17 ... interlayer insulating film, 18 ... contact plug, 19 ... connection wiring.

Claims (5)

In the semiconductor device in which two MOS transistors having the same polarity share one impurity diffusion layer of each source / drain region and each polysilicon gate of the two MOS transistors has a portion adjacent to each other.
The height of each polysilicon gate of the two MOS transistors is 150 nm or more, the distance between adjacent polysilicon gates is 87 nm or less, and the impurity diffusion layer shared by the two MOS transistors is a diffusion layer surface portion. A semiconductor device characterized in that the impurity concentration of is the highest inside the diffusion layer.   In the semiconductor device having a MOS transistor, the channel region of the MOS transistor has both ends in the channel width direction adjacent to the element isolation region of the trench structure, and impurities are introduced by solid phase diffusion. A semiconductor device characterized in that the central portion and the peripheral portion in the width direction are substantially equal. A P well in an NMOS transistor formation region, an N well in a PMOS transistor formation region, an element isolation region having a trench structure formed to separate the P well and the N well and having a depth of 300 nm or less and a width of 100 nm or less; A semiconductor having an N diffusion layer for the drain / source region of the NMOS transistor formed on the surface of the P well and a P diffusion layer for the drain / source region of the PMOS transistor formed on the surface of the N well. A device manufacturing method comprising:
Forming a pattern for an etching mask on the semiconductor substrate, and forming a trench isolation element isolation region having a depth of 300 nm or less and a width of 100 nm or less in a surface layer portion of the semiconductor substrate;
Depositing a first oxide film doped with a P-type impurity on the entire surface of the semiconductor substrate, and patterning the first oxide film to leave on the P-well region;
Depositing a second oxide film doped with an N-type impurity on the entire surface, and patterning the second oxide film so as to remain on the N-well region;
An oxide film for suppressing outward diffusion of impurities and promoting diffusion to the semiconductor substrate is deposited on the entire surface of the semiconductor substrate, and then the oxide film on the semiconductor substrate is subjected to chemical mechanical polishing. And leaving the oxide film in the trench of the element isolation region;
Peeling the pattern for the etching mask;
Performing ion implantation for forming the P-well region and ion implantation for forming the N-well region;
And a step of diffusing impurities by annealing, and forming a region having a higher impurity concentration than other portions of the same depth around the element isolation region in each well. Method. A gate electrode of a MOS transistor, an impurity diffusion layer for source / drain regions, a gate side wall, and an epitaxial growth diffusion layer epitaxially grown from the surface of the semiconductor substrate below the gate side wall to a position higher than the surface. A method of manufacturing a semiconductor device having a MOS transistor,
Forming a gate electrode, an impurity diffusion layer for source / drain regions, and a gate sidewall, and then etching the surface of the impurity diffusion layer using the gate sidewall as a protective film;
Epitaxially growing SiGe from the semiconductor substrate surface below the gate sidewall, and forming an epitaxial growth diffusion layer at a position higher than the original semiconductor substrate surface;
And a step of introducing an impurity by solid phase diffusion below the side wall of the gate.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of introducing impurities by solid phase diffusion, the temperature and time of annealing are set appropriately to control the movement distance of the impurities.

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