JP2008249379A - Semiconductor integrated circuit and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce human cost and a test time to be required for a scanning test when the scanning test is performed for a part of a gate array block. <P>SOLUTION: A gate array block 2 having a scanning test inapplicable circuit 21, 23, and a scanning test applicable circuit 22 is provided. A multiplexer 24 selects an input signal to be input to a circuit 21 on the occasion of usual use, and a scanning test signal to be input to a circuit 22 on the occasion of the scanning test, and leads this selected signal to the circuits 21, 22. An output circuit 25 takes out a signal representing the result of a scanning test to be output from the circuit 22 on the occasion of the scanning test. Moreover, the scanning test signal and an input signal to the circuit 21 are input from external terminals 11 to the multiplexer 24 via an I/O block 1 respectively, and the output signal of the output circuit 25 is output to an external terminal 11 via the I/O block 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit (IC) adapted to, for example, an LCD driver, and in particular, when a scan test is performed on a part of a circuit including a gate array included in the IC, the test coverage is increased. The present invention relates to a semiconductor integrated circuit that can be guaranteed and subjected to a shipping inspection, and a test method thereof.

Conventionally, in a configuration in which a gate array is included inside, such as a semiconductor integrated circuit of a display driver such as an LCD driver, an asynchronous circuit is mainly used as a circuit configured by the gate array. In this case, the design for testability (DFT) cannot be adopted at the time of designing for the entire circuit composed of the gate array.
For this reason, when a guarantee inspection (operation test) is performed on the entire circuit at the time of shipment, a test program based on specifications is created and used instead of ATPG (Automatic Test Pattern Generation).

In a general application-specific IC (ASIC), since the entire chip is designed in a hardware description language or a synchronous circuit design, the DFT method can be used for the entire circuit.
By the way, in a semiconductor integrated circuit that executes a scan test method, when a circuit that can be applied to a scan test and a circuit that cannot be applied to a scan test are included, a scan test is performed on a circuit that can be applied to a scan test. An invention to be performed is disclosed (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 6-18632

However, in the case of a semiconductor integrated circuit including a block made of an analog circuit in addition to a gate array block made of a digital circuit, like the semiconductor integrated circuit for a display driver, the invention according to Patent Document 1 It cannot be applied as it is.
Therefore, in such a semiconductor integrated circuit, when performing a scan test on a part of the gate array block, it is possible to reduce the human cost and test time required for the test and to guarantee the test. A new semiconductor integrated circuit and a test method thereof are desired.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit capable of reducing the human cost and test time required for a test and guaranteeing the test when a scan test is performed on a part of a gate array block. It is to provide a circuit and a test method thereof.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
A first invention is a test of a semiconductor integrated circuit including at least a gate array block having a first circuit to which a scan test is not applicable and a second circuit to which a scan test is applicable, and an I / O block having an external terminal The scan test for the second circuit is performed by taking a scan test signal from the external terminal and passing it through the I / O block to the second circuit. The signal indicating the result of the scan test output from is routed to the external terminal via the block I / O.

  According to a second aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit comprising at least a gate array block having a first circuit to which a scan test is not applicable and a second circuit to which the scan test is applicable, and a predetermined block having an external terminal A dedicated path for a scan test for electrically connecting the second circuit and the external terminal is provided, and the scan test for the second circuit takes a scan test signal from the external terminal. The signal indicating the result of the scan test output from the second circuit is guided to the external terminal via the dedicated path. I made it.

  The third invention includes a first circuit to which the scan test cannot be applied and a second circuit to which the scan test can be applied. These include at least a gate array block constituting a controller and a driver block having an external terminal. A test method for a semiconductor integrated circuit for a display driver, comprising: a scan test dedicated path for electrically connecting the second circuit and the external terminal, and a scan test for the second circuit Is implemented by taking a scan test signal from the external terminal and guiding it to the second circuit via the dedicated path, and a signal indicating the result of the scan test output from the second circuit is the dedicated signal It was led to the external terminal via a route.

  A fourth invention is a semiconductor integrated circuit comprising at least a gate array block having a first circuit to which the scan test is not applicable and a second circuit to which the scan test is applicable, and an I / O block having an external terminal. Then, an input signal input to the first circuit during normal use and a scan test signal input to the second circuit during a scan test are selected, and this selection signal is selected as the first or second circuit. Selection means for leading to the output, and output means for extracting a signal indicating the result of the scan test output from the second circuit at the time of a scan test, and the input signal of the first circuit and the scan test signal are respectively The signal input from the external terminal to the selection means via the I / O block and taken out by the output means is the I / O block. It is adapted to be outputted to the external terminal via, and said selection means and said output means are provided in the gate array block.

A fifth invention includes a first circuit to which the scan test is not applicable and a second circuit to which the scan test is applicable, and includes at least a gate array block constituting a controller and a driver block having an external terminal. The display driver includes a semiconductor integrated circuit for selecting an input signal input to the first circuit during normal use and a scan test signal input to the second circuit during a scan test. Selection means for guiding a signal to the first or second circuit; output means for extracting a signal indicating a result of a scan test output from the second circuit during a scan test; the external terminal; the selection means; And a dedicated path for electrically connecting each of the output means, and the selection means is configured to output the external device during a scan test. A scan test signal that is input from a child and passes through the dedicated path is received, and the output means sends a signal indicating the result of the scan test to the external terminal via the dedicated path during a scan test. The selection means and the output means are provided in the gate array block.
According to the present invention having such a configuration, when the scan test is performed on a part of the gate array block, the human cost and the test time required for the test can be shortened and the test can be guaranteed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
A configuration of a first embodiment of a semiconductor integrated circuit to which the present invention is applied will be described with reference to FIG.
As shown in FIG. 1, the semiconductor integrated circuit according to the first embodiment is applied to a display driver such as an LCD driver, and includes a gate array including an I / O block 1 and a gate array. A block 2, driver blocks 3 and 4, and memory blocks 5 and 6 are provided. They are configured independently and function as a display driver as a whole.

The I / O block 1 is composed of an I / O circuit, and has a plurality of external terminals 11 as shown in the figure. The I / O block 1 exchanges signals with the outside through the external terminals 11, and also includes a gate array block. Signals are exchanged with 2.
As shown in the figure, the gate array block 2 includes scan test non-applicable circuits 21 and 23 to which a scan test cannot be applied, and a scan test application circuit 22 to which a scan test can be applied, which control each unit as a display driver controller. Is supposed to do.

Further, the gate array block 2 includes a multiplexer 24 and an output circuit 25 as shown in the figure.
The multiplexer 24 selects an input signal that is input to the scan test non-applied circuit 21 during normal use and a scan test signal that is input to the scan test applied circuit 22 during the scan test. 22 is led. These two signals are input to the multiplexer 24 from the external terminal 11 via the I / O block 1.

The output circuit 25 extracts a signal indicating the result of the scan test output from the scan test application circuit 22 during the scan test. The extracted signal is output to the external terminal 11 via the I / O block 1.
Each of the driver blocks 3 and 4 includes an analog circuit (drive circuit) that drives a display unit (not shown). The driver blocks 3 and 4 respectively have a plurality of external terminals 31 and 41 that output drive signals to the outside. The memory blocks 5 and 6 can store data.

Next, a method of performing a scan test on the scan test application circuit 22 in the gate array block 2 in the first embodiment having such a configuration will be described with reference to FIG.
At the time of the scan test, the scan test signal is inputted to the I / O block 1 from a predetermined part of the plurality of external terminals 11, and the I / O block 1 supplies it to the multiplexer 24 of the gate array block 2. At this time, the multiplexer 24 guides the scan test signal to the scan test application circuit 22.

As a result, the scan test application circuit 22 performs the scan test, and a signal indicating the result of the scan test is output from the scan test application circuit 22. At this time, the output circuit 25 captures a signal indicating the result of the scan test and outputs the captured signal to the I / O block 1. The I / O block 1 outputs the signal to a predetermined part of the plurality of external terminals 11.
As described above, according to the first embodiment, when a scan test is performed on a part of the gate array block 2, the human cost and test time required for the test can be shortened and the test is guaranteed. it can.

(Second Embodiment)
The configuration of the second embodiment of the semiconductor integrated circuit to which the present invention is applied will be described with reference to FIG.
As shown in FIG. 2, the semiconductor integrated circuit according to the second embodiment is applied to a display driver such as an LCD driver, and includes a gate array composed of an I / O block 1 and a gate array. A block 2a, driver blocks 3 and 4, and memory blocks 5 and 6 are provided. They are configured independently and function as a display driver as a whole.

This second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and dedicated paths (dedicated wirings) 7 and 8 dedicated to the scan test are added as shown in FIG. The configuration of the array block 2 is replaced with the configuration of the gate array block 2a.
Accordingly, the same components are denoted by the same reference numerals, and the description thereof is omitted as much as possible. In the following description, portions having different configurations are mainly described.
As shown in FIG. 2, the gate array block 2a includes a multiplexer 24a and an output circuit 25a.

  The multiplexer 24a selects the input signal from the I / O block 1 during normal use and outputs it to the scan test inapplicable circuit 21. During the scan test, the multiplexer 24a receives the scan test signal input from the external terminal 41 and passing through the dedicated path 7. These are selected and output to the scan test application circuit 22. For this reason, the dedicated path 7 has one end connected to the multiplexer 24 a and the other end electrically connected to, for example, a predetermined part of the external terminal 41 of the driver block 4.

  The output circuit 25 a takes out a signal indicating the result of the scan test output from the scan test application circuit 22 during the scan test, and outputs the signal to the external terminal 41 via the dedicated path 8. Therefore, one end side of the dedicated path 8 is connected to the output circuit 25a, and the other end side is electrically connected to a predetermined part of the external terminal 41 of the driver block 4, for example.

Next, a method of performing a scan test on the scan test application circuit 22 in the gate array block 2a in the second embodiment having such a configuration will be described with reference to FIG.
At the time of the scan test, the scan test signal is input from the predetermined part of the plurality of external terminals 41 to the multiplexer 24a via the dedicated path 7. At this time, the multiplexer 24 a guides the scan test signal to the scan test application circuit 22.

  As a result, the scan test application circuit 22 performs the scan test, and a signal indicating the result of the scan test is output from the scan test application circuit 22. At this time, the output circuit 25a takes in a signal indicating the result of the scan test and outputs this taken signal to the dedicated path 8. The signal is output to the outside from the external terminal 41 via the dedicated path 8.

As described above, according to the second embodiment, when a scan test is performed on a part of the gate array block 2a, the human cost and test time required for the test can be reduced, and the test is guaranteed. it can.
In the second embodiment, the external terminals of a block having a large number of external terminals 41 such as the driver block 4 can be used.

It is a block diagram which shows the structure of 1st Embodiment of this invention. It is a block diagram which shows the structure of 2nd Embodiment of this invention.

Explanation of symbols

  1 ... I / O block, 2, 2a ... gate array block, 3, 4 ... driver block, 5, 6 ... memory block, 7, 8 ... dedicated path (dedicated wiring), 11, 31, 41 ... external terminals

Claims (5)

A test method of a semiconductor integrated circuit comprising at least a gate array block having a first circuit to which a scan test is not applicable and a second circuit to which a scan test is applicable, and an I / O block having an external terminal,
The scan test for the second circuit is performed by taking a scan test signal from the external terminal and passing it through the I / O block to the second circuit,
A test method for a semiconductor integrated circuit, wherein a signal indicating a result of a scan test output from the second circuit is guided to the external terminal via the block I / O. A test method for a semiconductor integrated circuit comprising at least a gate array block having a first circuit to which a scan test is not applicable and a second circuit to which a scan test is applicable, and a predetermined block having an external terminal,
A dedicated path for a scan test that electrically connects the second circuit and the external terminal is provided,
The scan test for the second circuit is performed by taking a scan test signal from the external terminal and guiding it to the second circuit via the dedicated path,
A test method for a semiconductor integrated circuit, wherein a signal indicating a result of a scan test output from the second circuit is guided to the external terminal via the dedicated path. A display driver semiconductor having a first circuit to which a scan test cannot be applied and a second circuit to which a scan test can be applied, and comprising at least a gate array block constituting a controller and a driver block having an external terminal An integrated circuit test method comprising:
A dedicated path for a scan test that electrically connects the second circuit and the external terminal is provided,
The scan test for the second circuit is performed by taking a scan test signal from the external terminal and guiding it to the second circuit via the dedicated path,
A test method for a semiconductor integrated circuit, wherein a signal indicating a result of a scan test output from the second circuit is guided to the external terminal via the dedicated path. A semiconductor integrated circuit comprising at least a gate array block having a first circuit to which a scan test is not applicable and a second circuit to which a scan test is applicable, and an I / O block having an external terminal,
An input signal input to the first circuit during normal use and a scan test signal input to the second circuit during a scan test are selected, and this selection signal is guided to the first or second circuit. A selection means;
An output means for extracting a signal indicating the result of the scan test output from the second circuit at the time of the scan test,
The input signal of the first circuit and the scan test signal are input from the external terminal to the selection unit via the I / O block, and the signal taken out by the output unit passes through the I / O block. And output to the external terminal,
The semiconductor integrated circuit is characterized in that the selection means and the output means are provided in the gate array block. A display driver semiconductor having a first circuit to which a scan test cannot be applied and a second circuit to which a scan test can be applied, and comprising at least a gate array block constituting a controller and a driver block having an external terminal An integrated circuit,
An input signal input to the first circuit during normal use and a scan test signal input to the second circuit during a scan test are selected, and this selection signal is guided to the first or second circuit. A selection means;
An output means for extracting a signal indicating the result of the scan test output from the second circuit during the scan test;
A dedicated path for electrically connecting the external terminal and the selection means and the output means, respectively,
The selection means is configured to receive a scan test signal that is input from the external terminal and passes through the dedicated path during a scan test,
The output means is configured to output a signal indicating a result of a scan test to the external terminal via the dedicated path during a scan test,
The semiconductor integrated circuit is characterized in that the selection means and the output means are provided in the gate array block.

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