JP2008245387A - Switching power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power supply capable of coping with voltage fluctuation in an electric double-layer capacitor. <P>SOLUTION: The switching power supply includes: the electric double-layer capacitor 2; a first transformer 11 having primary winding 11a and secondary winding 11b; FET 12 that is connected in series with the primary winding 11a and switches input voltage Vin from the electric double-layer capacitor 2; FET 15 for synchronous rectification; the primary winding 17a of a transformer 17 and a capacitor 18 connected across the secondary winding 11b; FET 16 connected in parallel with a series circuit of the primary winding 17a and the capacitor 18; secondary winding 17b magnetically coupled with the primary winding 17a; a diode 20 and a capacitor 21 that rectify and smooth alternating-current voltage V2 induced in the secondary winding 17b to generate direct-current voltage V3; and a switching control circuit 22 that operates on the direct-current voltage V3 and controls switching of the FETs 12, 15, 16. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a forward-type switching power supply apparatus using synchronous rectification that generates a DC voltage by switching.

  As this type of forward switching power supply (hereinafter also referred to as “switching power supply”), a switching power supply disclosed in US Pat. No. 5,535,112 is known. This switching power supply device is a switching power supply device that combines a so-called active clamp method and synchronous rectification, and includes a first FET (field effect transistor) that switches an input voltage supplied to the primary winding of the transformer, A second FET for rectifying the AC voltage output to the secondary winding and a third FET for passing commutation current, a choke coil and a smoothing capacitor for smoothing the rectified output, and a state in series with the capacitor And a fourth FET connected in parallel to the primary winding of the transformer. In this case, the second FET and the third FET are n-channel FETs, the second FET is connected in series with the secondary winding of the transformer, and the third FET is connected in parallel with the secondary winding of the transformer. In addition, the gate terminal of the second FET is connected to one end of the secondary winding of the transformer that has a positive potential when the first FET is on, and the gate terminal of the third FET is connected to the other end of the secondary winding of the transformer. Yes.

In this switching power supply device, the second FET and the third FET are driven by a transformer, and when the first FET is on, the second FET is on and the third FET is off, and when the first FET is off, the second FET is When the third FET is turned off and the third FET is turned on, the AC voltage generated in the secondary winding of the transformer is rectified to generate a DC voltage. The fourth FET limits the voltage generated in the primary winding and the secondary winding of the transformer by turning on only for a predetermined period in the off period of the first FET. According to this switching power supply device, the third FET for passing commutation current can be turned on over the entire period in which the first FET is turned off, so that loss can be reduced.
US Pat. No. 5,535,112 (page 2-3, FIG. 1-4)

  However, this conventional switching power supply device has the following problems. That is, in this switching power supply device, the voltage generated at each end of the secondary winding of the transformer is directly input to the gate terminals of the second FET and the third FET, so that the voltage supplied to the primary winding of the transformer As the voltage increases / decreases, the voltage generated in the secondary winding, that is, the voltage applied to each gate terminal of the second FET and the third FET also increases / decreases. In this case, the voltage applied between the gate and source of each FET, that is, the voltage generated in the secondary winding of the transformer is set to the gate cut-off voltage in order to reliably turn on each FET while avoiding the gate breakdown. More than (about 4V) and lower than the absolute maximum rating (about 20V) of the gate-source voltage, this limits the voltage value of the input voltage supplied to the primary winding of the transformer. Therefore, this switching power supply device has a problem that it cannot cope with a wide range of input voltages.

  On the other hand, in recent years, for example, in an electric vehicle, an electric double layer capacitor is used as a DC power source, and a switching power supply device that generates various DC voltages from the electric double layer capacitor is used. In this case, there is a usage example in which the voltage supplied from the electric double layer capacitor varies in a range of about 12V to 60V. Therefore, it is desired to realize a synchronous rectification type switching power supply apparatus that can cope with such a wide range of input voltages.

  The present invention has been made in view of such problems, and a main object of the present invention is to provide a synchronous rectification type switching power supply apparatus that can cope with voltage fluctuations of an electric double layer capacitor.

  In order to achieve the above object, a switching power supply device according to claim 1, wherein an electric double layer capacitor, a first transformer having a primary winding and a secondary winding, and the electric double layer connected in series to the primary winding. A second switching element for periodically switching an input voltage supplied from a capacitor; a second switching element for synchronous rectification; a smoothing inductor; and a storage element for smoothing. A rectifying / smoothing circuit connected between both ends of the winding; a third switching element for passing commutation current connected in parallel to a series circuit of the inductor and the smoothing power storage element; the smoothing inductor; Detection coils coupled to each other, a voltage generation circuit for rectifying and smoothing an AC voltage induced in the detection coils, and generating a DC voltage, and using the DC voltage as a power source Working to, and a switching control circuit for generating and outputting a respective control signal for said second switching element and the third switching element to control the switching of the first switching element.

  The switching power supply device according to claim 2 is the switching power supply device according to claim 1, wherein the second switching element is electrically insulated from the control signal for the second switching element output from the switching control circuit. A second transformer for outputting to the element; and a third transformer for outputting to the third switching element while electrically insulating the control signal for the third switching element output from the switching control circuit.

  The switching power supply device according to claim 3 is the switching power supply device according to claim 1 or 2, wherein the switching power supply device has a power storage element and a fourth switching element connected in series, and is connected in parallel to the primary winding. The fourth switching element includes a clamp circuit that is controlled to be turned off when the first switching element is turned on and is turned on when the first switching element is turned off.

  As described above, in the switching power supply device according to claim 1, the switching control circuit is stabilized and generated by rectifying and smoothing the AC voltage induced in the detection coil magnetically coupled to the smoothing inductor. The control signal for the second switching element and the third switching element is generated by operating with the DC voltage as a power source. Therefore, according to this switching power supply device, the amplitude of the control signal for the second switching element and the third switching element can be maintained substantially constant, and as a result, the on-voltage (FET) is controlled regardless of the fluctuation of the input voltage from the electric double layer capacitor. In this case, it is possible to stably operate the second switching element and the third switching element by outputting a control signal having an amplitude equal to or higher than the gate cut-off voltage and lower than the absolute maximum rating.

  In the switching power supply device according to the second aspect, the control signal output from the switching control circuit is output to the second switching element and the third switching element while being electrically insulated by the transformer. Therefore, according to this switching power supply device, it is possible to improve the secular change, responsiveness and environmental resistance unlike the configuration of electrically insulating using a photocoupler. Can be planned.

  According to the switching power supply device of the third aspect, the primary circuit of the first transformer is provided with the clamp circuit having the fourth switching element and the storage element and connected in parallel to the primary winding of the first transformer. The voltage of the winding and the secondary winding can be limited, and the third switching element for passing the commutation current can be turned on over the entire period when the first switching element is turned off. The loss can be reduced and the efficiency can be improved.

  The best mode of a switching power supply according to the present invention will be described below with reference to the accompanying drawings.

  As shown in FIG. 1, a switching power supply device 1 includes an electric double layer capacitor 2 as a power source, and a voltage Vin between both ends of the electric double layer capacitor 2 (an input voltage in the present invention; hereinafter, also referred to as “voltage Vin”). And a forward type DC / DC converter 3 that generates an output voltage Vo based on the above.

  The DC / DC converter 3 includes a transformer 11. A first FET (field effect transistor) 12, a capacitor 13, and a clamp circuit 14 are disposed on the primary circuit side of the transformer 11, and on the secondary circuit side of the transformer 11. Includes a second FET 15, a third FET 16, a transformer 17, a capacitor 18, and a pair of output terminals 19 a and 19 b, and on the secondary winding 17 b side of the transformer 17 (on the primary circuit side of the transformer 11), A capacitor 21, a switching control circuit 22, a buffer circuit 23, and transformers 24 and 25 are arranged.

  The transformer 11 corresponds to the first transformer in the present invention, and includes a primary winding 11a and a secondary winding 11b. In this case, the primary winding 11a has a winding start side terminal (terminal with a mark) connected to the plus electrode of the electric double layer capacitor 2 and a winding end terminal (not marked with a mark). Side terminal) is connected to the negative electrode of the electric double layer capacitor 2 via the first FET 12.

  The first FET 12 is composed of an n-channel FET, and is connected in series to the primary winding 11a to function as the first switching element in the present invention, and switches the voltage Vin of the electric double layer capacitor 2. Specifically, the first FET 12 has a drain terminal connected to the winding end terminal of the primary winding 11 a and a source terminal connected to the negative electrode of the electric double layer capacitor 2. The capacitor 13 is connected in parallel to the electric double layer capacitor 2. The clamp circuit 14 includes a fourth FET 14a and a capacitor 14b. In this case, the fourth FET 14a is composed of an n-channel FET and functions as the fourth switching element in the present invention, and is connected in series with the capacitor 14b as the power storage element in the present invention. The clamp circuit 14 is connected in parallel to the primary winding 11a.

  The second FET 15 is composed of an n-channel FET, and functions as a second switching element for synchronous rectification in the present invention together with a diode 15a that is a body diode thereof. In this case, the drain terminal of the second FET 15 is connected to the winding end side terminal of the secondary winding 11b, and the source terminal thereof is connected to one end of the primary winding 17a of the transformer 17 (the terminal on the side marked with ·). It is connected. Here, the winding end side terminal of the secondary winding 11b is a winding start side terminal (a terminal marked with a mark when the AC voltage Vs is induced in the secondary winding 11b during the ON period of the first FET 12. ) Is a low voltage terminal. The second FET 15 has a gate terminal connected to one end of the secondary winding of the transformer 24 and a source terminal connected to the other end of the secondary winding of the transformer 24. When a transistor is used instead of the second FET 15, the diode 15 a can be configured by a separate and independent diode instead of the body diode of the second FET 15. The primary winding 17a of the transformer 17 functions as a smoothing inductor in the present invention, and the other end is connected to the capacitor 18 and the output terminal (minus side terminal) 19b.

  The third FET 16 is composed of an n-channel FET, and its source terminal is connected to one end of the primary winding 17a of the transformer 17, and its drain terminal is a winding start side terminal and an output terminal (plus side) of the secondary winding 11b. Terminal) 19a. The diode 16a is a body diode of the third FET 16 that is equivalently connected in parallel to the third FET 16, and functions together with the third FET 16 as a third switching element for passing commutation current in the present invention. When a transistor is used instead of the third FET 16, the diode 16 a can be configured by a separate and independent diode instead of the body diode of the third FET 16.

  The capacitor 18 corresponds to the smoothing storage element in the present invention, and has one end connected to the output terminal 19a and the other end connected to the output terminal 19b. The capacitor 18 is connected in series with the primary winding 17a of the transformer 17, the second FET 15 and the secondary winding 11b of the transformer 11, and together with the primary winding 17a of the transformer 17 and the second FET 15, the rectifying / smoothing circuit of the present invention is provided. Constitute. The secondary winding 17b magnetically coupled to the primary winding 17a of the transformer 17 functions as a detection coil in the present invention. The anode terminal of the diode 20 is connected to one end of the secondary winding 17b. The capacitor 21 has one end connected to the cathode terminal of the diode 20 and the other end connected to the other end of the secondary winding 17b. The diode 20 and the capacitor 21 function as a voltage generation circuit in the present invention. The diode 20 rectifies the AC voltage V2 induced in the secondary winding 17b of the transformer 17, and the capacitor 21 smoothes the capacitor. A DC voltage V3 proportional to the voltage V1 generated across the primary winding 17a is generated across the capacitor 21.

  The switching control circuit 22 operates using the DC voltage V3 as a power source, and is a switching control signal S1, which is a pulse signal having a predetermined cycle, and a polarity opposite to that of the switching control signal S1 (a low level period of the switching control signal S1 (first FET 12 The switching control signal (control signal in the present invention) S2 which is a pulse signal that becomes a high level period (the ON period of the third FET 16) is generated during the (off period). The switching control circuit 22 outputs the generated switching control signal S1 to the first FET 12 to perform on / off control of the first FET 12, and outputs the generated switching control signal S2 to the fourth FET 14a to turn on / off the fourth FET 14a. Turn off control. The switching control circuit 22 also performs on / off control of the second FET 15 and the third FET 16 by outputting the switching control signals S1 and S2 to the buffer circuit 23.

  At this time, the switching control circuit 22 is based on the AC voltage V2 induced in the secondary winding 17b of the transformer 17, specifically based on the DC voltage V3 generated by rectifying and smoothing the AC voltage V2. The output voltage Vo is maintained at a preset voltage by controlling the duty ratio of the switching control signal S1 and the duty ratio of the switching control signal S2 (according to the fluctuation of the DC voltage V3). The switching control circuit 22 outputs an output when a current value detected by a current transformer (not shown) disposed between the primary winding 11a of the transformer 11 and the drain of the first FET 12 exceeds a predetermined current value, for example. Assuming that the current has reached an abnormally large current value, the switching operation for the first FET 12 is stopped (overcurrent operation). Further, the switching control circuit 22 assumes that the output voltage Vo has reached an abnormally high voltage value when, for example, a Zener diode (not shown) arranged in parallel with the secondary winding 17b of the transformer 17 becomes conductive. The switching operation for 1FET 12 is stopped (overvoltage operation).

  As an example, the buffer circuit 23 includes two sets of complementary emitter follower circuits 31 and 32 and two capacitors 33 and 34 as shown in FIG. In this case, as shown in the figure, the complementary emitter follower circuit 31 is composed of an NPN transistor 31a and a PNP transistor 31b in which the base terminals are connected to each other and the emitter terminals are connected to each other, and the complementary emitter follower circuit 32 is The NPN transistor 32a and the PNP transistor 32b are connected to each other between base terminals and emitter terminals. In the complementary emitter follower circuit 31 configured as described above, as shown in the figure, the DC voltage V3 is operated as a power source so that the transistor 31a receives the high level switching control signal S1 and the switching control signal S1. The direct current component is cut by the capacitor 33 and output as the switching control signal S3. Further, the transistor 31b operates using the DC voltage V3 as a power source, inputs the low level switching control signal S1, and releases the DC component stored in the capacitor 33 to the reference potential. Further, in the complementary emitter follower circuit 32, as shown in the figure, the DC voltage V3 is operated as a power source so that the transistor 32a receives the high level switching control signal S2 and also converts the DC component of the switching control signal S2 into the capacitor 34. And is output as a switching control signal S4. Further, the transistor 32b operates using the DC voltage V3 as a power source, inputs the low level switching control signal S2, and releases the DC component stored in the capacitor 34 to the reference potential.

  The transformer 24 is a second transformer according to the present invention. As shown in FIG. 2, the primary winding 24a is connected to the complementary emitter follower circuit 31 of the buffer circuit 23 to electrically input the switching control signal S3. The signal is output from the secondary winding 24b as the switching control signal S5 while being insulated. The switching control signal S5 is output between the gate terminal and the source terminal of the second FET 15 as shown in FIG. The transformer 25 is a third transformer according to the present invention. As shown in FIG. 2, the primary winding 25a is connected to the complementary emitter follower circuit 32 of the buffer circuit 23 to electrically input the switching control signal S4. It outputs from secondary winding 25b as switching control signal S6, insulating. The switching control signal S6 is output between the gate terminal and the source terminal of the third FET 16 as shown in FIG. In this case, the amplitudes of the switching control signals S1 and S2 and the turns ratio of the transformers 24 and 25 are such that the amplitudes of the switching control signals S5 and S6 are equal to or higher than the gate cutoff voltage (about 4 V) of the second FET 15 and the third FET 16. The gate-source voltage is set to a predetermined voltage that is not higher than the absolute maximum rating (about 20 V).

  Next, the overall operation of the switching power supply device 1 will be described with reference to the drawings. In order to facilitate understanding of the invention, it is assumed that the switching power supply device 1 is in an operating state in which a constant voltage Vin is input from the electric double layer capacitor 2 and a constant output voltage Vo is output.

  In this operation state, the switching control circuit 22 outputs the switching control signal S1 to the gate terminal of the first FET 12 at a predetermined duty ratio (ratio determined by the voltage Vin, the output voltage Vo, and the turn ratio of the transformer 11). The first FET 12 repeats the on state and the off state in synchronization with the switching control signal S1. The switching control circuit 22 outputs a switching control signal S2 having a polarity opposite to that of the switching control signal S1 to the gate terminal of the fourth FET 14a, so that the fourth FET 14a is turned on in synchronization with the switching control signal S2. Is turned off, and turned on when the first FET 12 is turned off.

  In this case, in the ON period in which the first FET 12 is in the ON state, the fourth FET 14a is in the OFF state, and the current resulting from the voltage Vin flows into the primary winding 11a, whereby the AC voltage Vs is applied to the secondary winding 11b. Is induced with the polarity shown in FIG. In addition, during the ON period of the first FET 12, the switching control signal S1 is output to the second FET 15 as the switching control signal S5 through the buffer circuit 23 and the transformer 24 with the polarity unchanged and the amplitude being substantially constant. The switching control signal S2 is output to the second FET 16 as the switching control signal S6 through the buffer circuit 23 and the transformer 25 with the polarity as it is and the amplitude being substantially constant. As a result, the second FET 15 is turned on and the third FET 16 is turned off. Therefore, during the ON period of the first FET 12, the load 41 connected to the output terminals 19a and 19b, the primary winding 17a of the transformer 17, and the second FET 15 (and the diode 15a) are connected from the secondary winding 11b of the transformer 11. A current I1 flows through a path that passes back to the secondary winding 11b, and an output voltage Vo is applied to the load 41.

  On the other hand, in the off period in which the first FET 12 is in the off state, the inflow of current to the primary winding 11a is stopped, so that a counter electromotive force is generated in the primary winding 11a and an AC voltage is applied to the secondary winding 11b. A voltage having a polarity opposite to that of Vs is induced. At this time, since the fourth FET 14a is in the on state, the energy accumulated in the primary winding 11a is once moved to the capacitor 14b of the clamp circuit 14 and the parasitic capacitance Cs between the source and drain terminals in the first FET 12, Thereafter, the electric double layer capacitor 2 is regenerated through the fourth FET 14a in the ON state. Therefore, the counter electromotive force generated in the primary winding 11a, and hence the voltage induced in the secondary winding 11b, is suppressed (clamped) by the clamp circuit 14. In the off period of the first FET 12, the switching control signals S1 and S2 have the same polarity and the amplitude is substantially constant via the buffer circuit 23 and the transformers 24 and 25, as in the on period. In this state, the switching control signals S5 and S6 are output to the FETs 15 and 16, respectively. As a result, the second FET 15 is turned off and the third FET 16 is turned on. Therefore, due to the energy accumulated in the primary winding 17a during the ON period of the first FET 12, the current I2 is commutated to the load 41 through the third FET 16 in the ON state as shown in FIG. 1, and the output voltage Vo is applied to the load 41. Applied. In this case, the voltage V1 generated between the both ends of the primary winding 17a in the transformer 17 is in a state where the amplitude thereof substantially coincides with the output voltage Vo.

  In this way, even when the voltage Vin of the electric double layer capacitor 2 changes in a state where the switching power supply device 1 is applying the output voltage Vo to the load 41, the switching control circuit 22 changes the voltage Vin. By detecting a minute change in the DC voltage V3 accompanying the control and controlling the duty ratio of the switching control signals S1 and S2, the fluctuation of the output voltage Vo is suppressed within a preset voltage range, and the load 41 is applied. The applied output voltage Vo is maintained almost constant. As a result, as described above, the voltage V1 generated in the primary winding 17a of the transformer 17 and the DC voltage V3 generated based on the voltage V1 are also maintained at a substantially constant voltage. As a result, regardless of the change in the voltage Vin of the electric double layer capacitor 2, the amplitude of each switching control signal S1, S2 output from the switching control circuit 22 that operates using the DC voltage V3 as a power source, the switching control signal S1, The amplitudes of the switching control signals S3, S4, S5 and S6 generated based on S2 are also maintained substantially constant. Therefore, even if the voltage Vin of the electric double layer capacitor 2 changes, the voltage between the source and gate terminals of the second FET 15 and the third FET 16 is not less than a preset gate cut-off voltage and the absolute maximum of the gate-source voltage. It is maintained at a predetermined voltage below the rating.

  As described above, in this switching power supply device 1, the switching control circuit 22 operates by using the stabilized DC voltage V 3 generated by rectifying and smoothing the AC voltage V 2 induced in the secondary winding 17 b of the transformer 17 as a power source. Thus, switching control signals S5 and S6 for the second FET 15 and the third FET 16 are generated. Therefore, according to the switching power supply device 1, the amplitude of the switching control signals S5 and S6 for the second FET 15 and the third FET 16 can be maintained substantially constant. As a result, the gate cut-off is achieved regardless of the fluctuation of the voltage Vin of the electric double layer capacitor 2. The second FET 15 and the third FET 16 can be stably operated by outputting the switching control signals S5 and S6 having an amplitude that is equal to or higher than the voltage and lower than the absolute maximum rating of the gate-source voltage.

  In the switching power supply device 1, the switching control signals S 1 and S 2 output from the switching control circuit 22 are output to the second FET 15 and the third FET 16 while being electrically insulated by the transformers 24 and 25. Therefore, according to this switching power supply device 1, unlike the configuration of electrically insulating using a photocoupler, it is possible to improve aging, responsiveness, and environmental resistance. Can be achieved. It should be noted that the use of a photocoupler is not excluded, and it is needless to say that a photocoupler may be used instead of each of the transformers 24 and 25.

  In addition, according to the switching power supply device 1, since the clamp circuit 14 having the fourth FET 14a and the capacitor 14b and connected in parallel to the primary winding 11a of the transformer 11 is provided, the primary winding 11a and the second winding 11a of the transformer 11 are provided. Since the voltage of the secondary winding 11b can be limited and the third FET 16 for passing the commutation current can be turned on over the entire period in which the first FET 12 is turned off, the loss is reduced and the efficiency is reduced. Can be improved.

  Further, in this switching power supply device 1, each complementary emitter follower circuit 31, 32 of the buffer circuit 23 receives each switching control signal S 1, S 2 output from the switching control circuit 22 and each switching for the second FET 15 and the third FET 16. Output as control signals S3 and S4. Therefore, according to the switching power supply device 1, for example, the switching control signals S3 and S4 are further converted into the switching control signals S5 and S6 via the transformers 24 and 25 and output to the second FET 15 and the third FET 16. However, since the transformers 24 and 25 can be sufficiently driven with low impedance, the amplitudes of the switching control signals S5 and S6 can be stabilized. As a result, the second FET 15 and the third FET 16 can be reliably turned on / off. it can.

  In addition, this invention is not limited to above-described embodiment, The structure can be changed suitably. For example, in the switching power supply device 1 according to the embodiment of the present invention, as shown in FIG. 1, the second FET 15 is disposed on the winding end side of the secondary winding 11b. You may arrange | position to the winding start side of 11b. Similarly, the primary winding 17a of the transformer 17 may be disposed on the winding start side of the secondary winding 11b. Further, although the example in which the reset of the transformer 11 in the forward type DC / DC converter 3 is performed using the clamp circuit 14 has been described above, a configuration using a reset winding may be employed. Further, the preferred example in which the complementary emitter follower circuits 31 and 32 with a small signal delay are employed to configure the buffer circuit 23 has been described above. However, the buffer circuit 23 may be configured using an operational amplifier that operates using the DC voltage V3 as a power source.

1 is a circuit diagram of a switching power supply device 1 according to an embodiment of the present invention. 3 is a circuit diagram of a buffer circuit 23 and transformers 24 and 25. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Switching power supply device 2 Electric double layer capacitor 11 Transformer 11a Primary winding 11b Secondary winding 12 1st FET
14 Clamp circuit 14a 4th FET
14b capacitor 15 second FET
16 3rd FET
17 Transformer 17a Primary winding 17b Secondary winding 18 Capacitor 20 Diode 21 Capacitor 22 Switching control circuit 24, 25 Transformer 31, 32 Complementary emitter follower circuit S1, S2, S5, S6 Switching control signal V2 AC voltage V3 DC voltage Vin input Voltage

Claims (3)

An electric double layer capacitor;
A first transformer having a primary winding and a secondary winding;
A first switching element connected in series to the primary winding and periodically switching an input voltage supplied from the electric double layer capacitor;
A rectifying / smoothing circuit configured by connecting in series a second switching element for synchronous rectification, a smoothing inductor, and a smoothing storage element, and connected between both ends of the secondary winding;
A third switching element for passing commutation current connected in parallel to a series circuit of the inductor and the smoothing storage element;
A detection coil magnetically coupled to the smoothing inductor;
A voltage generation circuit for generating a DC voltage by rectifying and smoothing an AC voltage induced in the detection coil;
A switching control circuit that operates using the DC voltage as a power source to control the switching of the first switching element and generate and output control signals for the second switching element and the third switching element; Switching power supply. A second transformer that outputs to the second switching element while electrically insulating the control signal for the second switching element output from the switching control circuit;
2. The switching power supply device according to claim 1, further comprising: a third transformer that outputs to the third switching element while electrically insulating the control signal for the third switching element output from the switching control circuit.   A power storage element and a fourth switching element connected in series are connected in parallel to the primary winding, and the fourth switching element is controlled to be off when the first switching element is on, and 3. The switching power supply device according to claim 1, further comprising a clamp circuit controlled to be turned on when one switching element is turned off.

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