JP2008245273A - Symbol synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a symbol synchronizing circuit preventing an increase in clock phase deviation due to a temperature change or the like using a single synchronization circuit system. <P>SOLUTION: The symbol synchronizing circuit has a back stage number determining unit 104, and obtains a left end signal 109 and a right end signal 110 from a variable delay unit 101. The left end signal 109 and the right end signal 110 are signals that are obtained by delaying a clock signal 107 by the different number of delay stages. The number of delay stages means the number of delay elements through which the clock signal 107 is passed for delaying. The back stage number determining unit 104 calculates, as a back stage number, a difference in the number of delay stages between the left end signal 109 and the right end signal 110 when a phase difference between the left end signal 109 and the right end signal 110 is closest to a value obtained by multiplying a clock cycle by a natural number. A cyclic control unit 103 performs a back process, based on the number of stages indicated by the back stage number determining unit 104. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention dynamically synchronizes and synchronizes the timing with the data signal by dynamically controlling the delay of the clock signal on the receiving side in a transmission system that transmits and receives data between a plurality of devices operating with different clock sources. The present invention relates to a symbol synchronization circuit for identifying data based on a clock signal.

  FIG. 27 is a block diagram showing a conventional symbol synchronization circuit. The symbol synchronization circuit shown in FIG. 27 includes two synchronization circuits. When the control value for controlling the delay of the clock signal exceeds the limit value, the variable synchronization device is controlled by switching to another synchronization circuit. It operates so as not to exceed the range (see, for example, Patent Document 1).

  The symbol synchronization circuit dynamically controls the delay of the clock signal so that one of the first and second synchronization clocks is synchronized with the data signal. When the first synchronization clock 11 is synchronized with the data signal 10, the selection unit 13 selects the first synchronization clock 11 and outputs it as the selection clock 14. When the first synchronization clock 11 exceeds the limit value of the delay control, the second synchronization clock 12 is controlled to synchronize with the data signal 10 at a phase advanced from the first synchronization clock 11. When the second synchronization clock 12 is synchronized with the data signal 10, the selection unit 13 selects the second synchronization clock 12 and outputs it as the selection clock 14. When the second synchronization clock 12 exceeds the limit value of the delay control, switching from the second synchronization clock 12 to the first synchronization clock 11 is performed in the same procedure. Thereafter, the switching process is alternately repeated from the first synchronous clock 11 to the second synchronous clock 12 and from the second synchronous clock 12 to the first synchronous clock 11 again.

  FIG. 28 is a block diagram showing a conventional symbol synchronization circuit using a delay locked loop circuit. The symbol synchronization circuit shown in FIG. 28 operates so as not to exceed the control range of the variable delay device by using a single synchronization circuit and controlling the delay control value to circulate (see, for example, Patent Document 2). ). The symbol synchronization circuit is a delay locked loop circuit for acquiring the frequency and phase of the clock signal. However, those skilled in the art can easily use the symbol synchronization circuit as a symbol synchronization circuit with simple modifications. I can think of it.

  FIG. 29 is a state transition diagram showing the operation of the cyclic control means 21 provided in the symbol synchronization circuit shown in FIG. The cyclic control means 21 controls the variable delay device 22 so that the phase difference between the data signal 20 and the synchronous clock signal 23 is minimized. A number written in each state node shown in FIG. 29 indicates a delay control value of the variable delay device 22. In the example shown in FIG. 29, the control range of the variable delay device 22 is 0 to 7. The input / output delay time of the variable delay device 22 is equal to a value obtained by multiplying the unit delay time by the delay control value.

  A method for updating the delay control value will be described below. When the phase of the synchronous clock signal 23 is advanced compared to the data signal 20, the delay control value is increased by 1. When the phase of the synchronous clock signal 23 is delayed compared to the data signal 20, the delay control value is decreased by 1. When there is no phase difference between 20 and the synchronous clock signal 23, the delay control value is not changed. However, when the current delay control value is 0 or 7, when the control is performed in the direction exceeding the limit value, an 8-stage return process is performed. That is, when the delay amount is further increased from the delay control value 7, if it is simply increased by 1, it becomes 8 and exceeds the limit value of 7. Accordingly, the number of return stages 8 is subtracted from 8 increased by 1 to obtain 0. On the other hand, when the delay amount is further reduced from the delay control value 0, if it is simply reduced by 1, it becomes −1 and exceeds the limit value 0. Therefore, it is set to 7 by adding 8 of the number of steps back to −1 increased by 1. Thus, as shown in FIG. 29, it is possible to perform cyclic control by connecting 0 and 7, which are controllable ends, into a ring. The return time is equal to a value obtained by multiplying the unit delay time of the variable delay device 22 by the number of return stages. The number of return stages is designed to be the same as long as the return time and the natural number times the clock period can be obtained. As an internal configuration of the variable delay device 22, delay elements are connected in multiple stages, and an output of an arbitrary element is selected by a selector and output.

Japanese Patent No. 3001836 Japanese Patent No. 3564392

  However, since the symbol synchronization circuit shown in FIG. 27 includes two synchronization circuits, the circuit scale becomes large. In addition, the symbol synchronization circuit shown in FIG. 28 has only one synchronization circuit, but the return time is far from a natural number times the clock period due to a variation in the delay time of the delay element due to a temperature change or the like, The clock phase shift at the moment when the return process is performed increases.

  An object of the present invention is to provide a symbol synchronization circuit that has a single synchronization circuit and can prevent an increase in clock phase shift due to temperature change or the like.

  The present invention includes a data identification unit, a variable delay unit, a phase comparator, a cyclic control unit, and a return stage number determination unit, and determines the stage number Nc specified by the delay control signal output from the cyclic control unit. The number of left end signals output from the variable delay device is set to an integer of 1 or more, i is set to an integer of 1 to k, and Nl (i) is an integer of 0 or more. The signal number m of the right end signal output from the delay unit is an integer of 1 or more, j is an integer of 1 or more and m or less, Nr (j) is an integer of 0 or more, and for all i and j, Nl (I) <Nr (j), D is a unit delay time of a delay element included in the variable delay device, and the variable delay device converts the clock signal to Nc × based on the number of stages Nc specified by the delay control signal. A synchronous clock signal delayed by D is output and the clock signal is output. Is delayed by Nl (i) × D as the left end signal, the clock signal is delayed by Nr (j) × D as the right end signal, and the phase comparator Detecting a phase difference between the signal and the synchronous clock signal, and outputting a phase difference signal corresponding to the detection result, and the cyclic control unit converts the synchronous clock signal into the data signal based on the phase difference signal. The delay control signal designating the number of stages Nc to be synchronized is output, and based on the return stage number signal output from the return stage number determination unit, a return process is performed so as not to exceed the control range of the variable delay device, and the return stage The number-of-stage determining unit is a combination of (i, j) in which the phase difference Nr (j) × D−Nl (i) × D between the left end signal and the right end signal is closest to a time that is a natural number multiple of the clock cycle. , Jmin) And outputting the return stage number signal indicating the difference Nr (jmin) −Nl (imin) between the number of stages of the left end signal and the right end signal at that time, and the data identifying unit is configured to output the return stage number signal based on the timing of the synchronous clock signal. A symbol synchronization circuit for identifying a value of a data signal and outputting an identification data signal is provided.

  This symbol synchronization circuit has only one synchronization circuit, adjusts the number of return stages according to the variation of the delay amount of the delay element, and selects the number of return stages closest to the time that is a natural number times the clock period. In this case, the clock phase shift is prevented from increasing due to environmental fluctuations such as temperature. It should be noted that the phase difference is calculated in parallel for the left end signal and the right end signal at the same time, and it is not limited whether the phase difference is calculated while sequentially switching with the selector.

  In the symbol synchronization circuit, the return stage number determination unit includes k × m phase comparators to simultaneously detect the phase differences between all the left end signals and the right end signals.

  In the above configuration, since the phase difference between the right end signal and the left end signal is calculated at the same time, the control is simple because it is not necessary to switch the right end signal and the left end signal one by one.

  The symbol synchronization circuit includes a mode switching unit that outputs a mode switching signal based on the return stage number signal and the delay control signal, and the return stage number determination unit is instructed to execute the return process by the mode switching signal. The patrol control unit is controlled so that the return process is performed only when the

  In the above configuration, the operation is performed with low power consumption.

  In the symbol synchronization circuit, the variable delay unit selects any one of the k left end signals selected from the left selected signal and the m right end signals selected. The return stage number determination unit has one phase comparator that sequentially detects a phase difference between the selected left end signal and the selected right end signal.

  In the configuration described above, the phase difference is calculated while the pair of the left end signal and the right end signal is sequentially switched by the selector. However, even when the number of return stage candidates is large, one phase comparator for left end / right end comparison is provided. It is enough. When k = 1, the selected left end signal is the left end signal itself, and when m = 1, the selected right end signal is the right end signal itself.

  In the symbol synchronization circuit, the return stage number determination unit only selects a signal corresponding to a transmission rate indicated by a rate switching signal indicating a transmission rate of the data signal from the k left end signals and the m right end signals. And the return stage number signal indicating the difference in the number of stages of the selected left end signal and right end signal is output.

  In the above configuration, since only the left end signal and the right end signal which are possible for the transmission rate of the data signal are selected and the number of return stages is calculated, unnecessary calculation can be omitted.

  In the symbol synchronization circuit, the mode switching signal indicates an operation mode of either a synchronization mode or an adjustment mode, and the phase comparator is configured to output the data when the synchronization mode is indicated by the mode switching signal. A first phase difference signal indicating a phase difference between the signal and the synchronous clock signal, and a second phase difference indicating the phase difference between the left end signal and the right end signal when the adjustment mode is instructed by the mode switching signal. The return stage number determining unit does not operate according to the first phase difference signal, the cyclic control unit operates, and the cyclic control unit operates according to the second phase difference signal. The control unit does not operate, and the return stage number determination unit operates.

  In the above configuration, one phase comparator may be provided in the entire symbol synchronization circuit.

  In the symbol synchronization circuit, the phase comparator includes a waveform converter that converts either the left end signal or the right end signal, which is a rectangular wave, into a signal having a waveform having a voltage peak.

  The above configuration can be realized even if the phase comparator extracts the timing from the voltage level of the data signal input by processing the flat portion of the rectangular wave into a mountain shape or a valley shape with LPF or the like.

  The symbol synchronization circuit includes a temperature table unit that converts the return stage number signal and outputs a temperature information signal.

  In the above configuration, a temperature information signal for correcting the characteristics of a circuit that is incorporated in the same semiconductor chip as the symbol synchronization circuit and whose characteristics fluctuate due to a temperature change can be output.

  According to the symbol synchronization circuit of the present invention, the synchronization circuit is one system, and an increase in clock phase shift due to a temperature change or the like can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a symbol synchronization circuit of the first embodiment. As shown in FIG. 1, the symbol synchronization circuit of the first embodiment includes a data identification unit 100, a variable delay unit 101, a phase comparator 102, a cyclic control unit 103, and a return stage number determination unit 104. . Reference numeral 105 shown in FIG. 1 is a data signal, reference numeral 106 is an identification data signal, reference numeral 107 is a clock signal, reference numeral 108 is a synchronous clock signal, reference numeral 109 is a left end signal, reference numeral 110. Is a right end signal, reference numeral 111 is a delay control signal for instructing the delay amount to the variable delay device 101, reference numeral 112 is a return stage number signal for instructing the number of return stages to the cyclic controller 103, and reference numeral 113 is a position signal. It is a phase difference signal.

  The variable delay device 101 delays the clock signal 107 and outputs a synchronous clock signal 108. The data identification unit 100 identifies the value of the data signal 105 based on the timing of the synchronous clock signal 108 and outputs it as the identification data signal 106. The phase comparator 102 detects the phase difference between the data signal 105 and the synchronous clock signal 108, and the phase difference signal 113 according to the detection result of whether the phase of the synchronous clock 108 is ahead or behind the phase of the data signal 105. Is output.

  The cyclic control unit 103 increases or decreases the value of the delay control signal 111 based on the phase difference signal 113, and synchronizes the synchronization clock 108 and the data signal 105. The cyclic control unit 103 performs a return process based on the return stage number signal 112 so as not to exceed the control range of the variable delay device 101.

  The left end signal 109 and the right end signal 110 are signals obtained by delaying the clock signal 107 by different numbers of delay stages. The number of delay stages means the number of delay elements when one or a plurality of delay elements are passed to delay the clock signal 107. The return stage number determination unit 104 calculates the difference in delay stage number between the left end signal 109 and the right end signal 110 when the phase difference between the left end signal 109 and the right end signal 110 is closest to a time that is a natural number times the clock period. The cyclic control unit 103 is instructed as the return stage number signal 112.

  FIG. 2 is a block diagram showing the internal configuration of the variable delay device 101 and the return stage number determination unit 104. Reference numeral 200 shown in FIG. 2 is a delay device in which eight stages of delay elements are cascade-connected. Reference numeral 201 denotes a selector that has an 8-bit input line and a 1-bit output line, and selects and outputs one of the 8-bit inputs according to the value indicated by the delay control signal 111. Reference numeral 202 denotes a phase comparator that outputs the magnitude of the phase difference between the left end signal 109 and the right end signal 110. R1, R2 and R3 are each bit signal of the right end signal 110. P 1, P 2 and P 3 are phase comparison signals output from the phase comparator 202. The subscripts 1, 2, and 3 indicating the right end signal 110 and the subscripts 1, 2, and 3 indicating the phase comparison signal correspond to each other. It corresponds to the eye, the 7th stage, and the 8th stage. A minimum detection unit 203 compares the values of the phase comparison signals P 1, P 2, and P 3, and connects the line of the right end signal 110 determined to have the minimum phase difference to the left end signal 109 to the delay device 200. The set position is output as a return stage number signal 112.

  FIG. 3 is a diagram showing an input / output table showing the operation of the minimum detection unit 203 in the return stage number determination unit 104. When the phase comparison signal P1 is the minimum with respect to the input phase comparison signals P1, P2, and P3, R1 is connected to the sixth stage of the delay device 200, so “6” is output as the return stage number signal 112. The Similarly, “7” is output as the return stage number signal 112 when the phase comparison signal P2 is minimum, and “8” is output as the return stage number signal 112 when the phase comparison signal P3 is minimum. Note that the phase comparison signal P1 and the phase comparison signal P2 may be minimized simultaneously, or the phase comparison signal P2 and the phase comparison signal P3 may be minimized simultaneously. In this embodiment, the same value “7” as that when the phase comparison signal P2 is minimum is output as the return stage number signal 112, but “6” is returned when the phase comparison signal P1 and the phase comparison signal P2 are simultaneously minimum. Even if it is output as the stage number signal 112, “8” may be output as the return stage number signal 112 when the phase comparison signal P2 and the phase comparison signal P3 are simultaneously minimized. That is, either of the number of stages of the delay device 200 to which the two right-most signals that are minimized at the same time are connected may be output.

  Further, in this embodiment, the phase comparator 202 outputs the magnitude of the phase difference between the left end signal 109 and the right end signal 110, but whether the phase of the right end signal 110 is advanced or delayed with respect to the left end signal 109. The determination result may be output. However, in that case, the minimum detection unit 203 outputs, as the return stage number signal 112, the position where the right end signal 110 of the position where the determination result changes in the phase comparison signals P1, P2, and P3 is connected.

  FIG. 4 is a state transition diagram showing the operation of the patrol control unit 103. The numbers “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7” written in each state node shown in FIG. The value of the delay control signal 111 for setting the delay is shown. Reference numerals 400u and 400d are return paths when the number of return stages is 6, reference numerals 401u and 401d are return paths when the number of return stages is 7, and reference numerals 402u and 402d are return paths when the number of return stages is eight. . Of the three types of return paths, only the return path indicated by the return stage number signal 112 is used, and the other return paths are not used. For example, when the return stage number signal 112 is 6, only the return paths 400u and 400d are valid, and the return paths 401u and 401d and the return paths 402u and 402d are invalid. In this case, only six states of “0”, “1”, “2”, “3”, “4”, and “5” are used, and states “6” and “7” are not used. . As another example, when the return stage number signal 112 is 8, only the return paths 402u and 402d are valid, the return paths 400u and 400d and the return paths 401u and 401d are invalid, and all eight states are included. Is used.

  A method for updating the delay control value when the return stage number signal 112 is 6 will be described below. When the phase of the synchronous clock signal 108 is advanced compared to the data signal 105, the delay control value is increased (up) by one. When the phase of the synchronous clock signal 108 is delayed compared to the data signal 105, the delay control value is increased. When the data signal 105 and the synchronous clock signal 108 have no phase difference, the delay control value is not changed (hold). Since the number of return stages is 6, the delay control range is 0 to 5. For this reason, when the delay amount is further increased from the delay control value 5, if it is simply increased by 1, it becomes 6 and exceeds the limit value of 5. Therefore, the return stage number 6 is subtracted from 6 increased by 1 to obtain 0. On the other hand, when the delay amount is further reduced from the delay control value 0, if it is simply reduced by 1, it becomes −1 and exceeds the limit value 0. Therefore, it is set to 5 by adding 6 as the number of steps to −1 increased by 1. Thus, as shown in FIG. 4, it is possible to cyclically control the return paths 400u and 400d by connecting the controllable ends 0 and 5 into a ring.

  FIG. 5 is a timing chart showing the relationship between the left end signal 109 and the right end signal 110 output from the variable delay device 101. Each clock edge waveform of case 1 to case 3 indicates the rising edge of the clock signal output from each stage of the delay device 200, and the interval between adjacent edges differs for each case. The interval between the edges is determined by the delay time per delay element. Such a difference in delay time of the delay elements is caused by a difference in conditions such as ambient temperature, operating voltage, and variations in semiconductor processes. Here, in Case 1, the timing of R1 of the right end signal 110 coincides with the clock edge after one cycle of the left end signal 109. Further, in case 2, R2 of the right end signal 110 coincides with the clock edge of one cycle after the left end signal 109 in R3 of the right end signal 110 in case 3.

  For example, in case 1, since the phase comparison signal P1 is the smallest of the three phase comparison signals, the minimum detection unit 203 outputs “6” as the value of the number of return stages from the table shown in FIG. At this time, as the return path of the patrol control unit 103, the return paths 400u and 400d in FIG. 4 are used.

  FIG. 6 is a diagram illustrating an example of the rising edge of the synchronous clock signal 108. The horizontal axis shown in FIG. 6 represents relative timing with respect to the data signal 105. As the waveform of the synchronous clock signal, the solid line arrow represents the rising edge of the synchronous clock signal with respect to the value of the specific delay control signal, and the specific value of the delay control signal corresponding to the solid line arrow is shown on the right side in the figure. Yes. A dotted arrow represents a rising edge when it is different from a specific value of the delay control signal. Furthermore, the numbers under each arrow represent the value of the delay control signal corresponding to each edge timing.

  The synchronous clock signal 1 in FIG. 6 corresponds to case 1 in FIG. 5, and the number of return stages that exactly matches one cycle of the clock is “6”. In the synchronous clock signal 1 shown in FIG. 6, the rising edge when the delay control signal = 0 indicated by the solid line arrow is delayed from the center of the symbol of the data signal 105 and is not optimal as the data identification timing, and is left one by one. The dotted arrow with the delay control signal = 5 located is closer to the center of the symbol. Therefore, in this case, the phase comparator 102 determines that the synchronous clock signal 108 is delayed, and outputs a phase difference signal 113 that instructs to reduce the delay to the cyclic control unit 103.

  According to the present embodiment, the return stage number determination unit 104 determines that the return stage number is “6”, and the traveling control unit 103 performs the return process based on the instructed return stage number “6”. Therefore, the value of the delay control signal is updated to 5, and the timing of the synchronous clock signal 108 approaches the center of the symbol (see the synchronous clock signal 2 in FIG. 6).

  As described above, the symbol synchronization circuit according to the present embodiment always monitors the phase difference from one clock cycle using the phase comparison signals P1, P2, and P2, and based on this phase difference, a plurality of return stage numbers. The number of return stages closest to one clock cycle is selected from the inside. For this reason, even if the delay time of the delay element changes due to a temperature change or the like, the return stage number closest to one clock cycle is selected, and the return process is performed based on the selected return stage number. On the other hand, in the symbol synchronization circuit shown in FIG. 28, since the number of return stages is fixed to “8”, for example, even if the delay time of the delay element changes due to a temperature change, etc. Not. If the return processing is performed on the synchronous clock signal 1 of FIG. 6 based on the return stage number “8”, the value of the delay control signal is updated from “0” to “7”, and the timing of the synchronous clock signal 108 is Further away from the center of the symbol of the data signal 105 (see the synchronous clock signal 3 in FIG. 6). Thus, the symbol synchronization circuit of this embodiment can prevent an increase in clock phase shift due to a change in environmental conditions such as a temperature change.

  In the present embodiment, as shown in FIG. 2, the number of delay elements included in the delay device 200 of the variable delay device 101 is 8. However, the number of delay elements is not limited to 8, and may be 9 or more and 7 or less. Further, the right end signal 110 is 3 bits of R1, R2, and R3, but is not limited to 3 bits. Further, although the left end signal 109 is 1 bit and the right end signal 110 is 3 bits, the left end signal may be a plurality of bits and the right end signal may be 1 bit. Further, both the left end signal and the right end signal may be a plurality of bits. In the present embodiment, the delay control value is updated with reference to FIG. 4. In the present embodiment, the delay control value is not changed (hold) when there is no phase difference between the clock signal 105 and the synchronization data signal 108. Is not necessarily a required operation, it may be just up and down.

(Second Embodiment)
FIG. 7 is a block diagram showing a symbol synchronization circuit of the second embodiment. The symbol synchronization circuit according to the second embodiment includes a return stage number determination unit 700 instead of the return stage number determination unit 104 included in the symbol synchronization circuit according to the first embodiment illustrated in FIG. 1, and further includes a mode switching unit 800. . Except for this point, the second embodiment is the same as the first embodiment. In FIG. 7, the same reference numerals are given to components common to FIG.

  Reference numeral 701 shown in FIG. 7 is a mode switching signal. The mode switching signal 701 instructs the return stage number determination unit 700 to calculate or hold the return stage number. The return stage number determination unit 700 has a mode for calculating the return stage number and a mode for holding the value of the return stage number, and operates in the mode instructed by the mode switching signal 701. The mode switching unit 800 outputs a mode switching signal 701 based on the delay control signal 111 and the return stage number signal 112.

  Hereinafter, the operation of the return stage number determination unit 700 according to the mode switching signal 701 will be described. When the variation in the delay time of the delay element in the variable delay device 101 is sufficiently slower than the operation speed of the return stage number determination unit 700, it is not necessary to always operate the return stage number determination unit 700. The operation of the return stage number determination unit 700 may be temporarily stopped for the purpose.

  Usually, the delay time of a semiconductor element is determined by the temperature of the element, the operating voltage, and process variations. Among them, the temperature of the element may be constantly changed during the operation of the symbol synchronization circuit because of the influence of changes in the outside air and heat generation of the entire device. In addition, the operating voltage varies depending on the design of the power supply circuit, and there is a possibility that the voltage varies during circuit operation due to the influence of power supply noise. Among these, fluctuations in power supply noise can be reduced by a power supply filter or a bypass capacitor. In a battery-driven device, the voltage changes as the remaining battery level changes, but the voltage can be made constant by a power supply regulator or a DC-DC converter. Further, the process variation does not affect the temporal variation of the delay time of the semiconductor element after the manufacture although there are individual differences in the semiconductor chip. Therefore, it is necessary to consider the influence of temperature change as a factor for varying the delay during circuit operation. However, the fluctuation speed of the delay time accompanying the temperature change is usually very slow compared with the operation of the circuit that calculates the number of return stages. For this reason, by setting the update cycle of the number of return stages to a period that can sufficiently follow the fluctuation of the delay time, it is possible to save power consumed for calculating the number of return stages. In order to determine the update cycle of the return stage number, the temperature may be changed within the range of the value determined by the specification under actual use conditions, and the change in the output value of the return stage number determining unit 700 may be observed. That is, if it takes T (seconds) to change the value of the return stage number by 1 no matter how fast the temperature is changed under actual use conditions, the return stage number update cycle is T (seconds) or less. Set to. Therefore, the mode switching signal 701 may be a pulse signal having a cycle of T (seconds) or less, and the return stage number determination unit 700 only needs to operate every time the pulse signal is input.

  The pulse period of the mode switching signal 701 is not always a constant period and may be varied. For example, the temperature rises immediately after the power is turned on or immediately after the start of data reception, and conversely, the temperature decreases immediately after completing a series of data reception and returning to the standby state. The mode switching signal 701 must be set in a period that follows without delaying the characteristic variation. However, the period may be lengthened in a state where the temperature change is small except for this case. Further, the temperature of the delay element may be measured, and the mode switching unit 800 may output the mode switching signal 701 when a temperature change occurs.

  The cyclic control means 103 performs the return process during the symbol synchronization operation, but does not perform the return process at the time of data standby or transmission. Therefore, the return stage number determination unit 700 may update the return stage number only immediately before the data identification is performed by inputting the data signal 105 to the data identification unit 100 without periodically updating the return stage number. For example, when the system synchronization circuit according to the present embodiment is applied to a transmission system in which a received data packet is composed of a preamble and data and a reception operation is started by carrier sense, the return stage number determination unit 700 performs post-carrier sense. When the preamble is received, the number of return stages may be updated, and the symbol synchronization pull-in operation may be performed.

  Further, the return stage number determination unit 700 does not always perform the return process during the symbol synchronization operation. Therefore, the return stage number determination unit 700 may not update the return stage number constantly during the symbol synchronization operation, but may update it only in an internal state in which the cyclic control unit 103 may perform the return process. The cyclic control unit 103 may execute the return process only when the state value is “0” shown in the state transition diagram of FIG. 4 or when the state value is 1 less than the value of the number of return stages. The internal state of the cyclic control unit 103 can be known from the value of the delay control signal 111.

  FIG. 8 is a block diagram showing an internal configuration of the return stage number determination unit 700. As shown in FIG. 8, the return stage number determination unit 700 includes a phase comparator 802, a minimum detection unit 203, and a latch 803. In FIG. 8, the same reference numerals are assigned to components common to FIG. 7.

  The phase comparator 802 outputs the phase difference between the left end signal 109 and the right end signal 110 only when the operation is instructed by the mode switching signal 701 from the mode switching unit 800, and when the stop is instructed by the mode switching signal 701. Stops operation and reduces power consumption. When the operation is instructed by the mode switching signal 701 from the mode switching unit 800, the latch 803 stores the value of the delay control signal when the minimum detection unit 203 detects the minimum phase difference, and the mode switching signal 701 When the stop is instructed, the value of the return stage number stored last is held.

  FIG. 9 is a block diagram showing input / output signals of mode switching section 800. FIG. 10 is a diagram showing an input / output table showing the operation of the mode switching unit 800. As shown in FIG. 10, the mode switching unit 800 instructs to switch to the operation mode when the value of the delay control signal 111 is 0 or equal to the value obtained by subtracting 1 from the value of the return stage number signal 112, In other cases, a mode switching signal 701 for instructing to switch to the stop mode is output. Therefore, the return stage number determination unit 700 operates only when the cyclic control unit 103 has a state value that may perform the return process in the state transition diagram shown in FIG.

  As described above, since the symbol synchronization circuit of this embodiment operates the return stage number determination unit 700 only when instructed by the mode switching signal 701, power consumption can be reduced.

(Third embodiment)
The symbol synchronization circuit of the third embodiment includes a variable delay device 1008 instead of the variable delay device 101 included in the symbol synchronization circuit of the first embodiment shown in FIG. A stage number determining unit 1001 is provided, and a 2-mode cyclic control unit 1005 is provided instead of the cyclic control unit 103. The return stage number determination unit 1001 and the two-mode cyclic control unit 1005 are supplied with a mode switching signal 1000 instructing either a synchronization mode for performing a symbol synchronization operation or an adjustment mode for updating the number of return stages. Except for this point, the second embodiment is the same as the first embodiment. In FIG. 11, the same reference numerals are given to the same components as those in FIGS. 1 and 2.

  FIG. 11 is a block diagram illustrating an internal configuration of the variable delay device 1008, the return stage number determination unit 1001, and the two-mode cyclic control unit 1005 included in the symbol synchronization circuit of the third embodiment. As shown in FIG. 11, the return stage number determination unit 1001 includes a phase comparator 1002, a minimum detection unit 1003, and a latch 1004. The variable delay device 1008 includes a delay device 200, a selector 201, and a selector equivalent delay device 1010.

  In the adjustment mode in which the return stage number is updated, the return stage number determination unit 1001 stores the value of the delay control signal 1007 when the phase difference between the left end signal 109 and the right end signal 1006 is the minimum as the return stage number. On the other hand, the return stage number determination unit 1001 outputs the return stage number signal 112 and stops the operations of the phase comparator 1002 and the minimum detection unit 1003 in the synchronization mode in which the symbol synchronization operation is performed.

  The phase comparator 1002 outputs a phase difference between the left end signal 109 and the right end signal 1006 in the adjustment mode, and stops operating in the synchronous mode. The minimum detection unit 1003 includes a memory 1053 that stores the minimum phase difference (the past minimum phase difference) among the phase differences input in the past from the phase comparator 1002. In the adjustment mode, the minimum detection unit 1003 transparently operates the latch 1004 when the currently input phase difference is smaller than the past minimum phase difference stored in the memory 1053, and conversely, When the phase difference is greater than or equal to the past minimum phase difference, the latch 1004 is held. In the synchronous mode, the minimum detection unit 1003 stops the operation while holding the latch 1004. When the minimum detection unit 1003 switches from the synchronous mode to the adjustment mode, the minimum detection unit 1003 initializes the past minimum phase difference value stored in the memory 1053 to 180 °.

  In the adjustment mode, the latch 1004 outputs the delay control signal 1007 input from the two-mode cyclic control unit 1005 as it is when a transmission operation is instructed from the minimum detection unit 1003. Further, the latch 1004 holds the value of the delay control signal 1007 that is finally input during the transmission operation when the holding operation is instructed from the minimum detection unit 1003.

  The two-mode cyclic control unit 1005 operates according to the state transition shown in FIG. 4 based on the phase difference signal 113 and the return stage number signal 112 in the synchronous mode. Further, in the adjustment mode, the 2-mode cyclic control unit 1005 makes a state transition from the state value “5” to “6” and then from the state value “6” to “7” shown in the state transition diagram of FIG. The value of the delay control signal 1007 corresponding to the extraction position of the signal 1006 is sequentially switched from “5” → “6” → “7” and supplied to the latch 1004, and the values “5” and “6” of the delay control signal 1007 are supplied. The variable delay device 1008 controls the clock signal having a phase corresponding to “7” to be sequentially output as the synchronous clock signal 1009. The synchronous clock signal 1009 is sequentially supplied to the phase comparator 1002 as a right end signal 1006 indicating three phase candidates in the adjustment mode, and is the same as the synchronous clock signal 108 shown in FIG. 2 in the synchronous mode.

  The variable delay device 1008 outputs a right end signal 1006 with one line. As described above, the right end signal 1006 is the synchronous clock signal 1009 output from the variable delay device 1008 in the adjustment mode. The selector equivalent delay device 1010 is a delay device having a delay amount equal to that of the selector 201.

  As described above, in the symbol synchronization circuit of this embodiment, even if the number of lines of the right end signal 1006 is one, the same function as that of the symbol synchronization circuit of the second embodiment can be realized. Further, since the number of lines of the right end signal 1006 is one, the return stage number determination unit 1001 may be provided with one phase comparator. As a result, the circuit scale does not increase even when the number of candidates for the number of return stages is large.

(Fourth embodiment)
The symbol synchronization circuit of the fourth embodiment includes a variable delay device 1105 instead of the variable delay device 101 included in the symbol synchronization circuit of the first embodiment shown in FIG. A stage number determination unit 1100 is provided, and a selection control unit 1103 is further provided. Except for this point, the second embodiment is the same as the first embodiment. In FIG. 12, the same reference numerals are given to the same components as those in FIGS. 1 and 2.

  FIG. 12 is a block diagram illustrating the internal configuration of the variable delay device 1105, the return stage number determination unit 1100, the cyclic control unit 103, and the selection control unit 1103 provided in the symbol synchronization circuit of the fourth embodiment. As illustrated in FIG. 12, the return stage number determination unit 1100 includes a phase comparator 1101, a minimum detection unit 1102, and a latch 1004. The variable delay device 1105 includes a delay device 200, a selector 201, a selector equivalent delay device 1010, and a right end selector 1006.

  The return stage number determination unit 1100 performs the same operation as the return stage number determination unit 1001 in the adjustment mode described in the third embodiment. The selection control unit 1103 performs the same operation as the two-mode cyclic control unit 1005 in the adjustment mode described in the third embodiment. The selection signal 1104 output from the selection control unit 1103 is the same signal as the delay control signal 1007 output from the two-mode cyclic control unit 1005 in the adjustment mode described in the third embodiment. Similar to the variable delay device 1008 described in the third embodiment, the variable delay device 1105 outputs the right end signal 1006 having the number of lines 1 through the right end selector 1106.

  As described above, the symbol synchronization circuit of this embodiment has the effect of the third embodiment in that the number of lines of the right-end signal 1006 is one and thus the increase in circuit scale associated with the number of return stage candidates can be suppressed. However, since it is not necessary to set the two modes (adjustment mode and synchronization mode) required in the third embodiment, the number of return stages can be updated simultaneously while performing the symbol synchronization operation.

(Fifth embodiment)
FIG. 13 is a block diagram showing a symbol synchronization circuit of the fifth embodiment. As shown in FIG. 13, the symbol synchronization circuit of the fifth embodiment includes a data identification unit 100, a variable delay unit 1206, a phase comparator 102, a cyclic control unit 1203, and a return stage number determination unit 1201. . Reference numeral 1209 shown in FIG. 13 is a data signal having a variable transmission rate, reference numeral 1205 is a clock signal having a frequency equal to the transmission rate of the data signal 1209, and reference numeral 1200 is a rate switching signal representing the transmission rate of the data signal 1209. Reference numeral 1202 is a return stage number signal, reference numeral 1204 is a right end signal, reference numeral 1205 is a clock signal, reference numeral 1207 is a delay control signal, and reference numeral 1208 is a synchronous clock signal.

  FIG. 14 is a block diagram showing the internal configuration of the variable delay device 1206 corresponding to two types of transmission rates. As shown in FIG. 14, the variable delay device 1206 includes a delay device 1300 in which 16 delay elements are cascade-connected, and a selector 1301. An upward arrow extending from the delay device 1300 represents a signal obtained by delaying the clock signal 1205 and is arranged from the left in the order of the number of delay elements that have been passed. The selector 1301 selects a signal indicated by the delay control signal 1207 from the 16 inputs and outputs it as a synchronous clock signal 1208. The right end signal 1204 is composed of 6 bits of R11, R12, R13, R21, R22, and R23. As for the extraction position of each bit of the right end signal 1204 from the delay device 1300, the bit R11 is the sixth stage, the bit R12 is the seventh stage, the bit R13 is the eighth stage, the bit R21 is the 14th stage, and the bit R22 is 15th. The stage, bit R23 is the 16th stage.

  FIG. 15 is a block diagram illustrating an internal configuration of the return stage number determination unit 1201 corresponding to two types of transmission rates. As shown in FIG. 15, the return stage number determination unit 1201 includes phase comparators 1400 and 1401, minimum detection units 1402 and 1403, and a selector 1404. The phase comparators 1400 and 1401 have the same function as the phase comparator 202 shown in FIG. 2 and output the magnitude of the phase difference between each bit of the left end signal 109 and the right end signal 1204. Reference signs P11, P12, and P13 shown in FIG. 15 are phase comparison signals output from the phase comparator 1400, and reference signs P21, P22, and P23 are phase comparison signals output from the phase comparator 1401.

  The minimum detection unit 1402 has the same function as the minimum detection unit 203 shown in FIG. 2 and compares the phase comparison signals P11, P12, and P13, and the line of the right end signal 1204 that minimizes the phase difference is the delay unit 1300. The position connected to is output. The minimum detection unit 1403 has basically the same function as the minimum detection unit 203 shown in FIG. 2, and compares the phase comparison signals P21, P22, and P23, and the line of the right end signal 1204 that minimizes the phase difference is obtained. The position connected to the delay device 1300 is output. However, since the positions of the corresponding right end signal 1204 lines connected to the delay device 1300 are the 14th stage, the 15th stage, and the 16th stage, the minimum detection unit 1403 has output values “14” and “15”. The difference is “16”. The selector 1404 selects a signal based on the type of rate displayed by the rate switching signal 1200. The rate switching signal 1200 indicates whether the current rate is high or low. The selector 1404 selects the output of the minimum detection unit 1402 for the high rate and outputs it as the return stage number signal 1202, and selects the output of the minimum detection unit 1403 for the low rate and outputs it as the return stage number signal 1202.

  FIG. 16 is a timing chart showing the operation of the return stage number determination unit 1201 in the case of a high rate, and FIG. 17 is a timing chart showing the operation of the return stage number determination unit 1201 in the case of a low rate. In FIG. 16, among the right end signals R11, R12, and R13, R12 has the smallest phase difference from the left end signal 109, so the minimum detection unit 1402 outputs a value “7” corresponding to R12. Further, since R21 has the smallest phase difference from the left end signal 109 among the right end signals R21, R22, and R23, the minimum detection unit 1403 outputs a value “14” corresponding to R21. When the transmission rate is high, the selector 1404 selects the output of the minimum detection unit 1402 and outputs “7” as the return stage number signal.

  On the other hand, in FIG. 17, among the right end signals R11, R12, and R13, R11 has the smallest phase difference from the left end signal 109, so the minimum detection unit 1402 outputs a value “6” corresponding to R11. Since the phase difference between the right end signals R21, R22, and R23 and the left end signal 109 is the smallest in R22, the minimum detection unit 1403 outputs the value “15” corresponding to R22. When the transmission rate is low, the selector 1404 selects the output of the minimum detection unit 1403 and outputs “15” as the return stage number signal.

  FIG. 18 is a state transition diagram showing the operation of the patrol control unit 1203 corresponding to two types of transmission rates. A number from 0 to 15 written in each state node shown in FIG. 18 indicates a value of the delay control signal 1207 for setting the delay of the variable delay device 1206. Reference numerals 1600u and 1600d are return paths when the number of return stages is 14, reference numerals 1601u and 1601d are return paths when the number of return stages is 15, and reference numerals 1602u and 1602d are return paths when the number of return stages is 16. . Of the six types of return paths, only the return path indicated by the return stage number signal 1202 is used, and the other return paths are not used. For example, when the return stage number signal is 7 as in the example shown in FIG. 16, only the return paths 401u and 401d are valid, and the remaining return paths are invalid. In this case, only a total of seven states “0” to “6” are used, and states “7” to “15” are not used. As another example, when the return stage number signal is 15 as in the example shown in FIG. 17, only the return paths 1601u and 1601d are valid, and the remaining return paths are invalid. In this case, only 15 states from “0” to “14” are used, and the state “15” is not used.

  As described above, the symbol synchronization circuit of this embodiment can execute the return process even if the transmission rate of the data signal 1209 is variable. In this embodiment, the transmission rate is of two types, low speed and high speed, but the number of right end signals 1204 extracted from the variable delay device 1206 and the phase comparators (1400, 1401) in the return stage number determination unit 1201 By increasing the number of minimum detection units (1402, 1403) and the number of inputs of selector 1404, a configuration corresponding to three or more types of transmission rates may be used.

(Sixth embodiment)
The symbol synchronization circuit of the sixth embodiment includes a return stage number determination unit 1702 instead of the return stage number determination unit 1001 provided in the symbol synchronization circuit of the third embodiment shown in FIG. A switchable phase comparator 1700 is provided. Except for this point, the third embodiment is the same as the third embodiment. In FIG. 19, the same reference numerals are given to components common to FIG. 11.

  FIG. 19 is a block diagram showing a symbol synchronization circuit of the sixth embodiment. Reference numeral 1701 in FIG. 19 is a phase difference signal, and reference numeral 1803 is a rectangular wave data signal. The return stage number determination unit 1702 has a configuration in which the phase comparator 1002 is removed from the return stage number determination unit 1001 illustrated in FIG.

  FIG. 20 is a block diagram showing a switchable phase comparator 1700 corresponding to a rectangular wave data signal 1803. As shown in FIG. 20, the switchable phase comparator 1700 includes selectors 1800 and 1801 and a phase comparator 1802. The selectors 1800 and 1801 are 2-input 1-output selectors that perform a selection operation in accordance with an instruction of the mode switching signal 1000. The selector 1800 outputs a data signal 1803 in the synchronous mode, and outputs a left end signal 109 in the adjustment mode. On the other hand, the selector 1801 outputs the synchronous clock signal 108 in the synchronous mode, and outputs the right end signal 1006 in the adjustment mode. The phase comparator 1802 compares the phases of the two input signals from the selectors 1800 and 1801 and outputs a phase difference signal 1701.

  In the synchronous mode, the phase comparator 1802 compares the data signal 1803 with the synchronous clock signal 108 and outputs the phase difference signal 1701, so the two-mode cyclic control unit 1005 returns based on the phase difference signal 1701. Processing is performed, and the return stage number determination unit 1702 does not operate. On the other hand, in the adjustment mode, the phase comparator 1802 compares the left end signal 109 and the right end signal 1006 and outputs the phase difference signal 1701, so the return stage number determination unit 1702 returns based on the phase difference signal 1702. The number of stages is determined, and the two-mode cyclic control unit 1005 does not operate.

  As described above, the symbol synchronization circuit of this embodiment corresponds to both the synchronous mode and the adjustment mode by the phase comparator 1802 in the switching type phase comparator 1700. There is no need to provide a phase comparator. For this reason, a smaller circuit scale can be realized.

(Seventh embodiment)
The symbol synchronization circuit of the seventh embodiment includes a switchable phase comparator 1900 instead of the switchable phase comparator 1700 provided in the symbol synchronization circuit of the sixth embodiment shown in FIG. The switchable phase comparator 1700 provided in the symbol synchronization circuit of the sixth embodiment is limited to the case where the data signal is a rectangular wave, but in the present embodiment, it corresponds to a data signal having a waveform with a Nyquist band limited. Except for this point, this embodiment is the same as the sixth embodiment. In FIG. 21, the same reference numerals are given to components common to FIG. 20.

  FIG. 21 is a block diagram showing a switchable phase comparator 1900 corresponding to a data signal having a waveform limited in the Nyquist band. Reference numeral 1904 in FIG. 21 is a data signal limited to the Nyquist band. As shown in FIG. 21, the switchable phase comparator 1900 includes a selector 1801, a low-pass filter (LPF) 1901, a switch 1902, and a phase comparator 1903.

  The LPF 1901 shapes the rectangular wave left end signal 109 into a mountain shape. Switch 1902 is a 2-input 1-output analog switch that performs a selection operation in accordance with an instruction of mode switching signal 1000. The switch 1902 outputs a data signal 1904 in the synchronous mode, and outputs an output signal of the LPF 1901 in the adjustment mode. The phase comparator 1903 calculates the phase difference between the output signal of the switch 1902 and the output signal of the selector 1801 based on the voltage level obtained by sampling the waveform of the output signal of the switch 1902 at the timing of the output signal of the selector 1801. Calculate and output as a phase difference signal 1701.

  As described above, in the symbol synchronization circuit of the present embodiment, the switchable phase comparator 1900 shapes the rectangular wave left end signal 109 into a mountain shape by the LPF 1901 and extracts the timing from the voltage level in the same manner as the data signal 1904. , And a phase comparator 1903 that treats the other as a digital signal. Therefore, the present invention can be applied to a case where the data signal is not a rectangular wave, for example, the signal 1904 limited to the Nyquist band.

(Eighth embodiment)
FIG. 22 is a block diagram showing a symbol synchronization circuit of the eighth embodiment. The symbol synchronization circuit of the eighth embodiment includes a temperature table unit 2000 in addition to the components included in the symbol synchronization circuit of the first embodiment. Reference numeral 2001 in FIG. 22 denotes a temperature information signal. The temperature table unit 2000 converts the return stage number signal 112 and outputs a temperature information signal 2001. The temperature table unit 2000 is incorporated in the same semiconductor chip as the symbol synchronization circuit. The temperature information signal 2001 is a signal used to correct circuit characteristics whose characteristics fluctuate due to temperature changes.

  In this embodiment, the temperature information signal 2001 is determined by inputting only the return stage number signal 112 in the temperature table 2000. However, the temperature information signal may be determined by inputting the return stage number signal 112 and the operating voltage information. . In this case, the symbol synchronization circuit of this embodiment is applied to a device whose operating voltage fluctuates at a sufficiently low speed compared to the operating speed of the return stage number determination unit, for example, a device whose operating voltage varies depending on the remaining battery level. be able to.

(Ninth embodiment)
FIG. 23 is a block diagram showing a symbol synchronization circuit of the ninth embodiment. The symbol synchronization circuit of the ninth embodiment includes a phase comparator 2301 instead of the return stage number determining means 104 included in the symbol synchronization circuit of the first embodiment. Reference numeral 2302 in FIG. 23 denotes a phase difference signal. The cyclic control unit 21 in FIG. 23 is the same as the cyclic control unit 21 in FIG. 28 showing a conventional symbol synchronization circuit, and is different from the cyclic control unit 104 provided in the symbol synchronization circuit of the first embodiment. . Reference numeral 2303 in FIG. 23 denotes a variable delay device, which has a function of continuously changing the delay time of the delay element provided therein according to the phase difference signal 2302 that is an analog signal (for details, see FIGS. 24 and 25). This will be described with reference to FIG. Reference numeral 2304 in FIG. 23 is a delay control signal. In FIG. 23, the same reference numerals are given to components common to those in FIGS. With the above configuration, the number of return stages is fixed as shown in FIG. 29 by continuously changing the delay time of the variable delay device so that the phase difference between the left end signal 109 and the right end signal 110 becomes small. However, it is possible to reduce the clock phase shift at the moment when the return processing is performed.

  FIG. 24 is a block diagram showing the internal configuration of the temperature variable delay device, which is an example of the variable delay device 2303 of this embodiment. Reference numeral 2401 in FIG. 24 is a temperature variable delay device, and reference numeral 2402 is a heat generator. Reference numeral 2403 denotes a heat conductor that transfers heat generated by the heat generator 2402 to the delay device 200. When the phase of the right end signal 110 is advanced as compared to the left end signal 109, the heat generator 2402 increases the amount of heat and increases the delay time of the temperature variable delay device 2401. On the contrary, when the phase of the right end signal 110 is delayed as compared with the left end signal 109, the heat generator 2402 reduces the amount of heat and decreases the delay time of the temperature variable delay device 2401.

  FIG. 25 is a block diagram showing the internal configuration of the voltage variable delay device, which is an example of the variable delay device 2303 of this embodiment. In FIG. 25, reference numeral 2501 denotes a voltage variable delayer, reference numeral 2502 denotes a variable voltage source, reference numeral 2503 denotes a power supply line, and reference numeral 2504 denotes a delayer. When the phase of the right end signal 110 is advanced compared to the left end signal 109, the variable voltage source 2502 decreases the voltage and increases the delay time of the voltage variable delay device 2501. Conversely, when the phase of the right end signal 110 is delayed compared to the left end signal 109, the variable voltage source 2502 increases the voltage and decreases the delay time of the voltage variable delay device 2501.

  FIG. 26 is a block diagram showing the internal configuration of the variable capacity delay device, which is an example of the variable delay device 2303 of this embodiment. In FIG. 26, reference numeral 2601 denotes a variable capacity delay device, reference numeral 2602 denotes a variable capacitor, and reference numeral 2603 denotes a delay device. When the phase of the right end signal 110 is advanced as compared with the left end signal 109, the capacitance of the variable capacitor 2602 is increased and the delay time of the variable capacitance delay device 2601 is increased. On the contrary, when the phase of the right end signal 110 is delayed as compared with the left end signal 109, the capacitance of the variable capacitor 2602 is reduced and the delay time of the variable capacitance delay device 2601 is decreased.

  The symbol synchronization circuit according to the present invention has a function of compensating for a change in the characteristics of the variable delay device due to a temperature change or the like and preventing an increase in the clock phase shift during the return process. It is useful as a synchronization circuit for data demodulation in a transmission apparatus. Further, it can be applied to applications such as temperature monitoring of a semiconductor on which a symbol synchronization circuit is mounted and generation of a correction reference signal for characteristic variation of other circuits.

Block showing the symbol synchronization circuit of the first embodiment The block diagram which shows the internal structure of a variable delay device and a return stage number determination part The figure which shows the input / output table which shows the operation of the minimum detection part in the return stage number decision part State transition diagram showing the operation of the patrol controller Timing diagram showing the relationship between the left and right end signals output from the variable delay device The figure which shows an example of the rising edge of a synchronous clock signal A block diagram showing a symbol synchronization circuit of a second embodiment Block diagram showing the internal configuration of the return stage number determination unit Block diagram showing input / output signals of the mode switching unit The figure which shows the input / output table which shows the operation of the mode change part The block diagram which shows the internal structure of the variable delay device and return stage number determination part with which the symbol synchronization circuit of 3rd Embodiment is provided. The block diagram which shows the internal structure of the variable delay device and return stage number determination part with which the symbol synchronization circuit of 4th Embodiment is provided. The block diagram which shows the symbol synchronization circuit of 5th Embodiment The block diagram which shows the internal structure of the variable delay device corresponding to two types of transmission rates The block diagram which shows the internal structure of the return stage number determination part corresponding to two types of transmission rates Timing chart showing the operation of the return stage number determination unit in the case of a high rate Timing chart showing the operation of the return stage number determination unit in the case of a low rate State transition diagram showing the operation of the cyclic controller corresponding to two types of transmission rates A block diagram showing a symbol synchronization circuit of a 6th embodiment Block diagram showing a switchable phase comparator for rectangular wave data signals Block diagram showing a switched phase comparator corresponding to a Nyquist band-limited waveform data signal The block diagram which shows the symbol synchronization circuit of 8th Embodiment A block diagram showing a symbol synchronization circuit of a ninth embodiment Block diagram showing the internal configuration of the variable temperature delay device Block diagram showing the internal configuration of the voltage variable delay device Block diagram showing the internal configuration of the variable capacity delay device Block diagram showing a conventional symbol synchronization circuit A block diagram showing a conventional symbol synchronization circuit using a delay locked loop circuit State transition diagram showing operation of cyclic control means provided in symbol synchronizing circuit shown in FIG.

Explanation of symbols

100 Data identification units 101, 1008, 1206, 2303 Variable delay units 102, 202, 802, 1002, 1101, 1400, 1401, 1802, 1903, 2301 Phase comparators 21, 103, 1203 Cyclic control units 104, 700, 1001, 1100, 1201 Return stage number determination unit 200, 1300, 2504, 2603 Delay devices 201, 1301, 1404, 1800, 1801 Selector 203, 1003, 1102, 1402, 1403 Minimum detection unit 800 Mode switching unit 803, 1004 Latch 1005 Two-mode cyclic Control unit 1006 Right end selector 1010 Selector equivalent delay unit 1053 Memory 1103 Selection control unit 1700 Switching type phase comparator 1901 Low pass filter (LPF)
1902 Switch 2000 Temperature Table 2401 Temperature Variable Delay 2402 Heater 2403 Heat Conductor 2501 Voltage Variable Delay 2502 Variable Voltage Source 2601 Capacitance Variable Delay 2602 Variable Capacitor

Claims (8)

A data identification unit, a variable delay unit, a phase comparator, a cyclic control unit, and a return stage number determination unit,
The stage number Nc specified by the delay control signal output from the cyclic control unit is an integer of 0 or more,
The signal number k of the leftmost signal output from the variable delay device is an integer of 1 or more, i is an integer of 1 to k, Nl (i) is an integer of 0 or more,
The signal number m of the right end signal output from the variable delay device is an integer of 1 or more, j is an integer of 1 or more and m or less, Nr (j) is an integer of 0 or more,
For all i and j, Nl (i) <Nr (j), D is the unit delay time of the delay element of the variable delay device,
The variable delay is
Based on the number of stages Nc specified by the delay control signal, a synchronous clock signal obtained by delaying the clock signal by Nc × D is output.
A signal obtained by delaying the clock signal by Nl (i) × D is output as the leftmost signal;
A signal obtained by delaying the clock signal by Nr (j) × D is output as the right end signal;
The phase comparator detects a phase difference between the data signal and the synchronous clock signal, and outputs a phase difference signal corresponding to the detection result,
The cyclic control unit outputs the delay control signal designating the number of stages Nc with which the synchronous clock signal is synchronized with the data signal based on the phase difference signal, and the return stage number signal output from the return stage number determining unit On the basis of the return processing so as not to exceed the control range of the variable delay device,
The return stage number determination unit is a combination of (i, j) in which a phase difference Nr (j) × D−Nl (i) × D between the left end signal and the right end signal is closest to a time that is a natural number times the clock period. (Imin, jmin) is determined, and the return stage number signal indicating the difference Nr (jmin) −Nl (imin) between the number of stages of the left end signal and the right end signal at that time is output,
The symbol identification circuit, wherein the data identification unit identifies the value of the data signal based on the timing of the synchronous clock signal and outputs an identification data signal. The symbol synchronization circuit according to claim 1,
2. The symbol synchronization circuit according to claim 1, wherein the return stage number determination unit includes k × m phase comparators for simultaneously detecting a phase difference between all the left end signals and the right end signals. The symbol synchronization circuit according to claim 1,
A mode switching unit that outputs a mode switching signal based on the return stage number signal and the delay control signal;
The symbol synchronization circuit, wherein the return stage number determination unit controls the cyclic control unit to perform the return process only when the execution of the return process is instructed by the mode switching signal. The symbol synchronization circuit according to claim 1,
The variable delay device is
a selected left end signal in which any one of the k left end signals is selected;
a right end signal selected from any one of the m right end signals is output;
The symbol synchronization circuit, wherein the return stage number determination unit includes one phase comparator that sequentially detects a phase difference between the selected left end signal and the selected right end signal. The symbol synchronization circuit according to claim 1,
The return stage number determination unit selects and selects only signals corresponding to the transmission rate indicated by the rate switching signal indicating the transmission rate of the data signal from the k left-end signals and the m right-end signals. A symbol synchronizing circuit that outputs the return stage number signal indicating a difference in the number of stages of the left end signal and the right end signal. The symbol synchronization circuit according to claim 3, wherein
The mode switching signal indicates an operation mode of either a synchronization mode or an adjustment mode,
The phase comparator is
When the synchronous mode is instructed by the mode switching signal, a first phase difference signal indicating a phase difference between the data signal and the synchronous clock signal is output,
When the adjustment mode is instructed by the mode switching signal, a second phase difference signal indicating a phase difference between the left end signal and the right end signal is output,
In response to the first phase difference signal, the return stage number determination unit does not operate, the cyclic control unit operates,
In accordance with the second phase difference signal, the cyclic control unit does not operate, and the return stage number determination unit operates. The symbol synchronization circuit according to claim 1,
The phase comparator includes a waveform converter that converts any one of the left end signal and the right end signal, which are rectangular waves, into a signal having a waveform having a voltage peak. The symbol synchronization circuit according to claim 1,
A symbol synchronization circuit comprising a temperature table unit for converting the return stage number signal and outputting a temperature information signal.

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