JPH09139731A - Transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the configuration circuit, to decrease the power consumption and to provide general-purpose performance to a transmitter by adopting flip- flop circuits for a clock replacement section and providing a phase control section to correct a delay produced on a transmission line. SOLUTION: A 1st equipment A1 is provided with a clock generating section 3 and a phase control section 4. A phase of a clock CLK2 applied to a 2nd equipment B2 is controlled to be led in response to a delay of a transmission line or the like. Then the phase of DAT3 from the 2nd equipment B2 to the 1st equipment A1 is in matching with a phase of an internal clock CLK1 of the 1st equipment A1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transmission between devices in a data transmission system or between LSIs in a device.

[0002]

2. Description of the Related Art A conventional data transmission apparatus will be described with reference to FIGS. FIG. 14 is a configuration diagram of a conventional transmission device, and FIG. 15 is an operation timing chart for explaining an operation state of this transmission device. The transmission device shown in FIG. 14 is configured by connecting a first device A1 and a second device B2 via a transmission path 7. First device A1
Supplies a clock signal to the second device B2, receives a data signal synchronized with the clock signal from the second device B2, and processes the data in the internal circuit.

The first device A1 includes a clock generator 3 and
Flip-flop 5, internal circuit 6, and delay addition circuit 1
It has 0 and a clock replacement unit 11. The second device B2 has a flip-flop 8 and an internal circuit 9. The clock signal outputs the reference clock signal CLK1 from the clock generation unit 3 in the first device A1, is supplied to the internal circuit 6, the delay addition circuit 10, and the clock replacement unit 11 of the first device A1 and is transmitted. It is fed to the second device B2 via line 7. As shown in FIG. 15, the second device B2 has a clock signal CLK delayed from the reference clock signal CLK1 by a time corresponding to the length of the transmission path 7.
3 is input and supplied to the internal circuit 9 and the data output flip-flop 8.

The data signal is generated as the data DAT1 in the internal circuit 9 of the second device B2, and the data signal DAT2 synchronized with the input clock signal CLK3 in the output flip-flop 8 is transmitted through the transmission line 7 to the first device. It is supplied to A1. The data signal DAT2 supplied from the second device B2 to the first device A1 is added with the delay in the transmission line 7 similarly to the clock signal, and is taken into the first device A1 as the input data signal DAT3. At this time, the clock signal CLK2 used in the data fetch flip-flop 5 in the first device A1 adds the delay in the round-trip transmission path 7 and the internal delay of the second device B2 to fetch the input data signal DAT3. The added delay amount must be added to the reference clock CLK1 by the delay adding circuit 10. The data signal DAT4 latched by the flip-flop 3 with the delayed clock signal CLK2 and taken into the first device A1 is re-timed by the reference clock signal CLK1 in the clock replacement unit 11 and data synchronized with the reference clock signal CLK1. The signal DAT5 is input to the internal circuit 6.

[0005]

In the conventional data transmission apparatus, a typical configuration is such that a clock for fetching data is generated on the side of the transmission apparatus A1 which receives the data. In this case, the fetched data is re-generated. You must retime with the same clock as the internal circuit. The clock replacement unit 11 for retiming ES (E lastic S tore)
However, there is a drawback that the circuit scale becomes large. Further, although it is possible to simply configure the clock replacing unit 11 by using a flip-flop, there is a disadvantage that it is difficult to manage the phases of the received data, the fetched clock, and the internal clock, and the versatility is lost. Further, in the conventional configuration, since the circuit scale is large, there is a problem that the power consumption of the entire device, the circuit area, etc. are inevitably large.

Therefore, the present invention realizes a reduction in the number of constituent circuits in the transmission device and a reduction in power consumption by correcting the delay generated on the transmission path by using a circuit having a simple structure, and also has versatility in the transmission device. The purpose is to have.

A further object of the present invention is to provide a clock phase control circuit capable of advancing the phase of the clock supplied to the data transmission side transmission device according to the delay on the transmission path. It is another object of the present invention to provide a clock phase control circuit that can change the phase of the supplied clock by using a clock that is faster than the clock supplied to the data transmission side transmission device.

[0008]

In order to solve the above problems, a data signal and a clock signal or a device for transmitting a clock signal, and a device for transmitting a data signal according to the clock signal In the transmission device that performs the above transmission, the clock transmission side device includes the delay correction unit that corrects the delay of the data signal generated on the transmission path.

As the data signal delay correcting means, a phase changing means for changing the phase of the clock signal is provided, and the delay of the data signal is reduced by advancing the phase of the clock signal on the transmitting side by these transmission delay amounts. The phase control means for correction is used.

The phase changing means for changing the phase of the clock signal is composed of a high-speed clock having a frequency higher than that of the clock signal to be transmitted and a flip-flop, and clock generating means for generating a plurality of transmitted clock signals having different phases, and a plurality of these clock generating means. The selection means selects the clock signal having the phase corresponding to the transmission delay from the clock signal.

As means for selecting the clock signal,
A means for detecting the phase difference between the data signal and the reference clock signal is provided, and the phase of the clock signal to be transmitted is switched based on this phase difference.

[0012]

With the clock phase control circuit capable of changing the phase of the clock supplied to the data transmission side transmission device,
Since the clock replacement unit in the data receiving side device is not necessary, the circuit scale of the transmission device can be reduced, and the power consumption, the circuit area, etc. can be reduced. Further, by using a clock that is faster than the clock supplied to the data transmission side transmission device, it is possible to always change the same amount of phase regardless of the delay variation of the clock phase control circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A transmission device according to the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a data transmission device according to the present invention. The first device A1 supplies a clock to the second device B2 and the second device B2
Supplies data to the first device A1 based on the clock. The first device A1 and the second device B2 are connected by a transmission line 7. The first device A1 includes a clock generation circuit 3, a phase control unit 4, a flip-flop 5, and an internal circuit 6. The second device B2 has a flip-flop 8 and an internal circuit 9, and has the same configuration as the conventional device.

In the first device A1, the reference clock signal CLK1 is generated by the clock generator 3 and the first device A1 is generated.
It is supplied to the internal circuit 6, the phase control unit 4, and the flip-flop 5. As shown in FIG. 2, an output clock signal CLK obtained by advancing the reference clock signal CLK1 by a predetermined amount.
2 is generated by the phase control unit 4. Output clock signal CLK
2 becomes the input clock signal CLK3 delayed by the transmission path 7 before reaching the second device B2. Second device B2
Then, the input clock signal CLK3 is supplied to the internal circuit 9, and the data DAT1 to be transmitted to the first device A1 is generated. The data DAT1 is retimed by the flip-flop 8 by the input clock signal CLK3,
The output data DAT2 is output from the second device B2.

The output data DAT2 is taken into the first device A1 through the transmission line 7, but the propagation delay in the transmission line 7 is added like the clock, and is input to the first device A1 as the input data DAT3. In the first device A1, the input data DAT3 is input to the same reference clock signal C as the internal circuit 6.
The data is taken into the flip-flop 5 by LK1, retimed, and input to the internal circuit 6 as data DAT4. Since the input data DAT3 is taken in by the reference clock signal CLK1 in the first device A1, the phase control unit 4
Has the function of advancing the phase of the output clock CLK2 and absorbing the transmission line delay and the internal delay of the second device B2.

This operation will be described with reference to the timing chart of FIG. By controlling the phase of the reference clock signal CLK1 generated by the first device A1, the phase is advanced and output as the output clock signal CLK2. Propagation delay is added to the output clock signal CLK2 on the transmission line, and the input clock signal CLK3 is supplied to the second device B2. The generated data DAT1 generated by the input clock signal CLK3 is latched (retimed) by the input clock signal CLK3, and is output as the second output data DAT2.
Output from the device B2. Propagation delay is added to the output data DAT2 in the transmission path in the same manner as the clock, and the output data DAT2 is fetched into the first device A1 as the input data DAT3.

At this time, since the output clock signal CLK2 whose phase is advanced in advance to allow for the transmission line delay and the internal delay of the second device B2 is used, the flip-flop 5 in the first device A1 uses the internal clock signal CLK2. It can be latched (captured) by the reference clock signal CLK1 which is a clock. In FIG. 2, the above flow is shown using the data D2 (shaded portion).

[0018]

EXAMPLE A concrete example of the clock generator 3 and the phase controller 4 in the first device A1 shown in FIG. 1 will be described with reference to FIGS. In FIG. 3, the clock generator 3 and the phase controller 4 are shown as one circuit. The clock generator 3 includes a clock source 50 and a counter.
And a shift register 51. Phase control unit 4
Is composed of a selector 52 which selects and outputs one from a plurality of outputs of the counter shift register 51.

From the clock source 50, the clock signal CLK
1, High-speed clock signal HCL with higher frequency than CLK2
K is supplied to the counter shift register 51. The counter / shift register 51 has a function of dividing a high-speed clock, and can generate a plurality of clock signals having a desired frequency. The counter shift register 51 outputs to the selector 52 a plurality of clock signals that are out of phase with respect to the phase of the reference clock signal CLK1 at the same frequency as the reference clock CLK1 obtained by dividing the high-speed clock signal HCLK. The selector 52 selects a clock signal having an optimum phase from a plurality of clock signal inputs based on a phase select signal and outputs it as an output clock signal CLK2.

A more detailed example of the circuit of FIG. 3 will be described with reference to FIG. This example is one example of a circuit that generates a clock signal having eight different phases using a counter shift register, and its timing chart is shown in FIG.

The counter shift register 51 is composed of four flip-flops 81 each having a data input terminal D, a data positive phase output terminal Q, a data negative phase output terminal QB, and a reset terminal CLR. The Q output of each flip-flop 81 is connected to the D input of the next stage, and the QB terminal of the last output is connected so as to be returned to the D input of the first flip-flop 81. If the initial value of the operation start is indefinite, the circular counter shift register 51 cannot obtain a correct output. Therefore, the flip-flop 8 outputs the reset signal (RST) at the start of the operation.
1 is input to the reset terminal (CLR), and the Q output is set to "L" level and the QB output is set to "H" level.

In the timing chart of FIG. 5, the shaded portion represents the data indeterminate state. By inputting the RST signal at the start of operation, the Q outputs D4 to D7 of the flip-flop 81 are set to the "L" level and the QB
The outputs D0 to D3 are set to the "H" level.

The operation of the counter shift register 51 is performed by changing the high-speed clock signal HCLK, which is an input clock, to 8 times.
The divided output can be obtained, and the Q output and QB output of each flip-flop 81 become clock signals of different phases. At this time, the QB output of the final stage (bottom) flip-flop 81-4 in the counter shift register 51 of FIG.
When the signal entering 2 is D0, the Q output and QB output of each flip-flop 81 are D1 to D1 as shown in FIG.
Assuming D7, the phase relationship is as shown in FIG. That is,
The phase of each output is the high-speed clock signal H based on D0.
Each CKL cycle is getting faster. This different 8 phase clock (the output obtained by dividing HCLK by 8) is selected by the selector 5
By selecting and outputting according to 2, the reference clock CL
A clock with a phase earlier than K1 can be obtained.

FIG. 6 shows an example of another circuit configuration using a counter shift register, and FIG. 7 shows a timing chart thereof. The clock generator 3 includes a frequency division counter 9
2 and shift register 62. In order to generate an 8-phase output clock, the frequency division counter 92 is composed of a frequency division counter of 8, and the shift register 62 is composed of eight flip-flops 91. Further, the phase control unit 4 is composed of the selector 52 similarly to the structure of the above-mentioned embodiment. In the flip-flop 91 forming the shift register 62, the Q output of the first-stage flip-flop 91 is connected to the data terminal D of the next-stage flip-flop 91. Hereinafter, the Q output is sequentially connected to the data terminal D of the next stage.

The operation of the clock generator 3 is performed by the clock source 5
The high-speed clock signal HCLK generated by 0 is divided by 8 by a divide-by-8 counter, and the first-stage flip-flop 9 of the counter shift register 51 is divided as a divided clock signal SCLK.
1 is supplied to the data terminal D. In the counter / shift register 51, the flip-flop 91 sequentially shifts the divided clock signal SCLK in synchronization with the high-speed clock signal HCLK. When the outputs of the respective flip-flops at that time are D0 to D7, the final output of the shift register is D0, and the previous output thereof is D1, the first output of the shift register is D7. As shown in FIG. 7, these outputs are advanced in phase by one cycle of the high-speed clock signal HCLK with reference to the phase of the output D0 at the final stage.

A clock having a phase earlier than the reference clock CLK1 can be obtained by selecting and outputting the different 8-phase clocks (outputs obtained by dividing HCLK by 8) by the selector 52 which is the phase control unit 4. .

FIG. 8 shows an example in which the configuration of the clock generator 3 is realized by using the delay circuit 61. A clock signal SCLK is generated from the clock source 50 and supplied to the delay circuit 61. By connecting the delay circuits 61 in several stages in series, it is possible to obtain clock signal outputs having different phases from the respective outputs. A clock signal having an optimum phase is selected by the selector 52 which constitutes the phase control unit 4 from these outputs, and is output as the clock signal CLK2 which is in phase with or ahead of the reference clock signal CLK1.

FIG. 9 shows an example of a circuit for generating a clock signal having eight different phases using a delay circuit.
0 shows the timing chart. Clock generator 3
Is composed of seven delay circuits 61 connected in series. The output of each delay circuit 61 is connected to the selector 52 that constitutes the phase controller 4. The clock signal SCLK output from the clock source 50 passes through the delay circuit 61 and is delayed (d). This delay circuit can be easily configured with a buffer gate or the like. The final output of the delay circuit connected in series is D0,
Based on that phase, the phase of each delay circuit output is
As shown in 0, the delays are faster. By selecting and outputting these eight-phase clocks by the selector 52 included in the phase controller 4, the reference clock signal CLK is output.
A clock with a phase earlier than 1 can be obtained.

FIG. 11 shows an example of the clock generator 3 and the phase controller 4 which can automatically select the optimum phase. A PLL (Phase
A Locked Loop circuit 71 is used, and a timing extraction circuit 72 is used as a means for controlling the phase. The timing extraction circuit 72 has a function of extracting the phase of data from the input data DAT3 from the second device B. The phase extracted here and the output clock HCL of the clock source 50
The phase of K is compared by the PLL circuit 71, and a clock signal of an appropriate phase is output as the phase advance clock signal CLK2.

FIG. 12 shows an example in which the clock generator 3 and the phase controller 4 are composed of a PLL circuit 71 and a timing extraction circuit 72, and FIG. 13 shows an operation timing chart thereof. The PLL circuit 71 has a lead / lag determination circuit 93.
, An integrating circuit 94, and a voltage-controlled oscillator 95. The phase of the input data in the first device A1 has changed with respect to the reference clock signal CLK1 which is the clock of the first device A1 due to the delay in the transmission path 7 and the second device B2. Therefore, the timing extraction unit 7
At 2, the change point of the data is extracted from the received input data DAT3, and the phase is corrected by the PLL circuit 71.

The timing extracting section 72 can be realized by forming a differentiating circuit using a high speed clock or a chopper circuit. The change point of the data extracted here is P
An advance / delay determination unit 93 inside the LL circuit 71 determines advance or delay with respect to the reference clock signal CLK1.

As shown in the timing chart of FIG. 13, the change point of the input data DAT3 is changed to the reference clock signal CLK1.
In order to synchronize with the rising edge of, the change point position of the input data DAT3 with respect to the lead / lag window is determined. The result of the determination is phase-voltage converted in the integrating circuit 94. The output voltage level of the integrating circuit changes depending on the amount of lead / lag of the change point position. As shown in FIG. 13, when the phase of the input data DAT3 is largely deviated in the delay direction, the voltage level is low, and when there is a phase, the voltage level settles to a substantially constant voltage value. By controlling the voltage-controlled oscillator 95 to keep this voltage level constant,
An output clock CLK2 having a desired phase can be obtained.

The phase detection method (timing extraction, lead / lag determination) used here is the selection signal (SEL0, 1, 2) of the selector which is the phase control unit of the shift register method and the delay circuit method described above. Therefore, when the determination result is used as a selector selection signal, automatic phase control is possible.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the transmission device and can be applied to various devices. Since this device can be widely applied to data transmission between devices that require data transmission and within devices, it can also be applied to OA equipment and the like.

[0035]

According to the present invention, it is possible to correct the transmission line delay occurring between data transmission devices by using a simple circuit configuration. Further, according to the present invention, it is possible to provide a clock phase control circuit capable of advancing the phase of the clock supplied to the data transmission side transmission device according to the delay on the transmission path. Further, according to the present invention, it is possible to provide a clock phase control circuit capable of changing the phase of the supplied clock by using a clock faster than the clock supplied to the data transmission side transmission device.

Furthermore, as another means for changing the clock phase, it is possible to provide a clock phase control circuit which can change the phase of the clock supplied to the data transmission side transmission device by using a delay element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transmission device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the data transmission device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram when a shift register is used as a clock generation unit.

FIG. 4 is a configuration diagram when a cyclic shift register is used.

FIG. 5 is a timing chart when a cyclic shift register is used.

FIG. 6 is a configuration diagram when a frequency division counter and a shift register are used.

FIG. 7 is a timing chart when a frequency division counter and a shift register are used.

FIG. 8 is an explanatory diagram when a delay circuit is used in the clock generation unit.

FIG. 9 is a configuration diagram when a delay circuit is used.

FIG. 10 is a timing chart when a delay circuit is used.

FIG. 11 is an explanatory diagram when a PLL is used for a clock generation unit.

FIG. 12 is a configuration diagram when a timing extraction unit and a PLL are used.

FIG. 13 is a timing chart when a timing extraction unit and a PLL are used.

FIG. 14 is a configuration diagram of a conventional data transmission device.

FIG. 15 is a timing chart showing the operation of a conventional data transmission device.

[Explanation of symbols]

 1 1st apparatus A 2 2nd apparatus B 3 Clock generation part 4 Phase control part 5 Data acquisition flip-flop of 1st apparatus A 6 Internal circuit of 1st apparatus A 7 Transmission path 8 2nd apparatus B Data output flip-flop 9 Internal circuit of the second device B 10 Delay addition circuit 11 Clock replacement unit 50 Clock source 51 Counter shift register 52 Selector 61 Delay circuit 62 Shift register 71 PLL circuit 72 Timing extraction unit 81 Flip-flop with reset 91 Flip-flop 92 Frequency dividing counter 93 Leading / lagging judging section 94 Integrating circuit 95 Voltage controlled oscillator

Claims (4)

[Claims] 1. A transmission device for transmitting data between two devices, that is, a device for transmitting a data signal and a clock signal or a clock signal, and a device for transmitting a data signal according to the clock signal. A transmission apparatus comprising: a delay correction unit that corrects a delay of a data signal generated on a transmission path. 2. When the delay amount of the transmission path of the data signal and the clock signal and the delay amount in the receiving side device are known, the transmitting side device transmits the clock signal, and the receiving side device uses the clock signal to transmit the data. When a signal is generated and output, the delay correction means for the data signal is provided with a phase changing means for changing the phase of the clock signal, and the phase of the clock signal on the transmitting side is advanced by the amount of these transmission delays. 2. The transmission device according to claim 1, which is a phase control unit that corrects the delay of the data signal by. 3. Phase changing means for changing the phase of a clock signal, comprising: a high-speed clock having a frequency higher than that of the clock signal to be transmitted; and a clock generation means for generating a plurality of transmitted clock signals having different phases, and a counter composed of flip-flops. 3. The transmission device according to claim 2, further comprising: selecting means for selecting a clock signal having a phase corresponding to a transmission delay from the plurality of clock signals. 4. A means for detecting a phase difference between a data signal and a reference clock signal as means for selecting a clock signal, wherein the phase of the clock signal to be transmitted is switched based on this phase difference. Item 2. The transmission device according to Item 1.