JP2008244807A - Time interleave circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a time interleave circuit capable of performing processing with a margin for access even in a differential modulation system. <P>SOLUTION: The time interleave circuit is used for a transmitter which performs wireless transmission and is provided with a writing order changing part 2 which considers a signal of a carrier number with the equal number of delay symbols as one set, for carrier signals modulated by a prescribed modulation system, and outputs the carrier signals in order from the smallest carrier number in the set by every set, a memory control part 3 which writes output of the writing order changing part 2 in a memory element 4 and controls reading by being delayed by the predetermined number of symbols from the memory element 4 and an output order changing part 5 which rearranges output of the memory control part 3 in order of carrier numbers to perform output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a time interleaving circuit of a transmitting apparatus that performs radio transmission, and relates to a time interleaving circuit that performs rearrangement in units of symbols in order to disperse burst errors into random errors.

  There is a digital transmission device that digitally modulates an input digital signal for each symbol and transmits it wirelessly. In general, a carrier signal by digital modulation is carried by being synchronously modulated or differentially modulated, and the synchronous modulation method transmits an absolute value with respect to a reference, and the differential modulation method is a relative value, that is, a previous value. The difference value is transmitted with respect to the value.

  According to the ARIB-STD-B33 standard of the Radio Industry Association (portable OFDM digital wireless transmission system for transmitting television broadcast program material), when the memory cell length is 1K full mode, the total number of carriers is 1152 The number of data carriers is 672 in the synchronous modulation system and 840 in the differential modulation system. This is a modulation system based on orthogonal frequency division multiplex (OFDM), which transmits not only data, but also guard intervals and pilot signals, so the number of data carriers is set to the total number of carriers of one symbol. On the other hand, it is less. In addition, it is necessary to determine in advance whether to employ a synchronous modulation method or a differential modulation method for carrier modulation.

  The time interleave circuit is a technique for converting a local burst error into a random error that is distributed on the time axis, and specifically delays a specified number of symbols according to a data carrier number. FIG. 6 shows an example of time interleaving using a RAM of a memory element. A symbol number is set as an upper address and a carrier number is set as a lower address, and a signal is stored in the RAM. A time interleave is configured by reading with a delay. The carrier number of the read signal is the same as that at the time of writing, and the symbol number is obtained by subtracting the number of delay symbols from the symbol number at the time of writing. As a result, the signal is delayed by the number of delay symbols.

  As an example of the prior art of the time interleave circuit, there is an interleave device shown in FIG. In FIG. 7, the write address generator 10 and the read address generator 11 generate a write address and a read address according to the same clock, and the selector 12 switches between the read cycle and the write cycle in one clock, and the write is performed. The input data is written to the memory circuit (RAM) 13 during the cycle, and the data stored in the memory circuit 13 is read during the read cycle to output the data. The memory circuit 13 has a configuration in which a plurality of sub-blocks have a value in the carrier direction that is an integer multiple of an appropriate value, and the interleave depth is repeated in units of sub-blocks, thereby reducing the circuit scale of the memory circuit. (For example, see Patent Document 1).

Japanese Patent No. 3239084

A conventional time interleave circuit uses a RAM. In the RAM, data read and write requests detect a transition level (change from a high level to a low level) inside the DRAM chip and are asynchronous with respect to that level. Data read / write operations were performed using this method.
This asynchronous control method has room for improvement when it is desired to operate at high speed. Therefore, instead of this RAM, an attempt was made to use SDRAM (Synchronous DRAM) that performs data writing and reading in a synchronous manner as a memory element of the memory circuit, and to operate at high speed. In the SDRAM, all signal exchange with the outside is performed in synchronization with a synchronization signal (clock).

  When SDRAM is used in the time interleave circuit in the synchronous modulation method, in the data write operation to the memory (SDRAM), the lower address is the carrier number and the upper address is the symbol number, and the data is written to the memory in the order of the carrier number. When the data for one symbol has been written, the data is written to the memory area of the next symbol. In this write operation, 8 words (for the carrier) are collectively written, that is, the burst length is collectively set to 8 words, and the operation proceeds to the read operation. Next, when reading data from the memory (SDRAM), the lower address is used as the carrier number, and the upper address is read using an arithmetic expression [(written symbol number) − (number of delay symbols)]. In the read operation, 8 words are output in one access, and since only 1 word of the carrier data is required, the remaining 7 words are discarded. When 8 words (= 8 accesses for 8 carriers) are read from the memory, the next write operation is started. In the memory (SDRAM), writing and reading operations are executed repeatedly.

  Therefore, in the case of synchronous modulation, in the 1K · full mode, the carrier frequency is 20.450743 MHz, the number of data carriers is 672, and the cycle of the data carrier is expressed by the following equation.

  In the case of differential modulation, in the 1K · full mode, the carrier frequency is 20.450743 MHz and the number of data carriers is 840, and the period of the data carrier is expressed by the following equation.

  On the other hand, in the case of the half mode, any modulation method is twice the full mode. That is, in the case of the differential modulation method in the full mode, when an SDRAM having a memory access time (cycle time) of 60 nS is used, the access time cannot be used without sufficient capacity. If reading is performed for each carrier, there is a problem that access to the SDRAM as a transmission system is not in time.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a time interleave circuit capable of processing with a margin for access even in the differential modulation method.

The present invention achieves the above-mentioned problems, and the invention of claim 1 is a time interleave circuit used in a transmitter for wireless transmission,
A writing order changing means for making a carrier signal modulated by a predetermined modulation method a signal having a carrier number having the same number of delay symbols as one set, and outputting each set in the order of a carrier number having a smaller number in the set; ,
Memory control means for writing the output of the write order changing means to a memory element, and controlling reading by delaying the predetermined number of symbols from the memory element;
The time interleaving circuit further comprises output order changing means for rearranging outputs of the memory control means in the order of the carrier numbers.

According to a second aspect of the present invention, in the time interleave circuit according to the first aspect,
The memory control means writes to the memory element every predetermined number of bursts, and deletes data other than necessary from the data read from the memory element for each predetermined burst number, and outputs the data. It is a time interleave circuit.

According to a third aspect of the present invention, in the time interleave circuit according to the first aspect,
The memory element is a time interleave circuit, which is an SDRAM.

According to a fourth aspect of the present invention, in the time interleave circuit according to the first aspect,
The write order changing means, the memory control means, and the output order changing means are controlled by an external modulation method control, and are time interleave circuits.

  According to the first aspect of the present invention, since signals with carrier numbers having the same number of delay symbols are processed together, the processing for each carrier number is not required, and therefore the time at which dispersion is achieved by delaying by a predetermined number of symbols. This is suitable for an interleave circuit. Further, since processing is performed with the number of symbols, it is suitable for a digital modulation apparatus that performs modulation for each symbol.

  According to the second aspect of the present invention, since burst write and burst read are used in the access control to the memory element, there is an advantage that an access time (cycle time) can be afforded and an inexpensive memory element can be used. .

  Further, according to the invention of claim 3, since the memory element is an SDRAM, burst write and burst read are possible, which is suitable for time interleaving processing, and because SDRAM is less expensive than SRAM, There is an advantage that it can be handled at low cost.

  Further, according to the invention of claim 4, since it is configured to switch the presence / absence of rearrangement and the number of data deletion by the synchronous or differential modulation method, regardless of the modulation method, the synchronous modulation method or the differential modulation method can be used. There is an advantage that can be handled.

  The best mode of the time interleaving circuit of the present invention will be described below with reference to FIGS.

  FIG. 1 shows an embodiment of the present invention. In the figure, 1 is an input terminal, 2 is a writing order changing unit, 3 is a memory control unit, 4 is a memory element (SDRAM), 5 is an output order changing unit, 6 is an output terminal, and 7 is a mode setting unit. Yes, it is a time interleave circuit used in a transmitter for wireless transmission, and carrier signals modulated by a predetermined modulation method are set with a carrier number signal having the same number of delay symbols as one set, and each set has a number in the set. Writing order changing unit 2 (writing order changing means) for outputting in the order of smaller carrier numbers, and writing the output of writing order changing unit 2 to memory element 4 and delaying from memory element 4 by a predetermined number of symbols A memory control unit 3 (memory control unit) that controls reading, and an output order change unit 5 (output order change unit) that outputs the outputs of the memory control unit 3 in the order of carrier numbers. Provided by the time interleave circuit has can be randomly distributed error occurrence of errors dwell in digital transmission from burst errors.

  In this embodiment, the memory control unit 3 writes data to the memory element 4 every predetermined number of bursts, and deletes data other than necessary from the data read from the memory element 4 every predetermined number of bursts and outputs the data. Is controlling. The memory element 4 is, for example, an SDRAM. The write order changing unit 2, the memory control unit 3, and the output order changing unit 5 are controlled by a modulation method control from the outside by the mode setting unit 7, and the mode setting unit 7 has a synchronous or differential modulation method. The switching control unit is set to any one of the modulation schemes, and switches and controls the writing order changing unit 2, the memory control unit 3, and the output order changing unit 5 according to the modulation scheme.

  Hereinafter, this embodiment will be described in detail with reference to FIG. In the time interleave circuit, a carrier signal differentially modulated with a plurality of carriers is input to the input terminal 1. The order of the carrier signals input from the input terminal 1 is changed by the writing order changing unit 2 and the data is rearranged. First, the number of delay symbols used in the writing order changing unit 2 will be described. The number of data carriers of the differentially modulated signal is 840. Note that according to the ARIB-STD-B33 standard of the Radio Industry Association (standard document page 28), the cell length is I, the carrier number is i, and the number of delay symbols Xt (i) of the i-number carrier is as follows: The following relational expression holds.

  However, in the above [Expression 3], the cell length I is a parameter related to the interleave length, and is a predetermined value, which is an integer.

  When the arithmetic processing is performed according to the above [Equation 3], as shown in FIG. 2A, 0 and 672, 1 and 673, 2 and 674,... 167 and 839 become carrier numbers having the same number of delay symbols. When a group having the same number of delay symbols is set as one set and rearranged in ascending order of the carrier number in one set, as shown in FIG. 2B, the arrays are arranged in the order of 0 672 1 673 2 674 ... 167 839 168. Is done. 2 (a) and 2 (b) show the arrangement of carrier numbers changed by rearrangement. FIG. 2 (a) is an input, and FIG. 2 (b) is an output. This output is input to the memory control unit 3.

  The memory control unit 3 writes the input signal of FIG. 2B to the memory element 4 by 8 carriers at a burst length of 8 as shown in FIG. In the write operation, 8 carriers are written to 840 lines, so that 105 times are written per symbol. For the address, the upper address is a symbol number and the lower address is a carrier number. Therefore, the lower address is from 0 to 671.

  The read address is an address that is subtracted from the upper address for writing the number of symbols delayed by the upper address, and the lower address is the same address as the write. As a result, the carrier signal is output after being delayed by a predetermined number of symbols. The read operation is performed 672 times per symbol.

  As shown in FIGS. 5A and 5B, the read data is read for 8 carriers in order to read as a burst length of 8, as shown in FIGS. FIG. 5A shows a case where carriers having the same number of delay symbols are included, and carrier numbers 0 and 672 are read out simultaneously. The other X marks are unnecessary data and are deleted. FIG. 5B shows a case where carriers having the same number of delay symbols are not included. Carrier numbers 168 to 671 are targeted, and the x mark is deleted.

  The writing operation and the reading operation shift to the reading operation after writing once for 8 carriers, that is, with a burst length of 8. When reading is performed 8 times with a burst length of 8, the write operation starts. There are two types of read data: 6 data is deleted and 7 data is deleted.

  The output order changing unit 5 outputs the data output from the memory element 4 in a set having the same number of delay symbols in the carrier number order by the reverse operation of the writing order changing unit 2. 3 (a) and 3 (b) show the operation of the output order change unit 5, FIG. 3 (a) shows the data array input to the output order change unit 5, and FIG. 3 (b) shows the output. . The output order changing unit 5 operates in reverse to the writing order changing unit 2, and a carrier signal delayed by a predetermined symbol is output from the output terminal 6.

  Note that the write order changing unit 2 and the output order changing unit 5 can be implemented by using a memory element such as a RAM as an example. For example, if a dual port RAM having a sequential port is used, a compact configuration can be achieved. Specifically, the writing order changing unit 2 writes data from the sequential port and reads data from the random port while changing the order. The output order changing unit 5 changes the order from the random port and writes, and reads from the sequential port. It can respond by comprising in this way.

  The mode setting unit 7 controls the writing order changing unit 2, the memory control unit 3, and the output order changing unit 5 based on either modulation method of synchronous modulation or differential modulation. The number of data carriers is 672 in the synchronous modulation scheme and 840 in the differential modulation scheme. Since there are 672 synchronous modulation systems, the writing order changing unit 2 and the output order changing unit 5 do not need to be rearranged. Since the differential modulation method is 840 lines, it is necessary to rearrange them. For the memory control unit 3, there is no problem with the burst length of 8 during the write operation, but during the read operation, the number of data to be deleted is different, so control is performed according to the modulation method. The mode setting unit 7 performs the mode setting as described above.

  The SDRAM used in one embodiment of the present invention may be a DDR (Double Data Rate) type or an SDR (Single Data Rate) type as long as it can perform burst write / read.

  In the synchronous modulation method, the write operation to the memory (SDRAM) 4 is performed with a burst length of 8 for 672 carrier numbers, so that 672/8 = 84 write operations. In addition, since the number of carrier numbers is read, the read operation is 672 times, which is 756 times in total. In the differential modulation method, since the write operation is performed with a burst length of 8 for 840 carrier numbers, the operation is 840/8 = 105 times, and the read operation is 672 times by burst read. The total is 777 times, which is a 21% increase over the tuned modulation method. The average access time is 81.0 ns, and it can be verified that there is no problem even if a 60 ns SDRAM is used.

  As an application example of the present invention, it is effective for a time interleave circuit of a digital modulation transmission apparatus having carrier signals with the same number of delay symbols as in the ARIB-STD-B33 standard of the Radio Industries Association. Further, although it is a time interleaving circuit of the transmitting device, the receiving device can be configured in the same way as a reverse operation even as time deinterleaving.

It is a block diagram which shows one Embodiment of the time interleave circuit of this invention. It is operation | movement explanatory drawing of the writing order change part in this embodiment. It is operation | movement explanatory drawing of the output order change part in this embodiment. It is a figure which shows the data structure at the time of the memory write in this embodiment. It is a figure which shows the data structure at the time of the memory read in this embodiment. It is a figure explaining the time interleave operation | movement in this embodiment. It is a block diagram which shows the conventional time interleave circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Writing order change part 3 Memory control part 4 Memory element (SDRAM)
5 Output order change part 6 Output terminal 7 Mode setting part

Claims (4)

A time interleaving circuit used in a transmitting device for wireless transmission,
A writing order changing means for making a carrier signal modulated by a predetermined modulation method a signal having a carrier number having the same number of delay symbols as one set, and outputting each set in the order of a carrier number having a smaller number in the set; ,
Memory control means for writing the output of the write order changing means to a memory element, and controlling reading by delaying the predetermined number of symbols from the memory element;
The time interleaving circuit comprising: an output order changing means for rearranging and outputting the outputs of the memory control means in the order of the carrier numbers. The time interleave circuit according to claim 1,
The memory control means writes to the memory element every predetermined number of bursts, and deletes data other than necessary from the data read from the memory element for each predetermined burst number, and outputs the data. Time interleave circuit. The time interleave circuit according to claim 1,
The time interleave circuit, wherein the memory element is an SDRAM. The time interleave circuit according to claim 1,
The time interleaving circuit, wherein the writing order changing means, the memory control means, and the output order changing means are controlled by external modulation scheme control.

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