JP2008244406A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2008244406A
JP2008244406A JP2007086808A JP2007086808A JP2008244406A JP 2008244406 A JP2008244406 A JP 2008244406A JP 2007086808 A JP2007086808 A JP 2007086808A JP 2007086808 A JP2007086808 A JP 2007086808A JP 2008244406 A JP2008244406 A JP 2008244406A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor device
substrate
parasitic
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007086808A
Other languages
Japanese (ja)
Inventor
Masa Motohashi
雅 本橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2007086808A priority Critical patent/JP2008244406A/en
Publication of JP2008244406A publication Critical patent/JP2008244406A/en
Withdrawn legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: a resistor element does not work in accordance with design with respect to a high-frequency signal. <P>SOLUTION: A semiconductor device includes a substrate, a well formed on the substrate and having a relatively low impurity concentration, an insulating film formed on the well, and a resistor element engineered for a high-frequency signal and formed on the insulating film. For one part of the resistor element and the other part, the semiconductor device further includes a first parasitic capacitance to be formed between one part of the resistor element and the insulating film, a second parasitic capacitance to be formed between the other part of the resistor element and the insulating film, and a parasitic resistance to be formed between the first and second parasitic capacitances in the well. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、抵抗素子を有する、高周波信号用(例えば、数GHzの信号用)の半導体装置に関する。   The present invention relates to a semiconductor device for high frequency signals (for example, for signals of several GHz) having a resistance element.

図3に示される、従来の半導体装置SD10では、下記の特許文献1に記載された解決しようとする課題「高周波領域での寄生容量の低減」、及び、下記の特許文献2に記載された主要な構成「基板抵抗の低減のための、インダクタンス及び素子分離領域間でのシールド層の配置」に関連して、回路構成としては、P型基板S1上に、不純物濃度が「比較的高い」P型ウェルW10が形成されており、当該P型ウェルW10上に、素子分離膜の機能を有する絶縁膜D2が形成されており、当該絶縁膜D2上に、抵抗素子Rが形成されている。   In the conventional semiconductor device SD10 shown in FIG. 3, the problem to be solved “reduction of parasitic capacitance in a high-frequency region” described in Patent Document 1 below, and the main elements described in Patent Document 2 below. In connection with the “configuration of the shield layer between the inductance and the element isolation region for reducing the substrate resistance”, the circuit configuration is such that the impurity concentration is “relatively high” on the P-type substrate S1. A type well W10 is formed, an insulating film D2 having a function of an element isolation film is formed on the P type well W10, and a resistance element R is formed on the insulating film D2.

当該抵抗素子R上には、層間絶縁膜の機能を有する絶縁膜D1が形成されており、さらに、当該絶縁膜D1上には、金属配線M1a、M1bが形成されており、前記抵抗素子Rと、金属配線M1a、M1bとは、それぞれ、コンタクトCT1、CT2により接続されている。   An insulating film D1 having the function of an interlayer insulating film is formed on the resistance element R, and metal wirings M1a and M1b are formed on the insulating film D1, and the resistance element R The metal wirings M1a and M1b are connected by contacts CT1 and CT2, respectively.

前記抵抗素子Rは、電気的な機能としては、入力端IP2及び出力端OP2がP型基板S2により接地電位GNDに接続されている下で、金属配線M1aから、即ち、入力端IP1から、高周波信号Shの入力を受け、他方で、当該高周波信号Shを、金属配線M1bから、即ち、出力端OP1から出力する。   The resistance element R has an electrical function in that the input terminal IP2 and the output terminal OP2 are connected to the ground potential GND by the P-type substrate S2, and from the metal wiring M1a, that is, from the input terminal IP1, the high frequency On the other hand, the high frequency signal Sh is received from the metal wiring M1b, that is, from the output terminal OP1.

上記した半導体装置SD10の本質的な構成とは異なり、絶縁膜D2を挟む位置にある抵抗素子R及びP型ウェルW10間には、寄生容量C1、C2が存在し、また、P型ウェルW10中における前記寄生容量C1、C2間に、前記抵抗素子Rと並列接続となるような寄生抵抗Rwが存在する。これにより、前記高周波信号Shが通り得る経路として、図3に示されるように、抵抗素子Rのみからなる本来の経路RT1に加えて、寄生容量C1、寄生抵抗Rw、寄生容量C2からなる迂回的な経路RT2が存在する。   Unlike the above-described essential configuration of the semiconductor device SD10, there are parasitic capacitances C1 and C2 between the resistance element R and the P-type well W10 located between the insulating film D2, and in the P-type well W10. A parasitic resistance Rw that is connected in parallel with the resistance element R exists between the parasitic capacitances C1 and C2. Thereby, as shown in FIG. 3, as a path through which the high-frequency signal Sh can pass, in addition to the original path RT1 including only the resistance element R, a detour including the parasitic capacitance C1, the parasitic resistance Rw, and the parasitic capacitance C2 is performed. There is a simple route RT2.

特開2005−26616号公報Japanese Patent Laying-Open No. 2005-26616 特開2000−22085号公報JP 2000-22085 A

しかしながら、上記した寄生抵抗Rwの抵抗値が前記P型ウェルW10の不純物濃度の如何により定まることから、当該P型ウェル中の不純物濃度が大きいとき又は極めて大きいときには、当該寄生抵抗Rwの抵抗値は、当該抵抗素子Rの抵抗値に比して小さい又は極めて小さくなり、この結果、前記高周波信号Shは、本来の経路RT1より迂回的な経路RT2に優先的に流れてしまい、これにより、当該抵抗素子Rが、前記高周波信号Shに対し、設計通りに機能しなくなるという問題があった。   However, since the resistance value of the parasitic resistance Rw is determined depending on the impurity concentration of the P-type well W10, when the impurity concentration in the P-type well is high or extremely high, the resistance value of the parasitic resistance Rw is As a result, the high-frequency signal Sh flows preferentially to the detour path RT2 rather than the original path RT1, and as a result, the resistance value of the resistance element R becomes smaller. There is a problem that the element R does not function as designed for the high-frequency signal Sh.

本発明に係る第1の半導体装置は、上記した課題を解決すべく、
基板と、
前記基板上に形成されている、不純物濃度が相対的に低いウェルと、
前記ウェル上に形成されている、高周波信号のための絶縁膜と、
前記絶縁膜上に形成されている抵抗素子と、を含み、
前記抵抗素子の一部と他の一部とを、前記抵抗素子の前記一部及び前記絶縁膜間に形成され得る第1の寄生容量並びに前記抵抗素子の前記他の一部及び前記絶縁膜間に形成され得る第2の寄生容量と、
前記ウェル中における、前記第1、第2の寄生容量間に形成され得る寄生抵抗と、更に含む。
The first semiconductor device according to the present invention is to solve the above-described problems.
A substrate,
A well having a relatively low impurity concentration formed on the substrate;
An insulating film for high-frequency signals formed on the well;
A resistive element formed on the insulating film,
A part of the resistive element and another part of the first parasitic capacitance that can be formed between the part of the resistive element and the insulating film, and between the other part of the resistive element and the insulating film A second parasitic capacitance that can be formed in
And a parasitic resistance that can be formed between the first and second parasitic capacitances in the well.

本発明に係る第2の半導体装置は、上記した課題を解決すべく、
不純物濃度が相対的に低い基板と、
前記基板上に形成されている絶縁膜と、
前記絶縁膜上に形成されている、高周波信号のための抵抗素子と、を含み、
前記抵抗素子の一部と他の一部とを、前記抵抗素子の前記一部及び前記絶縁膜間に形成され得る第1の寄生容量並びに前記抵抗素子の前記他の一部及び前記絶縁膜間に形成され得る第2の寄生容量と、
前記基板中における、前記第1、第2の寄生容量間に形成され得る寄生抵抗と、更に含むことを特徴とする半導体装置。
The second semiconductor device according to the present invention is to solve the above-described problems.
A substrate having a relatively low impurity concentration;
An insulating film formed on the substrate;
A resistance element for a high-frequency signal formed on the insulating film,
A part of the resistive element and another part of the first parasitic capacitance that can be formed between the part of the resistive element and the insulating film, and between the other part of the resistive element and the insulating film A second parasitic capacitance that can be formed in
A semiconductor device further comprising: a parasitic resistance that can be formed between the first and second parasitic capacitors in the substrate.

上記した本発明に係る第1、第2の半導体装置によれば、前記第1の半導体装置における前記ウェルの不純物濃度、及び、前記第2の半導体装置における前記基板の不純物濃度が、相対的に低いことにより、前記寄生抵抗の抵抗値が従来に比して大きくなることから、前記高周波信号は、前記第1、第2の寄生容量と、当該大きい抵抗値を有する当該寄生抵抗とからなる迂回的な経路に流れ難くなり、その結果、前記高周波信号は、前記抵抗素子からなる本来の経路に優先的に流れることが可能となり、換言すれば、前記抵抗素子を、前記高周波信号に対し、略設計通りに機能させることが可能となる。   According to the first and second semiconductor devices according to the present invention described above, the impurity concentration of the well in the first semiconductor device and the impurity concentration of the substrate in the second semiconductor device are relatively Since the resistance value of the parasitic resistance is increased as compared with the conventional case, the high-frequency signal is a detour composed of the first and second parasitic capacitances and the parasitic resistance having the large resistance value. As a result, the high-frequency signal can flow preferentially to the original path composed of the resistance element, in other words, the resistance element is substantially connected to the high-frequency signal. It becomes possible to function as designed.

上記した本発明に係る第1の半導体装置では、前記基板及び前記ウェルは、P型である。   In the above-described first semiconductor device according to the present invention, the substrate and the well are P-type.

上記した本発明に係る第2の半導体装置では、前記基板は、P型である。   In the above-described second semiconductor device according to the present invention, the substrate is P-type.

本発明に係る半導体装置の実施例について図面を参照して説明する。
《実施例》
Embodiments of a semiconductor device according to the present invention will be described with reference to the drawings.
"Example"

図1(A)は、実施例の半導体装置の構成を示す断面図である。実施例の半導体装置SD1は、高周波信号Sh(例えば、数GHz以上の高周波信号)に対し、予め設計段階で決められた抵抗値を有する抵抗素子として機能すべく、基本的に、従来の半導体装置SD10(図3に図示。)と同様に、P型基板S1と、P型ウェルW1(従来のP型ウェルW10と異なる。)と、絶縁膜D1、D2と、抵抗素子Rと(ポリシリコンPからなる。)、コンタクトCT1、CTと、金属配線M1a、M1bと、を含む。   FIG. 1A is a cross-sectional view illustrating the structure of the semiconductor device of the example. The semiconductor device SD1 of the embodiment is basically a conventional semiconductor device so as to function as a resistance element having a resistance value determined in advance at the design stage with respect to a high-frequency signal Sh (for example, a high-frequency signal of several GHz or more). Similar to SD10 (shown in FIG. 3), a P-type substrate S1, a P-type well W1 (different from a conventional P-type well W10), insulating films D1 and D2, a resistance element R, and (polysilicon P) ), Contacts CT1 and CT, and metal wirings M1a and M1b.

より具体的には、半導体装置SD1では、回路構成としては、P型基板S1上に、不純物濃度が「比較的低い」P型ウェルW1が形成されており、当該P型ウェルW1上に、素子分離膜の機能を有する絶縁膜D2が形成されており、当該絶縁膜D2上に、抵抗素子Rが形成されている。   More specifically, in the semiconductor device SD1, as a circuit configuration, a P-type well W1 having a “relatively low impurity concentration” is formed on a P-type substrate S1, and an element is formed on the P-type well W1. An insulating film D2 having a function of a separation film is formed, and a resistance element R is formed on the insulating film D2.

当該抵抗素子Rには、当該抵抗素子Rの入力側(高周波信号Shの入力を受ける側)にコンタクトCT1が設けられており、他方で、出力側(高周波信号Shを出力する側)にコンタクトCT2が設けられている。当該コンタクトCT1には、入力側の配線として、金属配線M1aが接続されており、また、コンタクトCTには、出力側の配線として、金属配線M1bが接続されている。更に、当該抵抗素子R及び金属配線M1a、M1b間に、層間絶縁膜の機能を有する絶縁膜D1が形成されている。   The resistor element R is provided with a contact CT1 on the input side of the resistor element R (side receiving the input of the high-frequency signal Sh), and on the other hand, the contact CT2 on the output side (side outputting the high-frequency signal Sh). Is provided. A metal wiring M1a is connected to the contact CT1 as an input-side wiring, and a metal wiring M1b is connected to the contact CT as an output-side wiring. Further, an insulating film D1 having a function of an interlayer insulating film is formed between the resistance element R and the metal wirings M1a and M1b.

前記抵抗素子Rは、電気的な機能としては、金属配線M1aから(即ち、入力端IP1から)、高周波信号Shの入力を受け、他方で、当該高周波信号Shを、金属配線M1bへ(即ち、出力端OP1へ)出力する。なお、入力端IP2及び出力端OP2は、P型基板S1により接地電位GNDに接続されている。   The resistance element R receives an input of the high frequency signal Sh from the metal wiring M1a (that is, from the input terminal IP1) as an electrical function, and on the other hand, transmits the high frequency signal Sh to the metal wiring M1b (that is, the metal wiring M1b). Output to the output terminal OP1). The input terminal IP2 and the output terminal OP2 are connected to the ground potential GND by the P-type substrate S1.

上記した半導体装置SD1の本質的な構成に不要であるにも拘わらず、当該半導体装置SD1では、前記絶縁膜D2を挟む位置にある抵抗素子R及びP型ウェルW1間に、第1の寄生容量C1及び第2の寄生容量C2が存在し得る。また、P型ウェルW1における、当該第1の寄生容量C1及び第2の寄生容量C2間に、前記抵抗素子Rと並列接続の関係になるような寄生抵抗Rwが存在し得る。これにより、前記高周波信号Shが通過可能な経路としては、抵抗素子Rのみからなる本来的な経路R1に加えて、第1の寄生容量C1、寄生抵抗Rw、第2の寄生容量C2からなる迂回的な経路RT2が存在する。   In spite of being unnecessary for the essential configuration of the semiconductor device SD1 described above, in the semiconductor device SD1, a first parasitic capacitance is formed between the resistor element R and the P-type well W1 located between the insulating film D2. There may be C1 and a second parasitic capacitance C2. Further, a parasitic resistance Rw that can be connected in parallel with the resistance element R may exist between the first parasitic capacitance C1 and the second parasitic capacitance C2 in the P-type well W1. Thereby, as a path through which the high-frequency signal Sh can pass, in addition to the original path R1 including only the resistance element R, the detour including the first parasitic capacitance C1, the parasitic resistance Rw, and the second parasitic capacitance C2. There is a common path RT2.

当該半導体装置SD1は、上記したように、P型ウェルW1の不純物濃度が「相対的に低い」状態にあることから、前記寄生抵抗Rwの抵抗値は、従来に比して高くなり、その結果、前記高周波信号Shが、前記本来的な経路RT1より優先して当該迂回的な経路RT2に流れることが抑制される。換言すれば、前記抵抗素子Rが、前記高周波信号Shに対し設計通りに機能することを実現することが可能となる。   As described above, since the impurity concentration of the P-type well W1 is in a “relatively low” state in the semiconductor device SD1, the resistance value of the parasitic resistance Rw is higher than that in the related art, and as a result. The high-frequency signal Sh is suppressed from flowing to the detour route RT2 in preference to the original route RT1. In other words, it is possible to realize that the resistance element R functions as designed for the high-frequency signal Sh.

半導体装置SD1では、上記した構成に加えて、図1(B)の平面図に示されるように、抵抗素子Rは、P型ウェルW1から、X軸方向について距離d1(d1は、実験等により得られる値である。)だけ離し、Y軸方向について距離d2(d2は、実験等により得られる値。)だけ離すことが望ましい。これにより、高周波信号Shを、P型ウェルW1中の寄生抵抗Rwを含む迂回的な経路RT2よりも、抵抗素子Rのみを含む本来的な経路RT1に流すことが可能となる。   In the semiconductor device SD1, in addition to the above-described configuration, as shown in the plan view of FIG. 1B, the resistance element R is separated from the P-type well W1 by a distance d1 (d1 is experimentally determined) in the X-axis direction. It is desirable that the distance is separated by a distance d2 (d2 is a value obtained by experiment etc.) in the Y-axis direction. As a result, the high-frequency signal Sh can flow through the original path RT1 including only the resistance element R, rather than the detour path RT2 including the parasitic resistance Rw in the P-type well W1.

《変形例》
上記した実施例の半導体装置SD1における、P型基板S1及び不純物濃度が「比較的低い」P型ウェルW1を含む実施例の半導体装置SD1に代えて、図2に図示された変形例の半導体装置SD2における、不純物濃度が「比較的低い」P型基板S2によっても、上記したと同様な効果を得ることが可能となる。
<Modification>
In the semiconductor device SD1 of the above-described embodiment, instead of the semiconductor device SD1 of the embodiment including the P-type substrate S1 and the P-type well W1 whose impurity concentration is “relatively low”, the semiconductor device of the modification illustrated in FIG. Even with the P-type substrate S2 having a “relatively low” impurity concentration in SD2, the same effect as described above can be obtained.

実施例の半導体装置の構成を示す図。FIG. 6 illustrates a structure of a semiconductor device of an example. 変形例の半導体装置の構成を示す図。FIG. 9 shows a structure of a semiconductor device according to a modification. 従来の半導体装置の構成を示す図。FIG. 10 shows a structure of a conventional semiconductor device.

符号の説明Explanation of symbols

SD1…半導体装置、S1…P型基板、W1…P型ウェル、D1,D2…絶縁膜、R…抵抗素子、CT1,CT2…コンタクト、M1a,M1b…金属配線、C1…第1の寄生容量、C2…第2の寄生容量、Rw…寄生抵抗。   SD1 ... semiconductor device, S1 ... P-type substrate, W1 ... P-type well, D1, D2 ... insulating film, R ... resistance element, CT1, CT2 ... contact, M1a, M1b ... metal wiring, C1 ... first parasitic capacitance, C2: second parasitic capacitance, Rw: parasitic resistance.

Claims (4)

基板と、
前記基板上に形成されている、不純物濃度が相対的に低いウェルと、
前記ウェル上に形成されている絶縁膜と、
前記絶縁膜上に形成されている、高周波信号のための抵抗素子と、を含み、
前記抵抗素子の一部と他の一部とを、前記抵抗素子の前記一部及び前記絶縁膜間に形成され得る第1の寄生容量並びに前記抵抗素子の前記他の一部及び前記絶縁膜間に形成され得る第2の寄生容量と、
前記ウェル中における、前記第1、第2の寄生容量間に形成され得る寄生抵抗と、更に含むことを特徴とする半導体装置。
A substrate,
A well having a relatively low impurity concentration formed on the substrate;
An insulating film formed on the well;
A resistance element for a high-frequency signal formed on the insulating film,
A part of the resistive element and another part of the first parasitic capacitance that can be formed between the part of the resistive element and the insulating film, and between the other part of the resistive element and the insulating film A second parasitic capacitance that can be formed in
A semiconductor device further comprising a parasitic resistance that can be formed between the first and second parasitic capacitances in the well.
不純物濃度が相対的に低い基板と、
前記基板上に形成されている絶縁膜と、
前記絶縁膜上に形成されている、高周波信号のための抵抗素子と、を含み、
前記抵抗素子の一部と他の一部とを、前記抵抗素子の前記一部及び前記絶縁膜間に形成され得る第1の寄生容量並びに前記抵抗素子の前記他の一部及び前記絶縁膜間に形成され得る第2の寄生容量と、
前記基板中における、前記第1、第2の寄生容量間に形成され得る寄生抵抗と、更に含むことを特徴とする半導体装置。
A substrate having a relatively low impurity concentration;
An insulating film formed on the substrate;
A resistance element for a high-frequency signal formed on the insulating film,
A part of the resistive element and another part of the first parasitic capacitance that can be formed between the part of the resistive element and the insulating film, and between the other part of the resistive element and the insulating film A second parasitic capacitance that can be formed in
A semiconductor device further comprising: a parasitic resistance that can be formed between the first and second parasitic capacitors in the substrate.
前記基板及び前記ウェルは、P型であることを特徴とする請求項1記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate and the well are P-type. 前記基板は、P型であることを特徴とする請求項2記載の半導体装置。   The semiconductor device according to claim 2, wherein the substrate is P-type.
JP2007086808A 2007-03-29 2007-03-29 Semiconductor device Withdrawn JP2008244406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007086808A JP2008244406A (en) 2007-03-29 2007-03-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007086808A JP2008244406A (en) 2007-03-29 2007-03-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2008244406A true JP2008244406A (en) 2008-10-09

Family

ID=39915325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007086808A Withdrawn JP2008244406A (en) 2007-03-29 2007-03-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2008244406A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009481A (en) * 2010-06-22 2012-01-12 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
JP2015133527A (en) * 2015-04-27 2015-07-23 ルネサスエレクトロニクス株式会社 Semiconductor device and method of manufacturing the same
WO2023058555A1 (en) * 2021-10-04 2023-04-13 株式会社村田製作所 Transient voltage absorbing element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009481A (en) * 2010-06-22 2012-01-12 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
JP2015133527A (en) * 2015-04-27 2015-07-23 ルネサスエレクトロニクス株式会社 Semiconductor device and method of manufacturing the same
WO2023058555A1 (en) * 2021-10-04 2023-04-13 株式会社村田製作所 Transient voltage absorbing element

Similar Documents

Publication Publication Date Title
JP2008211215A (en) Multi-finger transistor
EP1840913A1 (en) Capacitor and electronic circuit
JP2009239844A (en) Noise filter and amplifier circuit with built-in noise filter
WO2018235135A1 (en) Semiconductor device
JP2008135675A (en) Semiconductor chip, semiconductor device, and mounting board
JP2008244406A (en) Semiconductor device
US7291918B2 (en) Layout structure of electrostatic discharge protection circuit
JP2004241710A (en) Semiconductor device
US8125749B2 (en) Electrostatic protection circuit
JP2008305852A (en) Semiconductor device
KR100910399B1 (en) Low-capacitance electrostatic discharge protection diodes
JP2006121377A (en) Input circuit and semiconductor device
JP3946874B2 (en) Semiconductor device
JP2002217374A (en) Semiconductor device
JP2007095965A (en) Semiconductor device and bypass capacitor module
JP2006196803A (en) Semiconductor device
JP2005244077A (en) Semiconductor device
JP2006210926A (en) Semiconductor device with esd protective circuit
JP2008244407A (en) Semiconductor device
JP2009010273A (en) Power source noise filtering structure of printed wiring board
JP2009170626A (en) High frequency esd protection circuit
JP4918652B2 (en) Semiconductor device
US20100078726A1 (en) Semiconductor device
JP2005223213A (en) Semiconductor integrated circuit device
JPH09246476A (en) Power supply lines and method of planning layout of them in semiconductor integrated circuit

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20100601