JP2008244066A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device achieved in the securing of a necessary signal wiring route without depending on complicated structure and having high reliability in terms of the securement. <P>SOLUTION: The semiconductor device (1) is provided with a plurality of circuit blocks grasped by a semiconductor substrate as an aggregate of a plurality of circuit cells. One part of the plurality of circuit cells are filler cells (40, 41 and 42) arranged to form power supply routes between the circuit cells while the first filler cells (40, 42) connected to the power supply routes with a power supply stabilization capacity and the second filler cell (41) excluding the power supply stabilization capacity from the first filler cells are provided as the filler cells. The second filler cell is employed at a place (35) where wiring is conjested, whereby necessary signal wiring routes can be secured without depending on the complicated structure. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to optimization of wiring properties in a semiconductor device, for example, a technique applicable to a semiconductor device incorporating a plurality of circuit blocks having different operating frequencies.

  In designing a semiconductor device, a macro cell or a standard cell is used as a circuit component. The macro cell is layout data that has already been verified in a large functional unit such as a CPU and a memory. Circuits that are not made into macrocells can be designed using standard cells. A standard cell is a circuit component of an element circuit such as an inverter, NAND gate, or OR gate, and a plurality of types of standard cells can be spread to achieve a required function.

  In addition, there is a filler cell that is a cell that does not have a predetermined logical function but has a wiring layer or the like, while the standard cell and the macro cell have a predetermined logical function.

  This filler cell is arranged in a gap generated between the standard cells arranged, and power supply is not interrupted in the gap. Patent Document 1 describes a connection form of a plurality of wiring layers to a power source / ground. The selective use of different types of filler cells is described.

JP 2004-158532 A

  The present inventor examined the wiring property in a circuit area designed using a standard cell or the like as follows. (1) The inventor examined the use of a filler cell incorporating a power supply stabilization capacity (decoupling capacity). It has been clarified that if such a filler cell is embedded in a gap generated between standard cells, the wiring property may be deteriorated. For example, when the filler cell includes a p-channel MOS capacitor as a decoupling capacitor, a lead-out wiring and a contact for connecting a power supply wiring to the source and drain of the MOS transistor constituting the MOS capacitor and a ground wiring at the gate Lead wires and conductors for connection must be included, and they may interfere with the arrangement of signal wires that connect circuits arranged before and after the filler cell. This reinforces the cell placement and further changes the cell itself. (2) When power supply and power supply stop for a circuit block constituting a predetermined functional unit can be selected by a power switch, a power supply cell and a power switch cell are arranged around the circuit block, and power supply to the power supply cell is performed by the power switch. It can be controlled by a cell switch. However, if the power supply cell simply defines the power supply / ground wiring pattern and the interlayer contact pattern regularly, it may be difficult to pass the external signal wiring connected to the circuit block while avoiding the power supply cell pattern. Was found. (3) When the operating frequency is different among a plurality of circuit blocks, if the difference is not considered with respect to the number of power supply points from the power plane wiring to the circuit block and the capacitance value of the decoupling capacitance, It has been found that an undesirable voltage drop can cause malfunction.

  An object of the present invention is to provide a semiconductor device that can secure a necessary signal wiring path regardless of a complicated structure and has high reliability in this respect.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the semiconductor device (1) has a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate. A part of the plurality of circuit cells is a filler cell (40, 41, 42) arranged to form a power feeding path between the circuit cells, and the power source stable connected to the power feeding path as the filler cell The first filler cell (40, 42) having the control capacity and the second filler cell (41) in which the power stabilization capacity is deleted from the first filler cell. By using the second filler cell in the place (35) where the wiring is crowded, a necessary signal wiring path can be secured without depending on a complicated structure.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the semiconductor device, it is possible to secure a necessary signal wiring path regardless of a complicated structure, and high reliability can be realized in this respect.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] << Filler Cell >> A semiconductor device according to the present invention has a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate. A part of the plurality of circuit cells is a filler cell arranged to form a power feeding path between the circuit cells, and the first filler has a power stabilization capacitance connected to the power feeding path as the filler cell. It has a cell (40, 42) and a second filler cell (41) in which the power stabilization capacity is deleted from the first filler cell. By using the second filler cell in the place (35) where the wiring is crowded, a necessary signal wiring path can be secured without depending on a complicated structure.

  Further, when the first circuit block (32) having a relatively low synchronous operation frequency and the second circuit block (33) having a relatively high synchronous operation frequency are included, the first circuit block disposed in the first circuit block is provided. The filler cell has a p-channel MOS capacitor (MOSCp) as the power stabilization capacitor, and the first filler cell arranged in the second circuit block serves as a p-channel MOS capacitor (MOSCp) as the power stabilization capacitor. ) And an n-channel MOS capacitor element (MOSCn). In a circuit block with a high operating frequency, the charge / discharge cycle of the circuit node is short and the amount of charge / discharge per unit time increases, so it is a good idea to increase the power supply stabilization capacity per filler cell. .

  As another specific form of the present invention, when the first circuit block (33) having a relatively low operating power supply voltage and the second circuit block (36) having a relatively high operating power supply voltage are provided, The first filler cell disposed in the circuit block has a MOS capacitor element having a relatively thin gate insulating film as the power stabilization capacitor, and the first filler cell disposed in the second circuit block is the power stabilization A MOS capacitor element having a relatively thick gate insulating film is provided as the capacitor. The withstand voltage of the MOS capacitor element can be improved with respect to the filler cell of the circuit block having a high operating power supply voltage.

  << Power Feeding Cell / Power Switch Cell >> As another specific form of the present invention, another part of the plurality of circuit cells includes a plurality of power supply cells arranged in parallel to form a power feeding path in the corresponding circuit block. A power supply cell (53, 54), and as the power supply cell, a power supply cell (53, 54) having a relatively high power supply path element arrangement density and a power supply cell (53_R, 54_R, 53_RI) are mixed. In the place (36) where the external signal wiring connected to the circuit block is crowded, a power feeding cell having a relatively low density of power feeding path elements is adopted, so that the signal wiring can be easily avoided by avoiding the pattern of the power feeding cell. Can pass through.

  << Number of Power Supply Contacts >> As another specific form of the present invention, a power supply path formed by power supply cells in a circuit block having a high operating frequency is relatively high with respect to a contact (CTH) used for connection between adjacent wiring layers. A power supply path formed of power supply cells in a circuit block having a low density and a low operating frequency has a low density relative to a contact (CTH) used for connection between adjacent wiring layers. A relatively large current supply can be guaranteed for a circuit block having a high operating frequency, and malfunction due to an undesired voltage drop in the power supply voltage can be prevented.

  [2] << Filler Cell; Stabilization Capacitance Arrangement Density >> In a semiconductor device according to another aspect of the present invention, a part of the plurality of circuit cells is arranged to form a feeding path between the circuit cells. A plurality of filler cells, and the filler cells include a plurality of types of filler cells having different arrangement densities of power stabilizing capacitors. By using a filler cell having a small arrangement density of the power stabilization capacitors in a place where the wiring is crowded, a necessary signal wiring path can be ensured regardless of a complicated structure.

  << Filler Cell; Correlation Between Wiring Density and Stabilized Capacitance Arrangement Density >> In a semiconductor device according to still another aspect of the present invention, a part of the plurality of circuit cells forms a feeding path between the circuit cells. It is a plurality of filler cells arranged. The filler cell having a relatively high wiring density has a power stabilization capacity connected to the power supply path at a relatively low density, and the filler cell having a relatively low wiring density is connected to the power supply path. Having a relatively high density. By using a filler cell having a small arrangement density of power stabilization capacitors in a place having a high wiring density, a necessary signal wiring path can be ensured without depending on a complicated structure.

  [3] << Power Supply Cell / Power Switch Cell >> A semiconductor device according to another aspect of the present invention has a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate. A part of the plurality of circuit cells is a plurality of power supply cells (53, 54) arranged in parallel to form a power supply path in the corresponding circuit block, and the power supply path element is relatively arranged as the power supply cell. A power supply cell (53_R, 53_RI, 54_R) having a relatively low power supply path element placement density is mixed. In locations where external signal wiring connected to the circuit block is crowded, by adopting a power feeding cell with a relatively low density of power feeding path elements, the signal wiring can be easily routed avoiding the power feeding cell pattern. it can.

  As one specific form of the present invention, a power supply cell (53, 53_R, 53_RI) in a part of the plurality of power supply cells performs power supply to or stops power supply to a power supply path formed by the plurality of power supply cells. A power switch (Q2n) to be selected is included. By selectively stopping the power supply to the circuit block whose operation should be stopped, it contributes to low power consumption.

  As a more specific form of the present invention, the power supply cell is arranged around a corresponding circuit block, and the power supply cell (53, 53_R, 53_RI) having the power switch is a plurality of circuit cells in the corresponding circuit block. It arrange | positions at the both ends of the electric power feeding path extended in the juxtaposed direction. The power supply cells arranged around the circuit block also function as a barrier for suppressing external noise. Good power supply efficiency to the circuit cells is achieved by arranging the power supply cells having the power switch cells at both ends of the power supply path extending in the parallel arrangement direction of the plurality of circuit cells. If a power supply cell having a power switch is arranged in a direction crossing a power supply path extending in the direction in which a plurality of circuit cells are arranged in parallel, the power supply path is frequently routed and the power supply efficiency is lowered.

  As a more specific form of the present invention, a power supply path formed of power supply cells in a circuit block having a high operating frequency has a high density relative to a contact (CTH) used for connection between adjacent wiring layers. A power supply path formed by power supply cells in a low-frequency circuit block has a low density relative to contacts (CTH) used for connection between adjacent wiring layers. A relatively large current supply can be guaranteed for a circuit block having a high operating frequency, and malfunction due to an undesired voltage drop in the power supply voltage can be prevented.

  [4] << Number of Power Supply Contacts >> A semiconductor device according to another aspect of the present invention has a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate, and is a circuit cell in a circuit block having a high operating frequency. The formed power supply path has a relatively high density with respect to contacts (CTH) used for connection between adjacent wiring layers, and the power supply path formed by circuit cells in a circuit block having a low operating frequency is connected between adjacent wiring layers. It has a low density relative to the contact (CTH) used for connection. A relatively large current supply can be guaranteed for a circuit block having a high operating frequency, and malfunction due to an undesired voltage drop in the power supply voltage can be prevented.

  [5] The semiconductor measure of the present invention according to another aspect related to the item [1] includes a first circuit block that operates in synchronization with a clock having a first synchronous operation frequency on the semiconductor substrate, and the first synchronous operation. And a second circuit block that operates in synchronization with a clock having a second synchronous operation frequency higher than the frequency. The first circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feeding path is formed between the transistor rows, and the power feeding route is provided in the region. A p-channel type MOS capacitor element is provided as a power source stabilization capacitor connected to. The second circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feed path is formed between the transistor rows, and the power feed route is provided in the region. A p-channel MOS capacitor and an n-channel MOS capacitor are used as power supply stabilization capacitors connected to.

  According to still another aspect of the present invention, there is provided a semiconductor device comprising: a first circuit block that operates in synchronization with a clock having a first synchronous operation frequency; and a second synchronization that is higher than the first synchronous operation frequency. And a second circuit block that operates in synchronization with a clock having an operating frequency. The first circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feeding path is formed between the transistor rows, and the power feeding route is provided in the region. A MOS capacitor element having a relatively thin gate insulating film is provided as a power source stabilizing capacitor connected to the. The second circuit block includes, between the arranged transistor rows, a region where the arrangement density of the transistors is lower than that of the transistor row and forms a power feeding path between the transistor rows, and the power feeding path is provided in the region. A MOS capacitor element having a relatively thick gate insulating film is provided as a connected power source stabilization capacitor.

  Further, according to another aspect of the semiconductor measure of the present invention, a circuit is formed on a semiconductor substrate by an arrangement of a plurality of transistors and a power supply path, and the arrangement density of transistors is lower between the arranged transistor rows than the transistor rows and A region for forming a power supply path is provided between the transistor arrays, the partial region includes a power supply stabilization capacitor connected to the power supply path, and the other region does not include a stabilization capacitor. In addition, one power supply path region arranged to form a power supply path in the circuit is an area where the arrangement density of the power supply path elements is high, and the other power supply path area is a region of the power supply path element than the one power supply path region. The area is low in arrangement density.

2. Details of Embodiments Embodiments will be further described in detail.

<Microcomputer>
FIG. 2 illustrates a microcomputer according to an example of the present invention. The microcomputer (MCU) 1 includes a central processing unit (CPU) 2 that executes instructions, a data transfer controller (DTC) 3, a RAM 4, and a flash memory (FLASH) 5.
Although not particularly limited, these circuits are commonly connected to an internal bus (IBUS) 7, and the internal bus 7 is connected to a peripheral bus (PBUS) 11 via a bus state controller (BSC) 10. The peripheral bus 11 includes an interrupt controller (INTC) 13, an A / D converter (A / D) 14 that converts an analog signal into a digital signal, and a D / A converter (D / A) that converts a digital signal into an analog signal. ) 15, serial communication interface circuit (SCI) 16, timer (TMR) 17, input / output port (PRT1) 18, input / output port (PRT2) 19, clock pulse generator (CPG) 20, and other circuits (MDL) 21 Is connected. A system controller (SYSC) 22 inputs a reset signal RES and a mode signal MD and determines an operation mode of the microcomputer. The RAM 4 has a work area for the CPU 2 and the FLASH 5 has a rewritable program and data for the CPU 2.

  The CPG 20 receives an external clock CLK or an oscillation clock generated by resonance of a crystal resonator (not shown), and outputs internal clock signals CK1 and CK2, for example. The clock frequency is CK1> CK2, and the high-frequency clock signal CK1 is a synchronization reference clock of a circuit represented by the CPU 22 connected to the internal bus IBUS. The low frequency clock signal CLK2 is used as a synchronous clock signal of a circuit represented by SCI16 connected to the peripheral bus PBUS. Both clock signals CK1 and CK2 are supplied to the BSC 10.

  FIG. 1 schematically shows a layout configuration of a microcomputer formed on a semiconductor substrate according to an example of the present invention. Here, the microcomputer 1 is shown in a chip state. Bonding pads (BP) 30 are disposed on the semiconductor substrate at the peripheral edge of the chip, and input / output buffers connected to the bonding pads 30 are formed in the IO region (IO) 31. Inside, there is a low speed operation region (LSO) 32 in which a circuit that operates in synchronization with the clock signal CKCK2 is formed, and a high speed operation region (HSO) 33 in which a circuit that operates in synchronization with the clock signal CK1 is formed. . In the low speed operation region (LSO) 32, a power source separation region (PSS) 34 in which the supply of power is selectively cut off is shown. Reference numeral 35 denotes a wiring congestion area (SLC) having a large number of wiring passing lines in the low speed operation area 32. Reference numeral 36 denotes a wiring congestion area (SLC) having a large number of wiring passing lines in the power source separation area 34. Reference numeral 36 denotes an analog circuit area (ANL) such as A / D 14 and D / A 15.

FIG. 4 schematically shows the types of wiring layers and their extending directions in the microcomputer 1. The metal wiring layer made of aluminum or the like has a multilayer structure of M1 to PM, and an insulating layer is formed between the wiring layers.
The semiconductor substrate side on which the wells and the like are formed is on the bottom, and the wiring layer PM is on the top side.

  The even-numbered metal wiring layers M2, M4, and M6 and the odd-numbered metal wiring layers M1, M3, M5, and M7 are wired in the chip so as to be orthogonal to each other. In FIG. 4, the illustration of the metal wiring layer M1 is omitted.

  The uppermost metal wiring layer PM is mainly used for a power supply plane, for example, a power plane that receives a power supply voltage from an external terminal and a ground plane that receives a ground voltage from an external terminal. The uppermost metal wiring layer PM is formed wider than the wiring patterns of the other wiring layers. This is because it is used as a power supply plane.

  As illustrated in FIG. 5, the wiring layer PM is sequentially conducted to the corresponding lower wiring layer through the contact holes. Details of FIG. 5 will be described later.

《Filler cell》
As described in the conventional example, a filler cell is a standard cell or macro cell that has a semiconductor element that achieves a predetermined logical function such as a transistor, but does not have a predetermined logical function. On the other hand, it refers to a cell that does not perform logic processing and output an output signal. In other words, the cell does not have a transistor that changes in accordance with an input signal, and is a cell provided with a wiring and a capacitor. The filler cell is arranged in a gap generated between the standard cells and the macro cells arranged so that power supply between the standard cells is not interrupted by the gap. That is, there is a region in which capacitors and wirings are provided between the transistors constituting the standard cell and the macro cell.

  In FIG. 1, 40 and 41 are filler cells mainly employed in the low speed operation region 32, and 41 and 42 are filler cells mainly employed in the high speed operation region 33.

  The filler cells 40, 41, and 42 correspond to the circuit cells used to fill the gaps generated between the circuit cells when circuit cells such as standard cells are arranged in the placement and wiring design. In the filler cells 40, 41, 42, for example, the upper half of the region having the same height as the standard cell is an n-type well region NWEL and the lower half is a p-type well region PWEL. A pattern VPTN is formed, and a ground pattern GPTN is formed at the lower end of the p-type well region PWEL.

  The filler cell 40 (first filler cell) has a p-channel MOS capacitor element MOSCp as a decoupling capacitor. In the p-channel type MOS capacitor element MOSCp, the source and drain of the n-type well region NWEL are contact holes (through holes or vias in this specification) in the lead portion DRW_VPT of the power supply pattern VPTN formed by the first-layer metal wiring M1. The pattern of the same layer as that used for the gate electrode of the p-channel MOS coupled with CTH is formed in the contact hole in the lead portion DRW_GPTN of the ground pattern GPTN formed by the first-layer metal wiring M1. Combined with CTH. The filler cell 41 (second filler cell) does not include the p-channel type MOS capacitor element MOSCp with respect to the filler cell 40, and therefore there is no extraction part DRW_VPT of the power supply pattern VPTN and extraction part DRW_DPTN of the ground pattern GPTN. . When the signal wiring SIG formed of the first-layer metal wiring M1 is formed on the filler cell 40 in the same direction as the power supply pattern VPTN, the signal wiring SIG is connected to the lead part DRW_VPT of the power supply pattern VPTN and the ground pattern GPTN. It must pass through the area between the drawers DRW_DPTN. In the figure, only the signal wiring SIG passes through three lines. Even when the signal wiring SIG is to be formed in a wiring layer different from the patterns GPTN and VPTN, as shown in FIG. 5, the contact has a structure in which a plurality of metal wirings are connected at the same position. Become. In addition, wiring patterns are routed between different wiring layers, the structure becomes complicated, and the variation in wiring length increases. On the other hand, in the case of the filler cell 41, since there is no pattern of the lead-out portions DRW_VPT and DRW_DPTN due to the absence of the decoupling capacitance MOSCp, seven wiring lines using the same wiring layer as the patterns VPTN and GPTN are used on the filler cell 41. The signal line SIG can be passed. Therefore, by using the filler cell 41 instead of the filler cell 40 in the wiring congestion area (SLC) 35 in a place where the wiring is crowded, it is possible to pass many signal wirings. It is possible to secure a necessary signal wiring path without a complicated structure. FIG. 3 (FIG. 8-1 of the inventor's drawing sheet 2 in the present correction) illustrates a state in which filler cells 40 and 41 are mixed and arranged in the low frequency region. In FIG. 3, required circuit cells are arranged in the hatched area. The filler cells 40 and 41 are positioned as circuit cells that fill the gaps.

  As shown in FIG. 18, in the low frequency region between the standard cell A and the standard cell B, for example, by using the filler cell 41 between the two standard cells, the signal wiring can be passed over a short distance. On the other hand, since there is no filler cell 41 in the past, it is necessary to pass signal wiring while bypassing not only the filler cell between the standard cells A and B but also the cells above and below the drawing. Wiring has become complicated. Considering the operating characteristics in the low frequency range, that is, giving priority to signal wiring delay over decoupling capacitance.

  A filler cell 41 that allows more wiring to pass than filler cells 40 and 42 with a decoupling capacity is employed.

  Next, as shown in FIG. 19, the filler cells are arranged in the high frequency region. In the high frequency region, since the operating frequency is high, stabilization of the voltage of the power supply wiring is emphasized, and many filler cells 40 having a decoupling capacity are employed as filler cells.

  Next, as another example of the high-frequency region, an example in which many filler cells 42 are used is shown in FIG.

  The filler cell 42 includes an n-channel MOS capacitor element MOSCn in addition to the p-channel MOS capacitor element MOSCp. The n-channel MOS capacitor element MOSCn has a source / drain of the p-type well region PWEL coupled to the lead portion DRW_GPT of the ground pattern GPTN formed by the first-layer metal wiring M1 through a contact hole CTH, and the gate of the p-channel MOS transistor A pattern of the same layer as the layer used for the electrode is coupled to the lead portion DRW_VPTN of the power supply pattern VPTN through a contact hole CTH. When the gate insulating film is made equal between the p-channel type MOS and the n-channel type MOS, the p-channel type MOS capacitor element MOSCp generally tends to have a smaller leakage current between the gate and the substrate than the n-channel type MOS capacitor element MOSCn. is there. In this respect, in the filler cell 40, it is advantageous to employ the p-channel type MOS capacitor element MOSCp as a decoupling capacitor. Each filler cell 42 has a capacity value larger than that of the filler cell 40. In the high-speed operation region 33 in which a circuit block having a high operating frequency is formed, the charge / discharge cycle of the circuit node is short and the amount of charge / discharge per unit time is large. Therefore, power supply stabilization per filler cell is performed there. It is advantageous to use a filler cell 42 having a large capacity.

  The analog circuit area 36 is operated at a higher power supply voltage than the other circuit areas in the same manner as the IO area. When a circuit block having a relatively low operating power supply voltage formed in the high-speed operating region 33 and the like and a block having a relatively high operating power supply voltage formed in the analog circuit region 36 are provided, It is desirable that the disposed filler cells are formed so that the gate insulating films of the MOS capacitance elements MOSCp and MOSCn are relatively thicker than the filler cells 40, 41 and 42. This is to improve the breakdown voltage of the MOS capacitor element with respect to the filler cell of the circuit block having a high operating power supply voltage.

  The difference between the filler cells 40 to 42 can be grasped as a difference in the relative arrangement density of the decoupling capacitance. 42 can be grasped as a filler cell having a relative arrangement density of decoupling capacity of 2, a filler cell having a relative arrangement density of decoupling capacity of 1, and 41 a filler cell having a relative arrangement density of decoupling capacity of 0. . Therefore, the number of decoupling capacities possessed by one filler cell is not limited to the above, and may be appropriately determined according to the cell size.

  Further, when viewed from a semiconductor device finished as a chip such as a microcomputer, the boundary of each cell is not known. However, when this embodiment is viewed from a semiconductor device, it appears as a difference in density in which MOS capacitance elements are provided between transistors constituting standard cells and macrocells. That is, it can be said that the capacity element density provided between the transistors in the low speed operation region 32 is lower than the capacity element density provided between the transistors in the high speed operation area 33. Further, when the density of the N-type and P-type MOS capacitors provided between the transistors in the low-speed operation region 32 is lower than the density of the N-type and P-type MOS capacitors provided between the transistors in the high-speed operation region 33, respectively. I can say that.

  Further, the difference between the filler cells 40 to 42 can be grasped as the relationship between the density of the wiring SIG (signal wiring density) and the density of the decoupling capacitance in the signal passing through the upper layer. For example, the filler cell 41 having a relatively high signal wiring density has a relatively low decoupling capacity, and the filler cells 40 and 42 having a relatively low signal wiring density have a relatively high decoupling capacity. Have in. By using a filler cell having a small decoupling capacitance arrangement density in a place having a high signal wiring density, a necessary signal wiring path can be secured without using a complicated structure, as described above.

<Number of power supply contacts>
FIG. 1 shows a connection form by a contact hole CTH at an intersection between a wiring layer PM and a lower wiring layer M7 in a part of the low speed operation region 32, and a wiring layer PM and a lower wiring layer in the high speed operation region 33. The connection form by contact hole CTH in the cross | intersection part with M7 is shown.

  There is a difference in the connection form between a part of the low speed operation area 32 and the high speed operation area 33. That is, in the high speed operation region 33, the contact hole used for connection between the wiring layer PM and the lower wiring layer M7 is used for connection between the wiring layer PM and the lower wiring layer M7 in a partial region in the low speed operation region 32. The contact holes are arranged at a density higher than that of the contact holes. As a result, a relatively large current supply can be assured for circuit blocks having a high operating frequency such as the CPU 2 and RAM 4 formed in the high-speed operation region 33, and malfunction due to an undesired voltage drop in the power supply voltage can be prevented. be able to.

  Further, as shown in FIG. 1, in the low-speed operation region 32, the lower number of contacts decreases, so that the lower metal wiring layer, for example, M5a, which is the fifth metal wiring layer from the bottom, is passed between the contacts CTH1 and CTH2. It becomes possible. The same applies to M5b.

  Note that M5c is a fifth metal wiring layer that can be conventionally passed through regardless of the number of contacts.

  The contact has a structure that can usually be connected from the wiring layer PM to the lower wiring layers M7 to M1 with one contact. This can be understood from the sectional view of FIG.

  For this reason, a lower wiring layer that is not connected to the position of the contact via the contact is not arranged.

  As shown in FIG. A, since the number of contacts is reduced compared to the high-speed operation region 33, the distance X1 between the wiring layer M5a and the contact CTH1 and the wiring layer M5 are reduced from two to one here. The distance X2 of the contact CTH2 can be secured, and the wiring layer M5a can be passed.

  The number of contacts is not limited to one and two, but depends on the manufacturing method and the like. Compared to the high-speed operation region, the contact density of contacts that are the same potential or the same signal transmission path connecting the upper and lower metal wiring layers in a part of the low-speed operation region is low. As described above, in a part of the low-speed operation region 32, the number of contacts is reduced, so that the lower wiring layer can be passed more than the high-speed operation region 33.

  Note that the number of contacts may be reduced in the entire low-speed operation region 32, but the number of contacts may be increased in a region with few signal lines.

  As described above, in the high-speed operation region 33, since the contact density is higher than that in a part of the low-speed operation region 32, a stable voltage is supplied and the operation is stabilized.

  In addition, in a part of the low speed operation region 32, the contact density is lower than that in the high speed operation region 33, so that more lower layer wiring can be passed between the contacts than in the high speed operation region 33.

<< Power supply cell / Power switch cell >>
FIG. 6 schematically shows a circuit configuration in the power supply isolation region 34. The power source separation region 34 includes, for example, a logic circuit (LOG) 50 and a power switch 51 connected to the logic circuit. Here, a power switch circuit 51 is disposed between the ground voltage VSS and the logic circuit 50, and supply of operation power to the logic circuit 50 is selectively stopped by selectively cutting off the ground voltage VSS. In FIG. 6, a p-channel MOS transistor Q1p and an n-channel MOS transistor Q1n are representatively shown in the logic circuit. The power switch 51 is composed of an n-channel MOS transistor Q2n. The gate insulating film of the MOS transistor C2n is thicker than the MPOS transistors Q1n and Q1p. The power switch MOS transistor Q2n gives priority to the reduction of the subthreshold leakage current and the logic MOS transistors Q1n and Q1p to increase the operation speed. ing. The source potential of the n-channel MOS transistor Q1n is a virtual ground voltage VSSM. When the n-channel MOS transistor Q2n is turned on, the source potential is almost the ground voltage, and when the n-channel MOS transistor Q1n is turned off, the source potential is cut off from the ground voltage VSS. Current stops flowing. DNW means a region where a high-concentration N-type impurity is implanted under the PWEL when the PWEL potential is separately controlled from the semiconductor substrate (P-Sub) potential.

  FIG. 7 illustrates an array of a power cell 54 and a power switch cell 53 as a power supply cell used for supplying and shutting off operating power to a unit for shutting off the operating power by the power switch circuit. The power cell 54 has a wiring pattern that constitutes a power supply path of the power source. The power switch cell 53 has a switch for selectively cutting off the ground voltage and its control line in addition to the configuration of the power cell. In the unit of shutting off the operating power by the power switch circuit 51, the power cell 54 and the power switch cell 53 are used for supplying and shutting off the power supply voltage VDD, the virtual ground voltage VSSM, and the ground voltage VSS. The power cell 54 and the power switch cell 53 are laid out so as to surround the logic circuit (LOG) 50. The power switch cells 53 are arranged at both ends of a power supply path (a wiring pattern corresponding to VPTN and GPTN) extending in the direction in which the plurality of circuit cells 55 constituting the logic circuit 50 are arranged side by side (left and right in the figure). The By arranging the power switch cells 53 at both ends of the power supply path extending in the direction in which the plurality of circuit cells 55 are juxtaposed, good power supply efficiency to the circuit cells 55 is achieved. If the power switch cell is arranged in a direction intersecting the power supply path (wiring pattern corresponding to VPTN, GPTN) extending in the direction in which the plurality of circuit cells 55 are juxtaposed, the power supply path is increased and the power supply efficiency is reduced. To do.

  FIG. 8 schematically shows the connection relationship between the circuit cell 55 of the logic circuit 50 (LOG_A, LOG_B) and the switch MOS transistor Q2n of the power switch circuit 51 in a longitudinal sectional structure.

  As can be seen from FIG. 8, the power switch transistors Q2n are arranged between the logic circuits LOG_A and LOG_B.

Thus, the two logic circuits are adjacent to each other through the power switch.
That is, on the chip, the power switch and the logic circuit of the logic circuit which is folded and adjacent to the VSS wiring of FIG. 7 as an axis are arranged.

  FIG. 5 shows the vertical sectional structure of FIG. 8 in detail with the addition of metal wiring layers M1 to MP.

  FIG. 9 schematically illustrates the power supply pattern of the wiring layer PM in the entire microcomputer 1. 60 is a pattern of the wiring layer PM in the power supply trunk line of the input / output circuit, 61 is a pattern of the wiring layer PM in the power supply trunk line of the digital system circuit, and 62, 63 and 64 are wirings in the digital system power supply branch line of the individual power supply separation region 34. This is a pattern of the layer PM. 65 is a pattern of the wiring layer in the power supply trunk line of the analog system circuit, and 66 is a pattern of the wiring layer PM in the analog system power supply branch line.

  On the chip is an analog circuit area, a high frequency area where a CPU core is arranged, a low frequency area 1 which is a peripheral control logic circuit 1 that executes processing while exchanging signals with the CPU core and other peripheral control logic circuits, Similarly, a low frequency region 2 that is a peripheral control logic circuit 2 that executes processing while exchanging signals is shown.

  Each region is surrounded by a power supply wiring (VDD) and a ground wiring. In addition, power switches such as Q2n in FIG. 6 are arranged in the regions indicated by broken lines. As shown in FIG. 8, the two regions are adjacent to each other with a power switch.

  In FIG. 9, the pattern of the wiring layer PM corresponding to the power supply trunk line and the branch line is illustrated as a continuous pattern, but actually, as illustrated in FIG. 1, the pattern is separated into a predetermined rectangle and arranged in an array shape. . In this way, rectangular patterns having different voltages, for example, a rectangular pattern of the power supply voltage VDD and a rectangular pattern of the ground voltage VSS are alternately arranged in the wiring layer PM, or the rectangular pattern of the power supply voltage VDD and the virtual ground The rectangular pattern of the voltage VSSM and the rectangular pattern of the ground voltage VSS can be arranged alternately in the wiring layer PM, and the required voltage can be easily drawn to the internal logic circuit at an arbitrary position. Is possible.

  Here, the array configuration of the rectangular pattern of the wiring layer PM in the power cell and the power switch cell is a plurality of types having different pattern densities.

  As shown in FIG. 1, in the wiring congestion area 36 of the signal wiring, the power cell 54_R and the power switch cell 53_R having a low density of the rectangular pattern of the wiring layer PM are employed.

  Thus, the signal wiring can be easily routed while avoiding the pattern and contact hole under the power cell 54_R and the power switch cell 53_R.

  In the example of FIG. 1, if the power cell 54_R or the power switch cell 53_R having a low density of the rectangular pattern of the wiring layer PM is adopted, seven signal wirings SIG per cell are passed over the area of the cell. However, for the power cell 54 and the power switch cell 53 in which the density of the rectangular pattern of the wiring layer PM is higher than that, only one signal line SIG can be passed through each corresponding to the region between the rectangular patterns. Can not.

  In this embodiment, the stabilization of the power supply voltage is emphasized between the high frequency region and the low frequency region, and the bypass of the wiring is reduced between the low frequency region and the low frequency region. As a result, the performance of the entire chip was improved.

  The background is as follows. The standard cells can be efficiently spread by reducing the height of the standard cells (40, 41, 42 in FIG. 1, H as shown in FIG. 3), that is, by reducing the gate width of each cell transistor. Thought.

  On the other hand, when the height of the standard cell is lowered, it becomes difficult to pass the wiring crossing the horizontal direction of the standard cell. These contradictions are adjusted by the number of wires in the power switch region in consideration of the characteristics between the regions.

  That is, the length X1 at which the low frequency region 1 is in contact with the high frequency region in the power switch region is longer than the length Y at which the low frequency region 1 and the low frequency region 2 are in contact with each other.

  Thereby, when the low frequency region 1 is in the high frequency region, the contact length is long, so that many signal wirings can be passed between the low frequency region 1 and the high frequency region without affecting the power supply wiring.

  On the other hand, in the low frequency region 1 and the low frequency region 2, although the contact length is short, the power supply wiring is devised as shown below, so that the low frequency region 1 and the low frequency wave region 2 are Through many signal wiring. It is also possible to facilitate the passage of the signal wiring by thinning out the wiring layer below the power cell 54 and the power switch cell 53. The configuration of the power switch cell will be described below.

  FIG. 10 schematically shows patterns of the polysilicon wiring layer P0 and the metal wiring layer M1 of the power switch cell 53_RI. An impurity diffusion region 70 is used as a source / drain.

  FIG. 11 shows a via V2 for connecting the wiring of the polysilicon wiring layer P0, the metal wiring layers M1 and M2, and the contacts CT, M2 and M3 of the power switch cell 53_RI.

  FIG. 12 shows the metal wiring layers M3 and M4 of the power switch cell 53_RI and the via V3 connecting the wirings of the wiring layers M3 and M4. Since the VSSM and VSS power supply patterns formed in the wiring layer M3 are regularly arranged, only one signal wiring SIG can be passed between the power supply patterns in the wiring layer M3. At this time, as illustrated in FIG. 13, by reducing the power density of VSSM and VSS in the wiring layer M3 to reduce the wiring density, the number of signal lines SIG that can be passed through the wiring layer M3 is more than doubled. be able to. In this example, the VSSM and VSS power supply patterns of the wiring layer M3 are power supply path elements, FIG. 12 shows an example in which the density of such power supply path elements is high, and FIG. 13 shows an example in which the density is low. Yes.

  12 shows a power switch unit between the low frequency region 1 and the high frequency region, and FIG. 13 shows a power switch unit between the low frequency region 1 and the low frequency wave region 2.

  FIG. 14 shows the metal wiring layers M5 and M6 of the power switch cell 53_RI, the via V4 connecting the wirings of the wiring layers M4 and M5, and the via V5 connecting the wirings of the wiring layers M5 and M6. Since the VSSM and VSS power supply patterns formed in the wiring layer M5 are regularly arranged leaving a small area in the central portion, several signal wirings SIG in the wiring layer M5 are arranged in the area from the central diagram in the central portion. Can only pass. At this time, as illustrated in FIG. 15, the number of signal lines SIG that can be passed through the wiring layer M5 is more than doubled by thinning out the VSSM and VSS power supply patterns in the wiring layer M5 to reduce the wiring density. be able to. In this example, the VSSM and VSS power supply patterns of the wiring layer M5 are power supply path elements, FIG. 14 shows an example in which the density of such power supply path elements is high, and FIG. 15 shows an example in which the density is low. Yes.

  FIG. 14 shows a power switch part between the low frequency region 1 and the high frequency region, and FIG. 15 shows a power switch part between the low frequency region 1 and the low frequency wave region 2.

  FIG. 16 shows the metal wiring layers M6, M7, and PM of the power switch cell 53_RI, and the via PV connecting the wiring layers M7 and PM.

  FIG. 17 is a cross-sectional view taken along the line A-A ′ of FIG. 16. The portion of RR is a region where a part of the power supply pattern is thinned out to facilitate the signal wiring SIG.

  As described above, considering the characteristics between the low frequency region and the high frequency region, the length of the power switch unit that contacts the low frequency region and the high frequency region is the contact between the low frequency region and the low frequency region. It was longer than the length.

  In addition, the wiring density across the power switch between the low frequency region and the low frequency region is made higher than the density across the power switch between the low frequency region and the high frequency region.

  Thereby, in a chip having a high frequency region and a low frequency region, it is possible to reduce the detour of the wiring while ensuring the stabilization of the power supply as a whole chip.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, the number of wiring layers, the power supply cell, the circuit scale of the power switch cell, and the like can be changed as appropriate.

  Moreover, you may combine these content suitably. By combining them, it is possible to realize a stable supply of voltages in the high-speed operation region and the low-speed operation region and an uncomplicated signal wiring arrangement for the entire semiconductor device.

  The semiconductor device according to the present invention is not limited to a microcomputer, and can be widely applied to various logic LSIs, analog LSIs, digital / analog mixed LSIs, and the like.

It is a top view which shows roughly the layout-like structure of the microcomputer based on an example of this invention. It is a block diagram of a microcomputer according to an example of the present invention. It is a conceptual diagram which illustrates a mode that several filler cells from which a wiring density and the density of a decoupling capacity differ are mixed and arrange | positioned in a wiring congestion area | region. It is a perspective view which shows roughly the kind of wiring layer in a microcomputer, and its extending direction. It is a longitudinal cross-sectional view which illustrates the structure which connects a power cell and a power switch cell via the uppermost wiring layer PM. It is a circuit diagram which shows roughly the circuit structure in a power supply isolation | separation area | region. FIG. 3 is a circuit diagram illustrating an array of power cells and power switch cells used for supplying and shutting off operating power to a unit of shutting off operating power by a power switch circuit. It is a schematic sectional drawing which shows roughly the connection relation of the circuit cell of a logic circuit, and the switch MOS transistor of a power switch circuit by a longitudinal cross-section structure. It is a top view which illustrates roughly the power supply pattern of wiring layer PM in the whole microcomputer. It is a top view which shows typically the pattern of the polysilicon wiring layer P0 of the power switch cell 53_RI, and the metal wiring layer M1. It is a top view which shows the layout of polysilicon wiring layer P0, metal wiring layers M1, M2, etc. of power switch cell 53_RI. It is a top view which shows the layout of metal wiring layers M3, M4, etc. of the power switch cell 53_RI. 13 is a plan view illustrating a layout when the wiring density is lowered by thinning out the VSSM and VSS power supply patterns in the wiring layer M3 with respect to FIG. It is a top view which shows the layout of metal wiring layers M5, M6, etc. of the power switch cell 53_RI. 15 is a plan view illustrating a layout when the wiring density is lowered by thinning out the VSSM and VSS power supply patterns in the wiring layer M5 with respect to FIG. It is a top view which shows the layout of metal wiring layers M6, M7, PM, etc. of the power switch cell 53_RI. It is A-A 'sectional drawing of FIG. It is a top view which illustrates arrangement | positioning of the filler cell in a low frequency area | region. It is a top view which illustrates arrangement | positioning of the filler cell which has a pMOS decoupling capacitor in a high frequency area | region. It is a top view which illustrates arrangement | positioning of the filler cell which has pMOS and an nMOS decoupling capacitor in a high frequency area | region.

Explanation of symbols

1 Microcomputer (MCU)
2 Central processing unit (CPU)
3 Data transfer controller (DTC)
4 RAM
5 Flash memory (FLASH)
7 Internal bus (IBUS)
10 Bus state controller (BSC)
11 Peripheral bus (PBUS)
13 Interrupt controller (INTC) 13
14 A / D converter (A / D)
15 D / A converter (D / A)
16 Serial communication interface circuit (SCI)
17 Timer (TMR)
18, 19 I / O port (PRT1PRT2)
20 Clock pulse generator (CPG)
22 System Controller (SYSC)
CK1, CK2 Internal clock signal 30 Bonding pad (BP)
31 IO area (IO)
32 Low speed operation area (LSO)
33 High-speed operation area (HSO)
34 Power supply isolation area (PSS)
35, 36 Wiring congestion area (SLC)
40, 41, 42 Filler cell VPTN Power supply pattern GPTN Ground pattern MOSCp p-channel MOS capacitor MOSCn n-channel MOS capacitor 50 Logic circuit (LOG)
51 Power switch circuit Q2n Power switch MOS transistor VDD Power supply voltage VSSM Virtual ground voltage VSS Ground voltage 53 Power switch cell (power feeding cell)
54 Power cell
53_R, 53_RI Power switch cell with low power supply path arrangement density 54_R Power supply cell with low power supply path arrangement density

Claims (14)

The semiconductor substrate has a plurality of circuit blocks grasped as a set of a plurality of circuit cells, and a part of the plurality of circuit cells is a filler cell arranged to form a power feeding path between the circuit cells, As the filler cell, a semiconductor device having a first filler cell having a power stabilization capacity connected to the power supply path, and a second filler cell in which the power stabilization capacity is deleted from the first filler cell,
A first circuit block that operates in synchronization with a clock having a first synchronization operation frequency, and a second circuit block that operates in synchronization with a clock having a second synchronization operation frequency higher than the first synchronization operation frequency. And
The first filler cell disposed in the first circuit block has a p-channel MOS capacitor as the power stabilization capacitor, and the first filler cell disposed in the second circuit block is the power stabilization capacitor. A semiconductor device having a p-channel MOS capacitor element and an n-channel MOS capacitor element. A first circuit block that operates in synchronization with a clock having a first synchronous operation frequency on a semiconductor substrate, and a second circuit that operates in synchronization with a clock having a second synchronous operation frequency higher than the first synchronous operation frequency. 2 circuit blocks,
The first circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feeding path is formed between the transistor rows, and the power feeding route is provided in the region. A p-channel MOS capacitor element as a power source stabilization capacitor connected to
The second circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feed path is formed between the transistor rows, and the power feed route is provided in the region. A semiconductor device having a p-channel type MOS capacitor element and an n-channel type MOS capacitor element as a power source stabilization capacitor connected to. The semiconductor substrate has a plurality of circuit blocks grasped as a set of a plurality of circuit cells, and a part of the plurality of circuit cells is a filler cell arranged to form a power feeding path between the circuit cells, As the filler cell, a semiconductor device having a first filler cell having a power stabilization capacity connected to the power supply path, and a second filler cell in which the power stabilization capacity is deleted from the first filler cell,
A first circuit block that operates in synchronization with a clock having a first synchronization operation frequency, and a second circuit block that operates in synchronization with a clock having a second synchronization operation frequency higher than the first synchronization operation frequency. And
The first filler cell arranged in the first circuit block has a MOS capacitor element having a relatively thin gate insulating film as the power source stabilization capacitor, and the first filler cell arranged in the second circuit block is A semiconductor device having a MOS capacitor element having a relatively thick gate insulating film as the power source stabilizing capacitor. A first circuit block that operates in synchronization with a clock having a first synchronous operation frequency on a semiconductor substrate, and a second circuit that operates in synchronization with a clock having a second synchronous operation frequency higher than the first synchronous operation frequency. 2 circuit blocks,
The first circuit block includes a region between the arranged transistor rows, in which the arrangement density of the transistors is lower than that of the transistor row and a power feeding path is formed between the transistor rows, and the power feeding route is provided in the region. Having a MOS capacitor element having a relatively thin gate insulating film as a power source stabilizing capacitor connected to
The second circuit block includes, between the arranged transistor rows, a region where the arrangement density of the transistors is lower than that of the transistor row and forms a power feeding path between the transistor rows, and the power feeding path is provided in the region. A semiconductor device having a MOS capacitor element having a relatively thick gate insulating film as a connected power stabilization capacitor. The semiconductor substrate has a plurality of circuit blocks grasped as a set of a plurality of circuit cells, and a part of the plurality of circuit cells is a filler cell arranged to form a power feeding path between the circuit cells, As the filler cell, a semiconductor device having a first filler cell having a power stabilization capacity connected to the power supply path, and a second filler cell in which the power stabilization capacity is deleted from the first filler cell,
Another part of the plurality of circuit cells is a plurality of power supply cells arranged in parallel to form a power supply path in the corresponding circuit block, and the arrangement density of power supply path elements is relatively as the power supply cell. A semiconductor device in which power supply cells having high power density and power supply cells having relatively low power supply path element arrangement density are mixed. A semiconductor device in which a circuit is formed by an arrangement of a plurality of transistors and a power supply path on a semiconductor substrate,
Between the arranged transistor rows, there is a region where the arrangement density of the transistors is lower than that of the transistor row and a power feeding path is formed between the transistor rows, and the partial region is a power source connected to the feeding route With a stabilizing capacity, the other area does not have a stabilizing capacity,
One power supply path region arranged to form a power supply path in the circuit is a region in which the power supply path element is disposed at a higher density, and the other power supply path region is disposed at a density higher than that of the one power supply path region. A semiconductor device in which the area is low.   The power supply path formed by the power supply cells in the circuit block having a high operating frequency has a high density relative to the contacts used for connection between adjacent wiring layers, and is formed by the power supply cells in the circuit block having a low operation frequency. 6. The semiconductor device according to claim 5, wherein the power supply path has a low density relative to contacts used for connection between adjacent wiring layers. Having a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate;
A part of the plurality of circuit cells is a plurality of filler cells arranged to form a power feeding path between the circuit cells, and the filler cells are a plurality of types of filler cells having different arrangement densities of power stabilization capacitors. A semiconductor device. Having a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate;
A part of the plurality of circuit cells is a plurality of filler cells arranged to form a power feeding path between the circuit cells, and the filler cell having a relatively high wiring density is connected to the power feeding path. A semiconductor device having a stabilization capacity at a relatively low density, and the filler cell having a relatively low wiring density has a power stabilization capacity connected to the power supply path at a relatively high density. Having a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate;
Some of the plurality of circuit cells are a plurality of power supply cells arranged in parallel to form a power supply path in the corresponding circuit block, and the power supply cell has a relatively high arrangement density of power supply path elements. A semiconductor device in which power supply cells having a relatively low arrangement density of power supply path elements are mixed with power supply cells.   The semiconductor device according to claim 10, wherein some of the plurality of power supply cells include a power switch that selects power supply to the power supply path formed by the plurality of power supply cells or power supply stop.   The power supply cell is disposed around a corresponding circuit block, and the power supply cell having the power switch is disposed at both ends of a power supply path extending in a parallel arrangement direction of a plurality of circuit cells in the corresponding circuit block. The semiconductor device according to claim 11.   The power supply path formed by the power supply cells in the circuit block having a high operating frequency has a high density relative to the contacts used for connection between adjacent wiring layers, and is formed by the power supply cells in the circuit block having a low operation frequency. The semiconductor device according to claim 10, wherein the power supply path has a low density relative to a contact used for connection between adjacent wiring layers. Having a plurality of circuit blocks grasped as a set of a plurality of circuit cells on a semiconductor substrate;
A power supply path formed by circuit cells in a circuit block having a high operating frequency has a relatively high density for contacts used for connection between adjacent wiring layers, and is formed by circuit cells in a circuit block having a low operating frequency. The power supply path is a semiconductor device having a low density relative to a contact used for connection between adjacent wiring layers.

Images