JP2008243896A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of changing a resistance value of a power source resistor and a capacitance value of decoupling at a minimum cost. <P>SOLUTION: In the structure of Fig.6(A), a metal laminate composed of three layers which contact with a polysilicon layer PL are formed at the left end, the right end, and the middle point of the polysilicon layer PL, respectively. On the third metal layer M3 of the metal laminate at the middle point of the polysilicon layer PL, a via contact part is formed with a power source line 9 composed of a fourth metal layer and formed in contact with the via contact part. Thus, almost a half of the polysilicon layer PL is inserted in the power source line 9 as a power source resistor R. In the structure of Fig.6(B), a via contact part is formed on the third metal layer M3 of the metal laminate on the left end of the polysilicon layer PL with the power source line 9 composed of the fourth metal layer and formed in contact with the via contact thereon. Thus, almost the entire polysilicon layer PL is inserted in the power source line 9 as the power source resistor R. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which countermeasures against electromagnetic interference noise are taken.

  The market for semiconductor integrated circuits is wide-ranging, including PCs, mobiles, digital home appliances, cars / aircrafts, and medical / bio equipment. As semiconductor microfabrication technology evolves, it is becoming larger and operating frequency and power consumption are increasing. For this reason, a change in current generated from the LSI chip radiates electromagnetic waves into the space through a package (hereinafter referred to as PKG), a printed circuit board (hereinafter referred to as PCB, PCB is an abbreviation of printed circuit board), or the like. Hereinafter, EMI, which is an abbreviation for electromagnetic interference, is becoming a problem [see Non-Patent Documents 1-7].

  EMI noise is divided into two problems: interference between devices caused by being radiated to the outside of an electronic device or influence on a human body, and malfunction of a circuit due to interference between LSIs inside the device. The former only requires countermeasures on the outside such as shielding of the casing and equipment, but the latter requires countermeasures with a chip, PKG, and PCB. For example, in-vehicle LSIs are equipped with functions for controlling radio, audio, navigation, etc., so it is necessary to prevent interference of frequencies used for them.

Conventionally, EMI noise has been reduced by a power supply resistor inserted into a power supply line in a chip and a power-to-ground capacitance (hereinafter referred to as a decoupling capacitance) inserted between the power supply line and the ground line. .
"EMI noise analysis under ASIC design environment" IEEE Trans. Computer-Aided Design, vol. 19, no. 11, pp. 1337-1346, Nov. 2000. "EMI noise analysis by gate level simulator" Proc. ISQED, pp. 129-136, Mar. 2000. "Electromagnetic radiation and simultaneous switching noise in CMOS device packages" Proc. Electronic Components and Technology Conf., Pp. 781-785, May 2000. "Power bus decoupling on multilayer printed circuit boards" IEEE Trans. Electromagnetic Compatibility, vol. 37, no. 2, pp. 155-166, May 1995. "Analysis of radiation from PCBs and related structures based on SPICE" Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 320-325, Aug. 1996. "Specify parameters for power supply current model of LSI and EMI noise simulation of digital PCB" Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 1185-1190, Aug. 2001. "Power supply current modeling of IC / LSI for EMI noise simulation with load dependency" Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 16-21, Aug. 2003.

  The EMI noise varies depending on the values of the power supply resistance and the decoupling capacitance. According to the result of the circuit simulation performed by the present inventor, the EMI noise increases when the resistance value of the power supply resistance is small, and a voltage drop is caused when the resistance value is large. Further, the decoupling capacitance is a certain value, and EMI noise is increased by resonance. That is, prediction by analysis is important for reducing EMI noise.

  However, in the semiconductor integrated circuit manufactured based on the prediction, the resistance value of the power supply resistor and the capacitance value of the decoupling capacitor may not be the estimated values. For this reason, there are cases where measures for reducing EMI noise are incomplete at the prototype stage of the semiconductor integrated circuit, and the resistance value of the power supply resistor and the capacitance value of the decoupling capacitance are desired to be changed.

  Generally, in that case, enormous costs are required due to many mask changes. The semiconductor process proceeds in the order of gate poly, first metal layer, second metal layer,. As the process returns to the first step, the cost for correction is required. In other words, when the characteristics are not ideal in the first trial manufacture, the number of masks to be changed is as small as possible, and the cost of the upper layer mask change that has advanced the process steps as much as possible can be reduced.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can change the resistance value of the power supply resistor and the capacitance value of the decoupling capacitor at a minimum cost in order to reduce EMI noise.

  The semiconductor integrated circuit of the present invention comprises a power supply line, a circuit that receives supply of a power supply potential from the power supply line, and a power supply resistor inserted into the power supply line, and the power supply line is formed on the power supply resistor, The position of a via contact connecting the power supply resistor and the power supply line is changed by a via formation mask.

  The semiconductor integrated circuit according to the present invention includes a power supply line, a circuit that receives supply of a power supply potential from the power supply line, a power supply resistor inserted into the power supply line, and a plurality of via contact portions connected to the power supply resistance. The power supply line is formed on the power supply resistor, and a position where the power supply line is connected to any one of the plurality of via contact portions is changed by the mask for forming the power supply line.

  In addition to the above configuration, the semiconductor integrated circuit of the present invention includes a ground line for supplying a ground potential to the circuit, and a decoupling capacitor formed between the power supply line and the ground line, The decoupling capacitor includes a first capacitor electrode connected to the ground line, and a second capacitor electrode disposed opposite to the first capacitor electrode, and the power supply line and the ground line The presence or absence of a via contact connecting any one of the second capacitor electrodes is changed by a mask for forming a via contact.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of changing the resistance value of the power supply resistor and the capacitance value of the decoupling capacitor at a minimum cost in order to reduce EMI noise.

  A semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a printed circuit board 1 (hereinafter referred to as PCB), a package 2 (hereinafter referred to as PKG), and a chip 3 around a crystal oscillation circuit as an example of a semiconductor integrated circuit. This is an example of PKG using a QFP (quad flat package) wire bond. The crystal oscillator 4 is attached outside the PKG 2. The circuit in the chip 3 uses an input / output circuit (I / O) 5 connected to a pad related to the oscillation circuit and a part of the internal circuit block 6. Pad PD corresponding to input signal XIN, output signal XOUT from crystal oscillator, 3.3V power supply voltage XV33, ground voltage (ground voltage) XVSS, 1.2V power supply voltage V12 connected to other circuits, ground voltage VSS Is provided. Each pad PD is connected to the lead 8 of the PKG 2 through the bonding wire 7. The ground is common on the PCB, but is separated in the chip 3 and the PKG 2.

  FIG. 2 shows a circuit around the crystal oscillation circuit in the chip 3. Actually, it is composed of circuits such as a protection element, a transfer gate, and a level shifter, but is simplified. Generally, the main power supply used for crystal oscillation (3.3V in this analysis) is separated from the power supplies used for other input / output circuits. Using this feature, only circuits directly related to crystal oscillation are used. Although the EMI noise is related to a change in current, the ground current is a combination of other circuits, and therefore, in the EMI noise analysis, the evaluation is performed using the current on the power supply side.

  In this circuit, a power supply resistor R is inserted in series in the power supply line 9 supplied with the power supply voltage XV33. A decoupling capacitor Cd is connected between the power line 9 and the ground line 10 to which the ground voltage XVSS is supplied. An input signal from the crystal oscillator is input to the first input terminal of the NAND circuit 11 that functions as an XIN amplifier. An oscillation control signal is applied to the second input terminal of the NAND circuit 11. The output of the NAND circuit 11 is input to the internal circuit block 6 through the inverter 12. The NAND circuit 11 and the inverter 12 are connected to the power supply line 9 and the ground line 10 and are supplied with the power supply voltage XV33 and the ground voltage XVSS.

According to the result of the circuit simulation performed by the present inventor for the semiconductor integrated circuit, the current gain in the power supply pad decreases as shown in FIG. As the current gain decreases, so does the EMI noise. on the other hand,
Increasing the resistance value of the power supply resistor R causes a voltage drop of the power supply line 9 through the power supply resistor R as shown in FIG. Further, as shown in FIG. 5, the decoupling capacitance Cd causes an increase in current gain, that is, an increase in EMI noise due to resonance at a certain value.

  Accordingly, the present invention provides a semiconductor integrated circuit that can change the resistance value of the power supply resistor R and the capacitance value of the decoupling capacitor Cd at a minimum cost in order to reduce EMI noise. For the power supply resistor R, the position of the via contact portion connected to the power supply line 9 is changed by a via formation mask or a power supply line formation mask. For the decoupling capacitor Cd, the potential applied to the capacitor electrode via the via contact portion is changed by the via mask. Hereinafter, specific configurations of the power supply resistor R and the decoupling capacitor Cd will be described.

[Configuration of power supply resistor R]
As shown in FIG. 6, in a four-layer metal process, a polysilicon layer PL is formed on a P-type semiconductor substrate 21, and a first metal layer M1, a second metal layer M2, a third metal layer M3, Four metal layers M4 are formed in order via the interlayer insulating film 22, respectively. These metal layers can be connected to each other through plugs embedded in vias formed in the interlayer insulating film 22.

  In the structure of FIG. 6A, on the left end, the right end, and the middle point of the polysilicon layer PL, three layers of metal stacks (M1, M2, M3 and plugs connecting them) in contact with the polysilicon layer PL. ) Are formed. A via contact portion including the via 23 and the plug 24 embedded in the via 23 is formed on the uppermost third metal layer M3 of the metal stacked portion on the middle point of the polysilicon layer PL, and the first contact is formed thereon. A power supply line 9 made of four metal layers is formed in contact with the via contact portion. According to this structure, almost half of the polysilicon layer PL is inserted into the power supply line 9 as the power supply resistance R.

  In the structure of FIG. 6B, a via contact portion including the via 23 and the plug 24 embedded in the via 23 is formed on the uppermost third metal layer M3 of the metal stacked portion on the left end of the polysilicon layer PL. A power line 9 made of a fourth metal layer is formed on the via contact portion thereon. According to this structure, almost all of the polysilicon layer PL is inserted into the power supply line 9 as the power supply resistance R. The resistance value of the power supply resistor R is about twice that of the structure shown in FIG.

  As described above, the resistance value of the power supply resistor R can be made variable simply by changing the position of the via contact that connects the power supply resistor R and the power supply line 9 with the via forming mask. Further, since only one mask is changed and the mask of the uppermost via is changed, the cost can be minimized.

  In the above structure, the via forming mask is changed, but the power line 9 forming mask as the fourth metal layer may be changed. As shown in FIG. 7, three layers of metal stacks (M1, M2, M3 and plugs connecting them) in contact with the polysilicon layer PL are disposed on the left end, the right end, and the middle point of the polysilicon layer PL. Form each one. Further, via contacts 23 formed of the vias 23 and the plugs 24 embedded in the vias 23 are respectively formed on the third metal layer M3 of the metal stacked portions.

  Then, in the structure shown in FIG. 7A, the power supply line 9 is connected to the metal laminated portion on the intermediate point of the polysilicon layer PL. Therefore, according to this structure, almost half of the polysilicon layer PL is inserted into the power supply line 9 as the power supply resistance R.

  Further, as shown in FIG. 7B, the power supply line 9 is connected to the metal laminated portion on the left end of the polysilicon layer PL and is not connected to the metal laminated portion on the intermediate point of the polysilicon layer PL. . According to this structure, almost all of the polysilicon layer PL is inserted into the power supply line 9 as the power supply resistance R. The resistance value of the power supply resistor R is about twice that of the structure shown in FIG.

  As described above, the resistance value of the power supply resistor R can be made variable simply by changing the position of the via contact connecting the power supply resistor R and the power supply line 9 with the mask for forming the power supply line. Further, since only one mask is changed and the mask of the uppermost metal is changed, the cost can be minimized.

  In the above-described embodiment, an example of a four-layer metal process has been described. However, the present invention is not limited to this, and can be widely applied to single-layer metal and multilayer metal in general.

[Decoupling capacitance Cd]
As shown in FIG. 8, in a four-layer metal process, a gate polysilicon layer GP (gate electrode) is formed on a P-type semiconductor substrate 21 via a gate insulating film 25. On the gate polysilicon layer GP, two metal stacked portions MS1, MS2 (M1, M2, M3 and plugs connecting them) in contact therewith are formed. The metal stacked portion MS1 is disposed under the power supply line 9 that is the fourth metal layer. In the other metal stacked portion MS2, the first metal layer M1 is extended, and the second metal layer M2 and the third metal layer M3 are formed thereon, and are disposed under the ground line 10 that is the fourth metal layer. Is done.

  In the structure of FIG. 8A, a via contact portion including a via 23 and a plug 24 embedded in the via 23 is formed on the metal stacked portion MS1, and the power line 9 is connected to the gate poly via the via contact portion. By being connected to the silicon layer GP, a decoupling capacitor Cd is formed between the power supply line 9 and the P-type semiconductor substrate 21. Since the P-type semiconductor substrate 21 is connected to the ground line 10, the decoupling capacitance Cd is formed between the power supply line 9 and the ground line 10.

  In the structure of FIG. 8B, a via contact portion including a via 23 and a plug 24 embedded in the via 23 is formed on the metal stacked portion MS2, and the ground line 10 is connected to the gate poly via the via contact portion. By being connected to the silicon layer GP, the decoupling capacitance Cd is not formed.

  In this way, the capacitance value of the decoupling capacitance Cd can be varied simply by changing the position of the via contact connected to the gate polysilicon layer GP by using the via formation mask. Further, since only one mask is changed and the via mask is changed, the cost can be minimized.

  In the above-described embodiment, an example of a four-layer metal process has been described. However, the present invention is not limited to this, and can be widely applied to single-layer metal and multilayer metal in general. The structure of FIG. 9 is an example of a single layer metal (first metal layer M1) process.

  In the structure of FIG. 9A, the power supply line 9 is connected to the gate polysilicon layer GP through a via contact portion including a via 23 and a plug 24 embedded in the via 23, and the ground line 10 is a similar via contact portion. It is connected to the P-type semiconductor substrate 21 via As a result, the decoupling capacitance Cd is formed between the power supply line 9 and the ground line 10.

  In the structure of FIG. 9B, the ground line 10 is connected to the gate polysilicon layer GP through a via contact portion including a via 23 and a plug 24 embedded in the via 23. As a result, the potential of the gate polysilicon layer GP becomes the same as the potential of the P-type semiconductor substrate 21, and the decoupling capacitance Cd is not formed between the power supply line 9 and the ground line 10.

It is a schematic diagram of the periphery of a crystal oscillation circuit according to an embodiment of the present invention. It is a figure which shows the circuit around the crystal oscillation circuit in a chip | tip. It is a figure which shows the influence on the current spectrum of resistance in a chip | tip. It is a figure which shows the influence on the voltage drop of the resistance in a chip | tip. It is a figure which shows the effect of the decoupling capacity | capacitance Cd to the electric current level of the 3rd harmonic in a PKG power line terminal. It is the 1st sectional view of power supply resistance. It is a 2nd sectional view of power supply resistance. It is a 1st sectional view of a decoupling capacity. It is a 2nd sectional view of a decoupling capacity.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 PCB 2 PKG 3 Chip 4 Crystal oscillator 5 Input / output circuit 6 Internal circuit block 7 Bonding wire 8 Lead 9 Power supply line 10 Ground line 11 NAND circuit 12 Inverter 21 P type semiconductor substrate 22 Interlayer insulation film 23 Via 24 Plug 25 Gate insulation Film R Power supply resistance Cd Decoupling capacitance PD Pad PL Polysilicon layer GP Gate polysilicon layer

Claims (4)

A power supply line, a circuit for receiving a power supply potential from the power supply line, and a power supply resistor inserted in the power supply line, wherein the power supply line is formed on the power supply resistor, and the power supply resistor, the power supply line, A semiconductor integrated circuit characterized in that the position of a via contact connecting the two is changed by a via forming mask. A power supply line; a circuit for receiving a power supply potential from the power supply line; a power supply resistor inserted into the power supply line; and a plurality of via contact portions connected to the power supply resistor, wherein the power supply line includes the power supply A semiconductor integrated circuit formed on a resistor, wherein a position where the power supply line is connected to any of the plurality of via contact portions is changed by the mask for forming the power supply line. A ground line for supplying a ground potential to the circuit; and a decoupling capacitor formed between the power line and the ground line, wherein the decoupling capacitor is a first capacitor connected to the ground line. A via contact that includes an electrode and a second capacitor electrode disposed opposite to the first capacitor electrode and connects either the power line or the ground line to the second capacitor electrode; The semiconductor integrated circuit according to claim 1, wherein: is changed by a mask for forming a via contact. The first capacitor electrode is a semiconductor substrate, the second capacitor electrode is a gate electrode, and a gate insulating film is formed between the first electrode and the second electrode. 4. The semiconductor integrated circuit according to 3.

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