JP2008227529A - Hall effect device and method of operating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an improved hall effect element including a ferromagnetic material component capable of being used, for example, as a logic application example executing a digital combination-allowable task and a memory element for a non volatile memory device of digital information in such as a magnetic field sensor. <P>SOLUTION: A hall effect element includes a ferromagnetic material layer 510 which covers a part of a hall plate 520 and being electrically isolated therefrom. The ferromagnetic material layer 510 on the hall plate 520 can be changed by applying an external magnetic field. When the element is used as a memory component, the element is allowed to have two stable magnetization statuses (positive and negative) along an anisotropy axis that can correspond to two different data values (0 or 1). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a hybrid Hall effect device. In particular, the present invention relates to a device in which a ferromagnetic layer is combined with a conventional Hall plate in a hybrid manner. This type of Hall effect device is used as a memory element, magnetic field sensor or logic gate and is integrated with a known semiconductor field effect transistor (FET) to form a hybrid ferromagnet / semiconductor device. In addition to adding new applications to these ferromagnetic materials and these devices, the performance is improved in an environment such as a nonvolatile memory.

A field effect transistor (FET) is a metal oxide semiconductor (MOSEFET) structure formed on a silicon substrate or a gallium arsenide (GaAsFET) device on a gallium arsenide substrate, and is a component of modern digital electronic equipment. For example, FETs are used as main components in memory cells that store binarized information, logic gates that process digital data strings, and the like.

  Examples of cell structures of various conventional memory devices include the following. For memory structures such as advanced volatile memory technology (memory that loses its memory contents when power is cut off, such as dynamic random access memory (DRAM)), conventional semiconductor FET structures and capacitors are used in the memory structure. Yes. In addition, non-volatile memories based on many other memory technologies (memory that retains stored contents even when the power supply is cut off) are stored by magnetoresistors made of electrostatic magnetic coupling and ferromagnetic materials. It is used to Further, in the nonvolatile memory device proposed by the applicant in US Pat. No. 5,432,373, a magnetic spin transistor having one or more passive elements is used.

  Also consider the Hall effect and Hall effect elements. Finally, a general gate operation according to the prior art will be described.

Memory Cell Structure Used in Conventional Volatile Memory Devices For memory cells used in DRAMs, the most common commercially available cells are field effect transistors (FETs) that insulate individual cells from data storage capacitors and cell arrays. ) Consists of only two elements. This type of cell is widely used because it can be easily miniaturized, and thus can be highly integrated and relatively inexpensive. The storage element of this type of cell is a capacitor, and indicates binary data “1” and “0” by two states, for example, a state in which charge Q is accumulated and a state in which charge 0 (zero) is accumulated. . Each cell is connected to an array of write and read lines called bit lines and word lines. Since each individual capacitor is linked to another capacitor in the array, the charge flows out to other adjacent cells. Each capacitor of each cell is connected to the transistor in the cell and insulated. When the transistor is on, the writing line or the reading line has a low resistance, the applied voltage is accumulated in the capacitor at the time of writing, and the charge accumulated by the detection circuit is detected at the time of reading. On the other hand, when the transistor is off, the write or read line is high impedance and the capacitor is isolated from the other elements in the array.

Generally, a metal oxide semiconductor field effect transistor (MOSFET) used in a DRAM is manufactured on a silicon substrate by a general lithographic process. The oxide that insulates the gate from the channel is highly insulated and is configured so that the metal gate is capacitive with respect to the rest of the device. The capacity of this gate may be used as a storage capacity. Reading in this case is performed by a detection circuit that compares the charge (or voltage) of C with the standard capacity C ′ of the dummy cell. The read voltage is about 10 to 100 mV, and the stored charge is about 1000000 electrons.

  However, conventional DRAMs have several operational and physical problems. First of all, the memory is volatile. Since discharge of leakage current is unavoidable, each cell must always be refreshed by reading and re-buying, and the refresh must be performed every few milliseconds. Furthermore, the release of background α particles causes sufficient conductance in the MOSFET, drains the capacitance in a pseudo manner, and erases the stored contents of the cell.

  Finally, because it is limited by the size of the capacitor, the cell size cannot be reduced to the limit possible by the lithograph. Therefore, there is a limit to the degree of integration of this type of cell using the conventional pseudo-tsu.

Cell structure used for non-volatile memory layer Several techniques are used to manufacture non-volatile memory cells. Capacitive memory elements using a ferromagnetic material as a dielectric have a problem of fatigue and have a limited number of read / write operations.
There is also a similar device using a ferromagnetic material. Below we examine three of these technologies.

Magnetoresistive RAM (MRAM)
Magnetoresistive RAMs are shown, for example, in JM Daughton's “Magnetic Resistive Memory Technology” thin solid films 216, 162 (1992). This device uses an array of bit lines and word lines. Each bit line is divided into n memory cells. Each cell has a three-layer structure of a ferromagnetic metal base (F layer), a non-ferrous intermediate layer (N layer), and a ferromagnetic upper layer (F layer). This cell structure is different from a giant magnetoresistive (GMR) structure where there is no exchange coupling across the N layer so that the interface spin scattering at the interface between the F layer and the N layer is negligible for the entire scattering. The cell is formed with dimensions of length l, width w, and thickness d. Looking at the cross section of the cell in the width direction, there are two stable magnetization states determined by electrostatic coupling, and these two magnetization states cause the two ferromagnets to interact in the clockwise and counterclockwise directions. It has a directivity in the opposite direction.

  The resistance of each cell as measured by the sense current applied in the cell length direction is a function of the F layer anisotropic magnetoresistance (AMR). When the magnetization direction is a direction orthogonal to the detection current (any stable magnetization state), the resistance value is R1, and when the magnetization direction of the ferromagnetic material is forced to be parallel to the detection current, The resistance value is R1 ′. Each cell of the bit line is connected to the next cell by a conductive piece having a resistance value Rc.

  The n word lines in the column direction intersect with the m bit lines in the row direction. Each non-ferrous word line intersects the top surface of each bit line cell. The state of cell (i, j) is determined by applying an appropriate detection current pulse through bit line i and word line j using a magnetic field generated by a current that magnetizes the cell in a clockwise or counterclockwise direction. Written. The stored contents of the cell are such that the word line j is first biased by a sufficiently large current, both ferromagnets are magnetized by a magnetic field generated by the current, and this is inclined 45 degrees from the axis of the bit line.

  In this orientation, the resistance of the cell to the detection current applied to the bit line is R2 between R1 and R1 '. Next, a detection current having a value proportional to (n-1) R1 + R2 + nRc is applied to the bit line. Finally, a read current pulse is applied to the word line in addition to the original bias current. In this state, the FET passes a current with a small resistance of about 1000Ω or less. The bias current Isense is applied to both the magnetic resistance R and the reference resistance R ′. At the end of one column or row in the array, the detected current is compared with two voltages ”, eg, Isense * (R0−R ′)> 0 or Isense * (R−R ′) = 0, respectively. In this case, it is converted to “1” or “0”. The voltage level corresponding to “1” (or “0”) is amplified to the TTL or CMOS level.

  The voltage Isense * δR for identifying the voltage values “1” and “0” is set large so as to ensure the reliability of the identification. Since the magnetoresistance ratio δR / R ′ of the ferromagnetic layer (or the multi-layered GMR layer) is as small as 10% or less, it is necessary to make the magnetoresistance very large. For example, when R = 100Ω and δR / R ′ = 0.06, the read voltage difference generated at 1 mA bias current is only 6 mV, and the S / N ratio of the GMR cell is very small.

  There are several problems with the above method. The resistor occupies a large area in the cell. As for the above example, a 100Ω magnetoresistance can be formed of a ferromagnetic material having a resistance of 20 μΩ-cm, a length l = 5 μm, a width w = 1 μm, and a thickness dz = 0.01. This cell requires the creation of two resistors R and R ', resulting in extra FETs and a large space as a whole. Since the reference resistance has a very small resistance difference δR, the resistance of each memory must match a predetermined reference resistance. Since the resistance value is a function of temperature (R = R (T)), the reference resistance must be formed very close to the magnetoresistance in order to always maintain the same temperature as the magnetoresistance. Further, the material for forming the reference resistance must be selected so that the temperature dependence of the resistance value approximates that of the magnetic resistance. Finally, the resistance of each cell becomes very large. When an array is formed by arranging a large number of cells on one readout line, the resistance of the readout line becomes very large. Since the read process uses a bias current, power consumption in each read cycle increases.

Spin transistor type non-volatile RAM (NRAM)
2. Description of the Related Art Active devices using magnetic spin transfer have been known. The history of spin transfer technology is described in the Mesevey experiment [R, Meservey, PM Tedrow and P, R. Meservey, Phys. Rev .. Lett, 25 1270 (1970); PM Tedrow and P, R. Meservey, Rev. Lett, 26 192 (1971); Phys. Rev. B7, 318 (1973)]. In this experiment, the current from the ferromagnetic electrode is transmitted through a low transmissivity barrier to a superconducting detector with effective spin polarization. [In several journals, including Mark Johnson and RH Silsbee, Phys. Rev. B 35,4959 (1987); Phys. Rev. B37,5312 (1988); Phys. Rev. B35,5326 (1988) As shown] From spin injection experiments, all ferromagnet-nonferrous (F1-N) interfaces have an effective spin polarization, and the classical diffusion distance δs from the (F1-N) interface. Non-equilibrium population of spin-polarized electrons equal to the non-equilibrium magnetization diffusing to the N side with a characteristic length equal to, and the current flow (or generated voltage) at the N-F2 interface of the second ferromagnetic layer The non-equilibrium magnetization to the affected N side is shown.

  It has been proposed by the inventors to replace conventional semiconductor devices with devices known as bipolar spin transistors. This device and related changes include Mark Johnson, “The All Metal Spin Transistor,” IEEE Spectrum Magazine, Vol. 31 No. 5 p47 (1994) and Mark. -It is shown in Johnson "The Bipolar Spin Transistor" Science 260, 320 (1993). The outline of this apparatus is that a first ferromagnetic layer and a second ferromagnetic layer F2 are arranged on one side of an aluminum continuum. The first ferromagnetic layer emits a source of spin-polarized electrons that are diffused. The second ferromagnetic layer detects the presence of spin-polarized electrons. This device has a novel F (ferromagnetic) (non-ferrous)-(ferromagnetic) structure and is used as a circuit element of a non-volatile memory cell and provides several advantages. The read voltage is bipolar and positive when parallel and negative and negative when non-parallel, and the determination between logical values “1” and “0” is relatively easy, Only a single storage element is required and its read voltage is compared to ground level. In addition, the transimpedance of a spin transistor is a practice that is almost inversely proportional to its size, and in small devices, the read voltage increases (relative to a constant current), which accelerates cell size reduction. .

  Two characteristics of the device must be considered when using a device in NRAM. First, the entire device is made of metal, and therefore has a low electrical resistance. Therefore, each element in the column must be electrically isolated to prevent the output of each element from being shorted to ground through an adjacent element. Second, the output voltage obtained from the device is lower than the TTL level or CMOS level, and the output must be amplified before being introduced into a TTL or COMS circuit.

  Another spin transistor NRAM cell design is shown in commonly owned US Pat. No. 5,432,373 for “Magnetic Spin Transistor”. The spin transistor NRAM cell includes a spin transistor, one or more capacitors, and a resistor. The passive element is used to isolate the spin transistor of each cell, and the read voltage is transmitted to the end of the conducting wire of the amplifying element. The disadvantage of this design is that resistors and capacitors occupy a large area in the chip. Therefore, many parts of the cell are occupied by passive elements, limiting the degree of integration, and wasting the scaling characteristics unique to spin transistors.

  Furthermore, cell insulation is not very effective, and the read voltage may deteriorate during transmission to the detection circuit, causing a problem of large noise and low read sensitivity. In spin transistor memory cell designs proposed by newer applicants, spin transistors are used with one or more insulating FETs. This is a practical method, and this configuration achieves a degree of integration equal to or higher than that of a DRAM.

  Hall plates have long been used as magnetic field sensors that measure a homogeneous magnetic field over the area of the plate. There are also various elements that combine ferromagnetic films with Hall plates. In a typical configuration [RS Popovi'c, "Hall-effect Devices," Sens. Actuators 17, 39 (1989)], the Hall plate is perpendicular to the semiconductor substrate (ie, on the substrate surface) by an appropriate doping technique. It is buried in the direction orthogonal). The ferromagnetic film is formed outside the Hall plate region and is used to “focus” the magnetic field of the external magnetic field onto the vertically arranged Hall plate. Roughly speaking, the external magnetic field is enhanced by the permeability of the ferromagnetic material.

  The disadvantage of this element used as a linearly responsive sensor is the fact that the sensitivity of the element is limited and the element itself is relatively expensive. The reason why the sensitivity is limited is that the enhancement factor of the magnetic field related to the focusing of the ferromagnetic layer with respect to the applied magnetic field is relatively small. Furthermore, the shape of this element does not allow memory effects, and in other ways also prevents it from being practically implemented as a memory element.

  A second configuration called “magnetic field sensor” (US Pat. No. 4,607,271, 1986) has been proposed, but no application example has been found. The above-mentioned US Pat. No. 4,607,271 shows a portion of a magnetic transistor formed on a P-type doped region of an N-type doped silicon substrate. An insulating layer passivates (protects) the surface of the silicon, and an in-plane anisotropic ferromagnetic film (NiFe or NiCo or the like) is formed on the insulating film between the collector and the emitter. . The magnetization of the ferromagnetic film always lies in the plane of the film and this film is formed to have an easy axis parallel to the ^ y axis, so the magnetization can be either + ^ y or-^ y. Orientated along. This element is suitable if the detected external magnetic field is also oriented along ^ y. This (magnetization) easy axis of the ferromagnetic film is oriented in a direction perpendicular or perpendicular to the current direction along the x-axis from the emitter to the collector. The collector and emitter N + type diffusion regions extend from the silicon substrate surface to a depth of a few microns or more (up to 1 mm), and the P-type doped region also has a maximum thickness of a few microns. Thus, current I flows throughout a cross-sectional area consisting of a width w (generally 50 microns) and a depth d on the order of 1 to 10 microns, this area being known as the "sensing zone". A small magnetic field (greater than the coercivity of the ferromagnetic film) orients the magnetization along + ^ y, and the ferromagnetic film generates a magnetic field. The magnetic field is similar to that of a bar magnet. The magnetic field in the vicinity of the zone is substantially uniform and oriented along ± ^ y and deflects the current by Lorentz force in the same way that an external magnetic field deflects the current. The deflected current is detected in a standard manner depending on the characteristics of the magnetic transistor. When the external magnetic field has the opposite sign and is above HC (| H |> | HC |), the magnetization reverses orientation, the magnetic field B changes sign, the Lorentz deflection changes sign, and the magnetic The transistor detects the reverse deflection as a change code. The magnetic field B in the zone is approximately 5 to 15 Oe (Oersted), which is the same as 10 times the coercivity of the ferromagnetic film. Thus, a “magnetic field sensor” is more sensitive to an applied magnetic field than a magnetic transistor formed without a ferromagnetic film. As a result of analysis of this element, the ferromagnetic film operates as a magnetic field transducer having a gain of (about) 10, which converts the external magnetic field H along ^ y into a magnetic field B along ^ y. It can be said that More importantly, the ferromagnetic film must be formed in the center between the emitter and collector and in the center of the “sensing zone”, and its easy axis must be perpendicular to the direction of current flow. It should be noted.

  This element has the advantage that its magnetic field B is substantially uniform throughout the “sensing zone”, whereas its main disadvantage is its low gain. Since the magnitude of B is only several times larger than that of the coercive force HC, the maximum gain is about 10, and the S / N ratio has a drawback. Furthermore, the uniformity of B is achieved by making the ferromagnetic film relatively long. In other words, this element does not have stretchability (scalable), and if it is made smaller, its performance is lowered. Such a behavior is counter to what is desired for a finely fabricated high-density element, and the device becomes large for practical use as a memory cell. What is clear is that it is desirable to devise a novel hybrid type ferromagnetic-semiconductor Hall element, which is stretchable (ie, the element characteristics do not deteriorate even when the dimensions shrink), and is remarkable. It is a device with high gain and hence a very high S / N ratio.

  Additional combinations of Hall conductors, gallium arsenide, and ferromagnetic films have been devised as memory cells [J. De Boek, J. Harbison et al., "Non-volatile Memory Characteristics of Submicrometer Hall Structures Fabricated in Epitaxial Ferromagnetic MnAl Films on GaAs ", Electronics Letter 29, 421 (1993)]. Before describing this element, it is necessary to outline some properties of ferromagnetic materials. Thin ferromagnetic films can be classified according to their anisotropy energy and will fall into two categories, one with a magnetic anisotropy that favors the magnetization lying in the plane of the film. The other category has magnetization anisotropy that is oriented so as to be orthogonal to the film plane and that prefers magnetization. In the device described by Harbison, a ferromagnetic material having a magnetization anisotropy perpendicular to the surface of the τ phase of MnAl is epitaxially grown as a thin film on the AlAs buffer layer, the buffer layer being gallium arsenide. Grown on the substrate. Ferromagnetic films have two stable states with upward or downward magnetization. Written by using stray magnetic fields due to current pulses in adjacent readout lines. In this state, “reading” is performed using a technique called “abnormal Hall effect”. This anomalous Hall effect occurs in the magnetic material and is caused by a mechanism unrelated to that of the normal Hall effect, generating a voltage across the bias current (similar to the classic Hall effect). . In the Harbison element, the sensing conductor and MnAl552 are bound, and the Hall effect in gallium arsenide is not utilized. As a result of the anomalous Hall effect, a positive voltage is generated between and when oriented downward. When oriented upward, the generated voltage has an opposite sign.

  One disadvantage of this Harbison element is that ferromagnetic materials with large anisotropy perpendicular to the plane also have a large coercivity. Thus, a large magnetic field (and a large write current) is required to write the device state. A second disadvantage is that these materials are generally new (unusual) and must be epitaxially grown in an expensive process. Thirdly, the anomalous Hall effect is somewhat smaller than the normal Hall effect with high hole mobility in the material, so the S / N ratio is relatively poor.

FET logic gate The logic processing in a computing element is typically performed by digital voltage pulses and FET gates interconnected in an appropriate manner. To provide an example that allows a brief critical discussion, the standard configuration for AND gate operation [Paul Horowitz and Winfield Hill, "The Art of Electronics," Cambridge Univ. Press, Cambridge UK (1980); p .328] is shown in FIG. 5, where each element is an enhancement mode (or enhancement type) FET. Each element is a p-type channel FET. A p-type channel FET has high impedance and is in an “off” state when the gate voltage is zero or positive. It has a low impedance and is in the “on” state when the gate voltage is below a threshold value less than zero (where the threshold is typically 0.5 volts or less). Each element is an n-type channel FET. An n-type channel FET is “off” when the gate voltage is below ground, and “on” when the gate voltage is greater than a threshold above ground. When a positive or zero voltage pulse amplitude (high or “1”, or low or “0”) is applied to the input at the same time, the cell operates as an AND gate as follows.

  Although the logic gates of this design are the backbone of digital electronics processing, they suffer from several disadvantages. The construction of this logic gate cell requires a large number of FETs (six in the example of FIG. 5) and therefore occupies a large area in the chip. Furthermore, the result of Boolean algebra processing is not stored and needs to be synchronized in the clock cycle used in the next processing step or sent to a separate storage cell for later recall. There is. The above discussion has been provided for complementary metal oxide silicon (CMOS) logic devices. Although transistor transistor logic (TTL) classes are based on bipolar transistors, similar conclusions apply. In other words, a single TTL logic gate cell contains several transistors and several resistors, and uses considerable space on the chip. Clearly, it is desirable to integrate logic processing and storage functions into a single element.

  Thus, there is a tremendous demand for improved devices that can be used easily and reliably in terms of high density memory and logic environments.

  Accordingly, it is an object of the present invention to provide an improved Hall effect element that includes a ferromagnetic component, which can be used in all other environments (eg, logic applications that perform digital combinable tasks, magnetic field sensors, etc. In the same manner, an improved Hall effect element that can be used as a memory element for a non-volatile storage device for digital information is provided.

  Another object of the present invention is to provide an improved hybrid FET device in which the modified Hall effect device of the present invention is combined with a conventional semiconductor FET structure, which is the conventional FET (or the conventional one) in the above-described application example. The magnetic field sensor can also be used.

  In accordance with the present invention, a novel Hall effect element is manufactured using a ferromagnetic layer that covers a portion of the Hall plate and is electrically isolated from the Hall plate. This structure may be generally referred to as a “deformed Hall plate”.

  The ferromagnetic layer of the modified Hall plate is manufactured to be magnetically anisotropic so that the element has two stable magnetization states (positive and negative along one anisotropic axis). . Thus, the deformed Hall plate has two stable Hall voltage states, which are determined by the orientation of the magnetization of the ferromagnetic layer, ie a “positive” Hall voltage (for positive orientation). And “negative” Hall voltage (for negative orientation). An external magnetic field can be used to change the magnetization state of the element by orienting the magnetization of the ferromagnetic layer to be positive or negative.

According to a first configuration of the present invention, there is an improved Hall effect element,
A conductive film layer having an upper surface and capable of carrying a current;
A ferromagnetic layer having a controllable magnetization orientation and covering the first portion of the top surface but not the second portion, wherein a fringe magnetic field substantially perpendicular to the surface is A ferromagnetic layer adapted to be generated by an edge portion of the ferromagnetic layer,
A Hall effect element is provided, wherein an electrical signal can be generated in response to the fringing magnetic field acting on the current in the conductive film layer.

  In the above configuration, the first sensor coupled to the first edge portion of the conductive film layer and the second sensor coupled to the second edge portion of the conductive film layer opposite to the first edge portion. It is preferable that the electric signal is a voltage generated substantially along an axis connecting the first sensor and the second sensor. Further, it is desirable that the conductive film layer and the ferromagnetic layer are separated by an insulating layer.

  The current is applied to a first bias terminal coupled to a third edge of the conductive film layer and to a fourth edge of the conductive film layer opposite to the third edge. It is desirable to configure to flow between the coupled second bias terminals. It is also possible to provide a write line for configuring the magnetization orientation in the ferromagnetic layer. Further, the ferromagnetic layer is coupled to a magnetic field generated by magnetically stored data, and the generated electrical signal is related to the value of the data so that the element operates as a magnetic field sensor. It is possible to configure. Still further, the ferromagnetic layer can be configured to have an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to an axis passing through the first and second sensors.

According to the second configuration of the present invention, a conductive film layer,
There are at least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, and a part of the upper surface of the conductive film layer has two states and the conductivity A ferromagnetic layer that generates a fringing magnetic field substantially normal to the upper surface of the film layer by an edge portion;
A memory device is provided, wherein two different electrical signals corresponding to two different values of the data item are generated according to a state of a fringe magnetic field acting on a current flowing through the conductive film layer. Is done.

  In the second configuration of the present invention, the first sensor coupled to the first edge portion of the conductive film layer and the first sensor of the conductive film layer opposite to the first edge portion. And a second sensor coupled to the two edges, wherein the two different electrical signals may be voltages that occur approximately along an axis passing through the first sensor and the second sensor.

  In the second configuration of the present invention described above, the two different electrical signals are a first voltage generated when a first value of two different values of the data item is stored in the memory device. An output signal and a second voltage output signal generated when the second value of two different values of the data item are stored in the memory device can be configured.

  In the second configuration of the present invention described above, a detection circuit for comparing the two electrical signals of the memory device with a reference value and determining the value of the data item stored in the memory device can be provided.

  In the second configuration of the present invention described above, the current includes a first bias terminal coupled to the third edge portion of the conductive film layer, and a fourth edge portion facing the third edge portion. Can be a read current flowing between the second bias terminals coupled to.

  In the second configuration of the present invention described above, a wiring defining two controllable magnetization orientation states in the ferromagnetic layer can be provided.

  In the second configuration of the present invention, the ferromagnetic layer can be provided with an easy magnetization axis that is substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors.

In the second configuration of the present invention described above, the magnetization orientation of the ferromagnetic layer is:
(I) The first state is set according to the write current having the first amplitude, and the first state is related to the magnetic field;
(Ii) It becomes a second state according to the write current of the second amplitude, and can be related to the second write magnetic field.

  In the second configuration of the present invention, the magnetization orientation of the ferromagnetic layer and the one state can be maintained until the other state is set in the ferromagnetic layer.

  In the second configuration of the present invention, a plurality of memory devices can be combined to form a memory array.

  In the second configuration of the present invention, the ferromagnetic layer is an iron, cobalt or permalloy thin film having a layer thickness of 130 nm, and the conductive film layer is a 1 micron wide gallium-arsenide plate. The two layers can be separated by an oxide insulating layer having a thickness of 50 nm.

According to a third aspect of the present invention, there is provided a logic device for performing a logic function related to the combination of one or more input signals and output signals,
A conductive film layer;
There are at least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, and a part of the upper surface of the conductive film layer has two states and the conductivity A ferromagnetic layer that generates a fringing magnetic field in a substantially normal direction with respect to the upper surface of the film layer by an edge portion; and one of the first and second current values on the ferromagnetic layer and the conductor. Composed of a magnetic field generated by an input data signal having a write line that is dielectrically coupled,
An electrical output signal is generated in response to the current flowing through the conductive film layer employed for the fringing magnetic field, and a logic device is provided in which the electrical output signal is related to the input data signal and the logic function .

According to the third configuration of the present invention, the electrical output signal is generated by a magnetic field corresponding to a first combination of the input data signals in which the magnetization orientation state of the ferromagnetic layer is related to the logic function. A first value when inverted, and a second value when the state of magnetization orientation of the ferromagnetic layer is not inverted by a magnetic field corresponding to the second combination of the input data signals associated with the logic function. It can be set as the structure which has.

According to the third configuration of the present invention described above, the magnetization orientation of the ferromagnetic material corresponds to the result of a logic function executed in the logic device, and this result depends on the combination of subsequent input signals. It is desirable to be stored in the logic device while the magnetization orientation state is reversed.

According to the third configuration of the present invention, the magnetization state of the ferromagnetic layer is preferably set to an initial state based on a logic function executed by the logic device.

  According to the third configuration of the present invention, the first sensor coupled to the first edge portion of the conductive film layer and the conductive film layer opposite to the first edge portion. A second sensor coupled to the second edge of the second sensor, wherein the two different electrical signals can be voltages that occur approximately along an axis passing through the first sensor and the second sensor. .

  According to the third configuration of the present invention, a detection circuit that compares the two electrical signals of the memory device with a reference value and determines the value of the data item stored in the memory device can be provided.

  According to the third configuration of the present invention described above, the current is supplied to the first bias terminal coupled to the third edge portion of the conductive film layer, and to the fourth edge facing the third edge portion. A read current flowing between the second bias terminals coupled to the edge portion can be used.

  According to the third configuration of the present invention, the ferromagnetic layer has an easy magnetization axis that is substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. I can do it.

According to the third configuration of the present invention, the logic device is configured to execute one predetermined logic function of an OR gate, a NOR gate, a NOT gate, a NAND gate, and an AND gate, and This logic function is preferably based on a predetermined logic function based on the initial configuration of the magnetization orientation and the amplitude associated with each input data signal.

  According to the third configuration of the present invention, a plurality of logic devices are combined to form a logic gate array, and an input signal can be an output signal from one or more logic devices.

According to the third configuration of the present invention described above, it is possible to provide a read circuit that reads the result of the logic function stored in the logic gate array in a predetermined sequence.

  According to the third configuration of the present invention described above, it is possible to provide a level shifter circuit that converts the output of the logic device to an acceptable logic level that can be used by the semiconductor circuit in the subsequent stage.

According to the fourth configuration of the present invention, the first axis connecting the first point coupled to the first edge of the conductive layer and the second point coupled to the second edge of the conductive layer. A method for generating an electrical signal related to a voltage potential generated along
Generating a current flowing along the second axis of the conductive film layer substantially orthogonal to the first axis;
Along the edge of the ferromagnetic layer located approximately along the first axis, generating a fringe magnetic field in a substantially normal direction relative to the second axis;
A method for generating an electrical signal is provided in which an electrical signal is generated in response to a fringe magnetic field acting on the current.

  According to the fourth configuration of the present invention, the fringe magnetic field is. Obtained from the magnetization orientation state of the ferromagnetic layer, the magnetization state can be changed by dielectrically coupling the ferromagnetic layer with a write line that generates a magnetic field.

According to the fourth configuration of the present invention described above, the magnetization orientation is changed by the fringe magnetic field generated from the write line, the first state being a nonvolatile state indicating a first value of a binary data item, While setting the second state, which is a non-volatile state indicating the second value of the binary data item, the generated electrical signal can be two different values corresponding to the two values of the binary data item.

According to the fourth configuration of the present invention, the magnetization orientation is set to one of two stable nonvolatile states by the fringe magnetic field generated from the write line, and these states are one to one. Boolean function results associated with multiple input logic signals are shown, and the magnetic orientation can be configured to store the Boolean function results and change only in response to a given combination of input logic signals. .

According to the fourth configuration of the present invention described above, the reading of the Boolean function binary data stored in the logic device by the measurement of the electric signal is compared with the reference value stored in the logic device or determined by the result of the Boolean function. It can be set as the structure containing the step to perform.

  According to the fourth configuration of the present invention described above, the configuration may include a step of converting the electrical signal into a logic level of an allowable voltage that can be used by the semiconductor circuit at the subsequent stage.

  According to the fourth configuration of the present invention, the ferromagnetic body is coupled to a magnetic field generated by magnetically stored data, and the generated electrical signal relates to a data value. It can be configured as follows.

According to a fifth configuration of the present invention, a field effect transistor including a source region, a drain region, a gate and a channel;
A magnetic layer having a controllable magnetization orientation and arranged in relation to the gate and the channel so that a fringing magnetic field substantially normal to the channel is generated by the edge;
An electronic device is provided in which an electrical signal related to the magnetization orientation of a ferromagnetic layer can be generated in response to a fringing magnetic field acting on a current flowing between a source region and a drain region of a field effect transistor.

  According to the fifth configuration of the present invention, the first sensor coupled to the first edge portion of the conductive film layer and the conductive film layer opposite to the first edge portion. A second sensor coupled to the second edge of the second sensor, wherein the two different electrical signals can be voltages that occur approximately along an axis passing through the first sensor and the second sensor. .

According to a fifth configuration of the present invention described above, the current, the the first bias terminal coupled to the source region of the field effect transistor, a second bias which is coupled to the drain region of the field effect transistor It can be configured to flow between the terminals.

  According to the fifth configuration of the present invention described above, it is possible to have a configuration having wirings that define two controllable magnetization orientation states in the ferromagnetic layer.

  According to the fifth configuration of the present invention, the channel and the ferromagnetic layer can be separated by the first insulating layer, and the wiring and the gate can be separated by the second insulating layer.

  According to the fifth configuration of the present invention, the gate can control the current flowing between the source region and the drain region in response to the control signal.

  According to the fifth configuration of the invention described above, the ferromagnetic material is coupled to a magnetic field generated by magnetically stored data, and the generated electrical signal is related to the value of the data, and the electron The device can operate as a magnetic field sensor.

  According to the fifth configuration of the present invention, the ferromagnetic layer has an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. I can do it.

According to a sixth configuration of the present invention, a field effect transistor including a source region, a drain region, a gate and a channel;
At least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, a portion of the top surface of the conductive film layer having two states and with respect to the channel It is constituted by a ferromagnetic layer arranged in relation to the gate and the channel so that a fringing magnetic field in a substantially normal direction is generated by the edge,
A memory device is provided, wherein two different electrical signals corresponding to two different values of the data item are generated according to a state of a fringe magnetic field acting on a current flowing through the channel.

  According to the sixth configuration of the present invention, further comprising: a first sensor coupled to the channel; and a second sensor coupled to the channel opposite to the first edge portion, The two different electrical signals can be voltages that occur approximately along an axis passing through the first sensor and the second sensor.

  According to the sixth configuration of the present invention, the two different electrical signals are generated when a first value of two different values of the data item is stored in the memory device. And a second voltage output signal generated when a second value of two different values of the data item is stored in the memory device.

  According to the sixth configuration of the present invention described above, the configuration includes a detection circuit that compares the two electrical signals of the memory device with a reference value and determines the value of the data item stored in the memory device. I can do it.

According to a sixth configuration of the present invention described above, the current has a first bias terminal coupled to the source region of the field effect transistor, the second bias terminal coupled to the drain region of the field effect transistor A reading current flowing between them can be used.

  According to the sixth configuration of the present invention described above, it is possible to have a configuration having wirings that define two controllable magnetization orientation states in the ferromagnetic layer.

  According to the sixth configuration of the present invention, the channel and the ferromagnetic layer are separated by a first insulating layer, and the write line and the gate are separated by a second insulating layer. It can be.

  According to the sixth configuration of the present invention, the ferromagnetic layer has an easy magnetization axis that is substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. I can do it.

According to the sixth configuration of the present invention, the magnetization orientation of the ferromagnetic layer is
(I) The first state is set according to the write current having the first amplitude, and the first state is related to the magnetic field;
(Ii) It is desirable to enter the second state in accordance with the write current having the second amplitude and to be related to the second write magnetic field.

  According to the sixth configuration of the present invention, the magnetization orientation of the ferromagnetic layer and the configuration in which one state is maintained until the other state is set in the ferromagnetic layer can be obtained. .

  According to the sixth configuration of the present invention, a plurality of memory devices can be combined to form a memory array.

  According to the sixth configuration of the present invention, the gate can control the current flowing between the source region and the drain region in response to the read signal.

According to a seventh configuration of the present invention, there is provided a logic device for performing a logic function related to the combination of one or more input signals and output signals,
A field effect transistor including a source, a drain, a gate and a channel;
At least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, a portion of the top surface of the conductive film layer having two states and with respect to the channel It is constituted by a ferromagnetic layer arranged in relation to the gate and the channel so that a fringing magnetic field in a substantially normal direction is generated by the edge,
The ferromagnetic layer and a write line that dielectrically couples with a magnetic field generated by an input data signal having one of the first and second current values on the conductor;
To provide a logic device, wherein two different electrical signals corresponding to two different values of the data item are generated according to a state of a fringe magnetic field acting on a current flowing through the channel. I can do it.

According to the seventh configuration of the present invention, the electrical output signal is generated by a magnetic field corresponding to a first combination of the input data signals in which the magnetization orientation state of the ferromagnetic layer is related to the logic function. A first value when inverted, and a second value when the state of magnetization orientation of the ferromagnetic layer is not inverted by a magnetic field corresponding to the second combination of the input data signals associated with the logic function. Can have.

According to the seventh configuration of the present invention, the result of the logic function can be stored in the logic device until the magnetization orientation state is inverted by a combination of subsequent input signals.

According to the seventh configuration of the present invention, the magnetization orientation state of the ferromagnetic layer can be set to the initial state based on the logic function executed by the logic device.

  According to the seventh configuration of the present invention, the first sensor coupled to the first edge portion of the conductive film layer, and the conductive film layer opposite to the first edge portion. A second sensor coupled to the second edge of the second sensor, wherein the two different electrical signals can be voltages that occur approximately along an axis passing through the first sensor and the second sensor. .

  According to the seventh configuration of the present invention, it is possible to have a configuration having a detection circuit that compares the electrical output signal of the logic device with a reference value in order to determine the result stored in the logic device.

According to a seventh configuration of the present invention described above, the current flows between the second bias terminal coupled to the drain of the first bias terminal and the field-effect transistor coupled to the source of the field effect transistor The read current can be used.

  According to the seventh configuration of the present invention, the ferromagnetic layer has an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. I can do it.

According to the seventh configuration of the present invention, the logic device is configured to execute one predetermined logic function of an OR gate, a NOR gate, a NOT gate, a NAND gate, and an AND gate, and logic functions can be based on a predetermined logic function on the basis of the amplitude associated with the initial configuration and the input data signal of the magnetization orientation.

  According to the seventh configuration of the present invention, a plurality of logic devices are combined to form a logic gate array, and an input signal can be an output signal from one or more logic devices.

According to the seventh configuration of the present invention described above, it is possible to have a readout circuit that reads out the result of the logic function stored in the logic gate array in a predetermined sequence.

  According to the seventh configuration of the present invention, the level shifter circuit that converts the output of the logic device to an acceptable logic level that can be used by the semiconductor circuit in the subsequent stage can be provided.

According to an eighth aspect of the present invention, the second point coupled to the second edge of the channel of the first point and the field effect transistor coupled to a first edge of the channel of the field effect transistor A method for generating an electrical signal related to a voltage potential generated along a connecting first axis comprising:
Generating a current flowing from the source of the channel of the field effect transistor along the second axis perpendicular to the first axis to the drain of the field effect transistor through the channel;
The fringe magnetic field generates a fringe magnetic field along the edge of the ferromagnetic layer disposed with respect to the gate oriented substantially normal to the channel,
A method for generating an electrical signal is provided in which an electrical signal is generated in response to a fringe magnetic field acting on the current.

  According to the eighth configuration of the present invention, the fringing magnetic field is obtained from a magnetization orientation state of the ferromagnetic layer, and the magnetization state is dielectrically coupled to the ferromagnetic layer by a write line that generates the magnetic field. It can be changed by doing.

  According to the eighth configuration of the present invention, the magnetization orientation is changed by the fringe magnetic field generated from the write line, the first state being a nonvolatile state indicating a first value of a binary data item, Set the second state, which is a non-volatile state indicating the second value of the binary data item, and the generated electrical signal has two different values corresponding to the two values of the binary data item. I can do it.

According to the eighth configuration of the present invention, the magnetization orientation is set to one of two stable nonvolatile states by the fringe magnetic field generated from the write line, and these states are one to one Boolean function results associated with multiple input logic signals are shown, and the magnetic orientation can be configured to store the Boolean function results and change only in response to a given combination of input logic signals. .

According to the eighth configuration of the present invention described above, the reading of the Boolean function binary data stored in the logic device by the measurement of the electric signal is compared with the reference value stored in the logic device or determined by the result of the Boolean function. It can be set as the structure containing the step to perform.

  According to the eighth configuration of the present invention described above, it is possible to include a step of converting the electrical signal into a logic level of an allowable voltage that can be used by the semiconductor circuit at the subsequent stage.

Conventional Hall Effect Element A typical Hall effect element is shown in FIG. 7, where the current I is driven through a thin rectangular plate called the Hall plate 520. When a uniform magnetic field B is applied orthogonal to the plate 520, the Lorentz force on the current carriers or current carriers (electrons or holes) in the plate is in the direction of the B magnetic field and the direction of the current flowing from the terminal 522 to the terminal 524. Occurs orthogonally. The voltage measurement made between the sensing contacts on both sides of the plate 520 (between S1514 and S2516) measures the Hall voltage VH caused by the Hall effect. When the sign of B is reversed, the sign of the detected voltage is also reversed.

  All conductors show a Hall effect, the most powerful effect among materials with low carrier density, such as bismuth (metal), appropriately doped silicon, and gallium arsenide. This effect is relatively weak for metals and relatively strong for semiconductors. A quantitative measure of the strength of this effect within a particular material is one characteristic called Hall mobility μH. The thickness of the Hall plate 520 does not contribute to this effect, and generally thinner plates work better. In particular, a thin bismuth film, a thin film of doped silicon or gallium arsenide, a two-dimensional electron gas (2DEG), or a conductive channel of an FET functions well as a hole plate. A typical thin film hole plate is shown in FIG.

Modified Hall Plate Example A schematic diagram of a modified Hall plate of the present invention is shown in FIG. This element is formed by covering a portion of a conventional Hall plate 520 with a ferromagnetic film 510 that is electrically insulated from the Hall plate, and one edge or edge of the film 510 is formed. , Aligned or aligned with the axis of the hall sensing terminals 514 and 516 and above. The ferromagnetic film 510 is preferably formed with an anisotropy that constrains or confines its magnetization 512 in the spatial plane of the film 510 with the easy axis along x. Therefore, the magnetization of the film 510 is oriented or set in a positive or negative state along an axis orthogonal to the axes of the Hall detection terminals 514 and 516. If the magnetization of the ferromagnetic film 510 is positive along + ^ x, the edge or peripheral fringing magnetic field B localized below the edge is perpendicular to the Hall plate 520 and at-^ z. Along the direction. This local magnetic field B causes Lorentz deflection of the carrier in the vicinity of the sensor, and the detected Hall output voltage (the voltage generated between S1514 and S2516) has a given polarity (eg, positive).

  If the magnetization of the ferromagnetic film 510 is negative, the fringe field below the edge is perpendicular to the Hall plate and is directed in the opposite direction along + ^ z. Lorentz deflection changes sign and output changes polarity (eg, negative). The polarity regulation of the Hall output can be reversed by selecting the material for the Hall plate or by changing the polarity of the bias current (or voltage). Thus, the element described above has two states, which are determined by the magnetization orientation 512 of the ferromagnetic film 510, where “1” or “0” corresponds to a positive or negative magnetization orientation 512 [ Optional].

  Data values in the form of data bits to be stored in the device can be written by using a magnetic field generated by a current pulse in the write line overlaid to orient the magnetization in the positive or negative direction. In a write procedure, when a write current pulse of positive [negative] polarity and 2 mA (milliamperes) is sent to the write line (not shown, but placed about 50 nm away from the film 510), the magnetic field H (about 8 Oe). And the magnetization 512 of the ferromagnetic film 510 is oriented positively [or negatively] (here, in the case of the ferromagnetic film 510 made of permalloy, H = 8 Oe> Hc = 4 Oe). While the write line is described and described as a “line”, a number of known structures (eg, including conductive films or interconnect lines) that can carry enough current to generate a magnetic field H are present. It will be apparent to those skilled in the art that the invention is compatible. Further, although not essential to the description of the present invention, more details regarding the operation of the read / write lines associated with the ferromagnetic layer can be found in the above-mentioned U.S. application Ser. Nos. 08 / 425,884 and 08 / 493,815. be able to.

  The stored information is non-volatile and can be read by sending a current (or voltage) pulse to the bias terminals 522 and 524 of the Hall plate 520 and sensing the voltage generated across the Hall sensing terminals 514 and 516. In this particular embodiment, a positive voltage represents “1” and a negative voltage represents “0”.

  A preferred embodiment of this “deformed Hall plate” of the present invention is shown in more detail in FIG. A ferromagnetic film 510 having in-plane magnetization anisotropy covers a part of the hole plate 520. A thin electrically insulating (buffer) layer 570 separates the Hall plate 520 from the ferromagnetic layer 510. This effective range is such that one edge portion of the film 510 is aligned with the axes of the detection probes S1514 and S2516. The ferromagnetic film 510 has a large anisotropy that constrains or confines the magnetization 512 to the film surface, and is weakly anisotropic such that the easy magnetization axis exists along the direction of current flow from 522 to 524. Have sex. Such in-plane anisotropy is typically a ferromagnetic material (such as permalloy, iron, or NiCo), an appropriate material thickness, or other standard known to those familiar with the industry. This is achieved by appropriately selecting a proper magnetic bias technique. Other non-metallic ferromagnetic materials known in the art are also compatible, eg, semimetals (eg, Heusler alloys), certain semiconductors, certain oxides having a ferromagnetic phase (eg, perovskite) There are other insulator / ferromagnetic materials. Anisotropy providing a single axis of magnetization provides a magnetic field to the substrate during deposition or formation of the ferromagnetic film, uses alternating bias for the appropriate lower layer or upper layer, or This is accomplished by using other standard magnetic biasing techniques known to those familiar with the industry.

  The modified Hall plate 520 is further illustrated in FIG. 10, with the top surface of the device being drawn to approximately uniform scale. The width w of the film 510 (and the width of the hole plate 520) can be several microns or less (in this case 1 micron) and the length l is approximately the same as its width (in this case about 1). .2 microns), the width of Hall sensors 514 and 516 is somewhat narrower (in this example about 0.6 to 0.8 microns). The width of the film 510 can be slightly smaller or larger than the width of the hole plate 520 and does not need to be perfectly aligned in the middle (with respect to ^ y). However, an important characteristic of the present invention is that, unlike the prior art, the edge of film 510 lies along the line connecting Hall sensors 514 and 516. As described above, since the ferromagnetic layer 510 is formed with magnetic anisotropy, there is an easy axis of magnetization along ^ x.

  Under such circumstances, the magnetization {circumflex over (M)} of the ferromagnetic layer 510 has two stable magnetic orientation states oriented in the positive or negative direction along {circumflex over (x)}. A small external magnetic field +/− Hx that can be supplied by stray magnetic fields from write pulses in adjacent write lines will cause ^ M to be oriented positively or negatively. In this context, it can be seen that the present invention functions as a memory element for storing information bits. In another embodiment, the small magnetic field Hx can be generated as an external magnetic field associated with the stray magnetic field from the magnetization of the storage bit on the magnetic medium, in which case the invention functions as a magnetic field sensor in the read head. Become.

  In the cross-sectional view, the magnetic field B generated by the ferromagnetic film 510 (when ^ M is positive) resembles a dipole magnetic field of a bar magnet, which is generally shown in FIG. 11 (this cross-sectional view). Are not drawn to scale). As shown in this figure, below the edge part of the film 510 is a vector magnetic field B, and some of the parts are represented by arrows and dotted magnetic lines in the figure. B has a large component Bz in the + / − ^ z direction. Bz is directed along-^ z when ^ M is positive, and is directed along + ^ z when ^ M is negative. The magnitude of Bz is a strong function of distance and decreases rapidly as the distance increases from the edge of the film.

  The outline of the distance dependence of the magnitude of the magnetic field depends on the separation z 0 between the Hall plate 520 and the film 510 and the thickness d of the film 510. A typical overview is easily calculated magnetostatically and depicted in FIG. 12 with d = 130 nm and z0 = 50 nm as typical values. The magnitude of Bz is directly proportional to the saturation magnetization Ms of the film 510 (an inherent property of this material) and linearly proportional to the thickness d of the film 510. The proportional relationship of the magnetic field to d is generally true within the limits where d is on the order of 1 micron or less. A thicker value of d is impractical because manufacturing is difficult and if d exceeds about 0.3 microns, the in-plane magnetization anisotropy is weakened. A thickness of a fraction of 1 micron is usually used in micromachining and is within the tolerance of the present invention. In the case of permalloy, the saturation magnetization Ms is substantially equal to 1000 emu / cm 3, and when d, z 0, and MS are the above values, the average magnetic field Bz in the 1-micron width region at the center of the edge of the film 510 is 1000 Oe.

Conceptually, the ferromagnetic film 510 operates as a transducer that converts a small externally provided magnetic field Hx into a large, localized magnetic field Bz. The magnitude of the magnetic field Bz can be measured using the classical Hall effect for carriers in the Hall plate 520. (FIG. 9) The Hall voltage VH generated between the sensors S1514 and S2516 is described by the line integral of Equation 1 below, where J is the bias current density, B is the magnetic field, and dl is the unit vector of this line integral. .

The present invention provides that the edge of the film 510 is given above and is well aligned with the path as shown in FIG. 9 even when the magnetization is not uniform over the area of the Hall plate 520. As long as there is a substantial Hall voltage, it can be used. In the actual embodiment (FIG. 10), Hall probes S1 514 and S2 516 have a finite width ws, which can be fabricated to be on the order of 1 micron. It is clear from the above analysis and explanation that the Hall effect works better with smaller values of ws, as well as with smaller values of z0. In such a case, the Hall voltage can be approximated using the average value Bav of the magnetic field (Formula 2).

  Since the value of Bav increases if such an average is taken over a narrower width ws (and in a more complete analysis, over a narrower width w), the Hall voltage VH is reduced by the size reduction. It turns out that it becomes bigger. In other words, this element has a reversed magnification and its characteristics are improved if the dimensions are reduced, which is a significant improvement over the prior art Hall element.

For 130 nm thick permalloy and w _s = 1 μm, using the value of Bav estimated as above for 1000 Oe, the value of VH can be estimated for some materials. For gallium arsenide with a typical hole mobility μH≈0.9 m ² V ⁻¹ sec ⁻¹ , the value of VH is expected to be VH = 0.067 per read bias voltage. For lightly doped n-type silicon with a hole mobility μH≈0.17 m ² V ⁻¹ sec ⁻¹ , the value of VH is predicted to be VH = 0.013 per read bias voltage. Those skilled in the art will appreciate that these values increase the thickness of the ferromagnetic layer 510, use a ferromagnetic material with a greater saturation magnetization (eg, iron), or adjust other suitable parameters. It will be understood that this can be increased by doing so.

  In a further variation of the invention, a second ferromagnetic film 510 ′ (not shown) can be added to the other side of the Hall plate 520 opposite the first film 510, with each film The edge is aligned along the axes of the sensors S1 and S2. While the fabrication of such elements is somewhat complicated, it also has the advantage of providing a slightly stronger fringing field that may be desirable in some environments.

  As described above, a ferromagnetic material having in-plane anisotropy is more preferable from this context of the present invention, because it tends to have a lower holding force. However, materials with orthogonal anisotropy are equally useful in some applications of the present invention because the coercivity is not a critical parameter in many environments. In these embodiments, the ferromagnetic film is preferably small (on the order of the width of sensors S1 and S2) and its orientation is aligned along the path between the sensors. Other shapes and structures will be apparent to those skilled in the art.

  The detected voltage VH is a bipolar (bipolar) that has a positive value when ^ M is positive and a negative value (having the same magnitude) when ^ M is negative. The output can be raised or lowered with a bias, for example, in the range of 0 to 2 VH by slightly offsetting the relative position to S1514 and S2516. Furthermore, if a bipolar output is not desired, readout can be accomplished with a single sensor referenced to any convenient terminal, such as 522 or 524. Also, a resistance change measured from terminal 522 to 524 can be achieved with some loss of sensitivity.

  The previous Hall element incorporating a ferromagnetic film to focus the external magnetic field [refers to the element by Popovi'c mentioned above] is homogeneous on a relatively large area of the vertically arranged Hall plate. Designed to deliver a strong magnetic field, the ferromagnetic components were intentionally placed away from the central region of the Hall plate. This limited one, with sensitivity as a magnetic field sensor, is expensive to manufacture due to its unusual vertical structure and does not have any memory effect that can be used for storage devices or for use in logic applications. Did not demonstrate.

  What the present invention utilizes is that new insights, i.e., significant Hall voltages with significant magnitude mainly along the line integration path between Hall sensors, can occur in local magnetic fields, not homogeneous. is there. By utilizing conventional lithographic techniques that allow the manufacture of thin sensors (and thin Hall plates), the present invention creates elements with much greater sensitivity [i.e., is analyzed as a transducer, whose The element converts an external magnetic field Hx along ^ x into a local magnetic field BZ along ^ z, and the gain representing the ratio BZ / Hx is about 250 (or more), which is the element according to the prior art. It is much larger than that of], making it a more efficient magnetic field sensor. Furthermore, it creates a device that is compatible with memory elements.

  Prior art “magnetic field sensors” were designed to provide a homogeneous magnetic field over a large area. When analyzed as a transducer, it converts the external magnetic field Hy along ^ y into a slightly larger magnetic field By along ^ y with a gain of about 10. The device was not stretchable and therefore could not shrink for an integrated microfabricated device. In contrast, the gain in the present invention (when analyzed as a transducer) is 250 or more, i.e. about 25 times, and has the opposite shrinkage, so that it can be used in microfabrication and integration applications. Ideal for.

  Compared to the prior art device described by Harbison, the present invention has a greater gain and therefore can use a much smaller amplitude write current so that less power is consumed. Furthermore, it can be manufactured from simple and inexpensive materials such as permalloy, iron and cobalt and is compatible with silicon-based device technology.

  The modified Hall effect element can be used as a single element in a single element memory cell, and an array of cells can be fabricated as a non-volatile random access memory, as shown in FIG. . Any material with compatible hole mobility can be used for the hole plate, such as a thin film of bismuth, gallium arsenide, or doped silicon. Writing a bit into the cell 610 can be done by sending a positive or negative write pulse through the sensing leads 514 and 516, so that the magnetization of the ferromagnetic film 510 is positive or negative (eg, “ 1 ”or“ 0 ”). In this embodiment, the write current amplitude can be about 1 mA (milliampere).

  The stored bits are non-volatile and do not need to be refreshed. Later, it can be read out by biasing between terminals 612 to 614 with current or voltage and detecting the Hall voltage generated between sensing probes 514 and 516. In this embodiment, the positive voltage corresponds to “1” and the negative voltage corresponds to “0”. As will be appreciated by those skilled in the art, this readout process can employ a combination of different conductors, such as by biasing conductors 514 and 516 and sensing the voltage between conductors 612 and 614. . The only consideration is that the magnitude of the read current should be less than the magnitude of the write, otherwise there is a possibility of destructive read for certain uses and the re-use of that bit. The need for writing comes out.

  The memory shown in FIG. 13 is fully stacked non-volatile and is typically 2 μm × 2 μm in size per cell and already exhibits a storage density at least twice that of conventional DRAM. Furthermore, unlike conventional devices, the nature of the present invention is such that the performance characteristics can be greatly improved as the device dimensions are reduced. Thus, as processing and lithography techniques improve, it is expected that elements constructed according to the teachings herein will be further reduced in size.

  The array shown in FIG. 13 uses specially simple cells and uses a simple structure. A separate array of write lines can also be provided as shown in FIG. 14 separated from the rest of the device by an insulating layer. This embodiment may be more preferred in low power environments to avoid power loss that can be caused by the high resistance of sense lines 514 and 516 during the write process. In such a configuration, a bit can be written into the cell 610 by sending a positive or negative write pulse through a write line conductor 616 having a width on the order of 0.6 to 0.8 microns. The read operation is the same as described above.

Ferromagnetic gate type FET
The Hall plate is fabricated as a conductive channel of the FET, and when the ferromagnetic film is incorporated into or near the channel gate, the device operates as a ferromagnetic gate FET (described in detail below). ). The write and read functions are performed as with a modified Hall plate, where the device has two additional states determined by the gate voltage, and in the “on” state, the channel conductance Is high and in the “off” state its conductance is negligibly small. Thus, the ferromagnetic gate FET is typically isolated from the multi-element array by an infinite impedance in the “off” state. The stored bit sends a voltage pulse to the gate, increasing the conductance of the channel, setting the FET to the “on” state, and then sensing the voltage that occurs across the Hall sensor probe on this element Read by.

  The schematic of FIG. 15 represents a gated FET (eg, an enhancement mode device) whose conductive channel functions as a hole plate and is electromagnetically coupled to a ferromagnetic layer at the gate 660 of the FET. A write line 664 is provided. A current (or voltage) bias is provided from the (typically) source 652 of this FET to the drain 654, and two additional terminals 656 and 658 are added to the channel 662 to sense the Hall voltage.

  As seen in FIG. 18, the ferromagnetic film 510 can be integrally included as part of the gate 660 or alternatively as a separate layer. The conductance of channel 662 in this FET is determined by the control voltage VG applied to gate 660 and is controlled to bring the conductance closer to zero ("off") or relatively high ("on"). To do. Since the write line 664 is located adjacent to the ferromagnetic film 510, driving the positive current pulse Iw through the wire 664 orients ^ M along the positive ^ x (hereinafter , In the “+” direction, or equivalently “upward”), driving the negative current pulse −Iw through the wire 664 orients ^ M along the negative ^ x (hereinafter "-" Direction or equivalent "downward").

  A preferred embodiment illustrating the use of the device as a memory cell is shown schematically in FIG. Drain 654 is biased by voltage VDD and source 652 is grounded. One of the hall detection lines (656) is grounded (eg, separately grounded) and the output voltage Vout is measured (with respect to this ground) at the other hall sensing line 658. If the magnetization state of the film 510 is oriented in the + direction or upward (+ ^ M), this two-state element can be described as storing a positive data value (“1”), and similarly , ^ M is oriented in the-direction or downward (-^ M), the stored state is a negative data value ("0").

  Writing data values (bits) to the element is from current pulses in the overlying write line 664, as in the write operation for orientation of ^ M to either + or-as described above. This is done by using a magnetic field [again, see FIGS. 17 and 18]. The stored data bits are non-volatile and separated from other elements in the form of a multi-element array because of the nearly zero conductance in the “off” state when no gate voltage is applied ( Infinite impedance) (eg, an enhancement mode FET) and a high conductance in the “on” state when the appropriate voltage is applied to the gate 660, the two settable states are the conductance of the channel 662 It is because it has. Reading the stored bit is accomplished by sending a control voltage pulse 670 to gate 660, increasing the conductance of channel 662, and biasing the drain with voltage VDD while setting the FET in the “on” state. Is called. The output voltage Vout can then be detected to determine whether there is a bit value stored in the element, ie, a positive or negative data value ("1" or "0").

  A cross-sectional view of a preferred embodiment of a ferromagnetic gate FET is shown in FIG. 18, with the ferromagnetic layer 510 incorporated into an enhancement mode n-channel FET. The length of channel 662 from source 652 to drain 654 in a typical MOSFET structure is on the order of 1 micron. A thin insulator 680 separates the gate 660 from the channel 662. As described above, the ferromagnetic layer 510 can be incorporated as part of the gate or can be fabricated in a separate state. Hall sensor probes 656 and 658 can be fabricated at the edge of channel 662 using doped silicon by a process similar to that of typical source 652 and drain 654 operations. The position y along the length of the channel 662 of these probes can be optimized for maximum signal.

  Write line 664 (or multiple write lines if used as an array) is electrically isolated from this element by a thin insulating layer 682. This state is shown in an exploded view (FIG. 17) for the write line 664, the insulating layer 682, the gate 660, the ferromagnetic layer 510, and the insulating layer 680 over the conductive channel 662. For example, alternative shapes and placement relationships will be apparent to those skilled in the art such that the conductive path for the write current traverses all or part of the gate 660.

Since a typical MOSFET has a Hall mobility of μH≈0.06 m ² V ⁻¹ sec ⁻¹ , the magnitude of the read voltage in the above example is about VH = 0.02 V (VG = 10 V and When VT = 0.55V). The resulting signal to noise ratio (S / N ratio) is superior to that of DRAM and competing non-volatile memory technologies.

  This element can also be used as a magnetic field sensor, for example in a storage head. It should be noted that the read voltage can be increased by changing parameters such as the type and thickness of the ferromagnetic material. For example, an iron film has about twice the saturation magnetization of permalloy, and the read voltage is doubled by using iron instead of permalloy.

  A number of ferromagnetic gate FET memory cells can be fabricated to form an array as shown in FIG. Each element is electrically isolated from the array if it is not addressed, and all elements in the array share the same sensing circuit 700. Writing to the bit element 710 is done by sending an appropriate write pulse through the write line 664. The bit is read by sending a voltage pulse VG to gate 660 while applying a bias VDD 712. Hall voltage from element 710 alone occurs across sensing lines 656 and 658 and is transmitted to sensing circuit 700 for readout.

  The Lorentz force that produces this lateral Hall voltage VH also has an effect on the channel resistance Rxx, which is measured along the direction of current flow from source to drain and is referred to as magnetoresistance. The resistance difference δRxx due to the two states of magnetization + / − ^ M is smaller than the Hall resistance Rxy (where Rxy is defined by the relationship VH = I · Rxy). Thus, the state of the element can be similarly detected by using the magnetoresistive effect, while reading the Hall voltage provides a more sensitive determination of this element state. It is clear to those familiar with the industry that although it may be preferable to use two sensors to detect the Hall resistance Rxy, it is not essential. A single sensor can be used with any ground, for example.

  Ferromagnetic gated hole plates are an advancement over DRAM because their memory cells have a single element and thus have a higher storage density. Also, since it has an excellent S / N ratio and is a non-volatile memory, the array requires substantially less power. Ferromagnetic gate-type hole plates are simpler, better in storage density, better in signal-to-noise ratio, and more efficient in isolation from the array, so that other non-volatile technologies are used. It is an improved type that surpasses. The ferromagnetic gate hole plate is different from the deformed hole plate because it shares the same structure as the DRAM and has excellent insulation from the array.

Ferromagnetic gate type FET as logic gate
Boolean logic processing can also be performed using this ferromagnetic gate type FET. For example, a logical input having two logical data values can be represented by two different current levels on the data wire. This logic input (having a specific current level corresponding to “1” or “0”) has a specific current level corresponding to either the second logic input (also “1” or “0”). ), And then the combined sum of the current levels of these inputs can be applied to a write line that is magnetically coupled to the ferromagnetic layer of the FET. The sum of these logic inputs constitutes a write current pulse in the write line, and the corresponding magnetic field acts electromagnetically on the magnetization state ^ M of the ferromagnetic layer. Depending on the state of the ferromagnetic layer orientation ^ M, and hence the particular combination of inputs, the magnetic field of the write current pulse can change this magnetization, and thus a new magnetization orientation in the ferromagnetic layer. The result of the logical operation is “stored” as a form of Also, although not essential to the description of the present invention, further details regarding structures and circuits that can be used in connection with Boolean logic processing of magnetic spin transistors can be found in U.S. Application Serial Nos. 08 / 425,884 and 08 described above. / 493,815.

  As will be appreciated by those skilled in the art, the principles of the present invention can be extended to create n-input logic AND gates or equivalent logic processors. For example, to set the logic processor so that the magnetization state of the FET drain can be changed only when n easy axes are provided and all n inputs are at a high current level. It can be implemented to generate a sufficiently high magnetic field that changes the orientation of the FET ferromagnetic layer. Other configurations that are compatible with other Boolean operations will be readily apparent to those skilled in the art.

  The result of a typical n ° state element (or the two state element in this discussion) is automatically stored as a Boolean function data value and can be read at any time. In this way, the ferromagnetic gate type FET can function as a logic gate having a memory capability. If the read operation can transmit the result (“0” or “1”, high or low) to other gates for other operations, these gates are linked to each other in combination tasks. Digital processing can be performed. An example of a suitable read technique is illustrated in FIG. The readout circuit 750 can integrate it into CMOS (or for appropriate circuitry such as TTL) logic to amplify the output to the CMOS level (high or low). Alternatively, the output can be sent to the write line of another ferromagnetic gate FET. The example of FIG. 20 is applied to the case of an n-type channel enhancement mode ferromagnetic gate type FET. The ferromagnetic gate FET 760 has two Hall voltages +/− VH in the “on” state. In a typical MOSFET device, VH may generally have the value VH = + / − 0.5 volts when biased with a voltage VDD = 15 volts. In the readout circuit 750, the FET Q1772 is an n-type channel enhancement mode FET, and its body is grounded and biased (V1 = 0). The FET Q2774 is a p-type channel enhancement mode FET whose body is biased at ground (V2 = 0). More generally, the bodies of FETs Q1777 and Q2774 can be biased with variable voltages V1 and V2. In the general case where a ferromagnetic layer with n distinct magnetization states is used, there are n possible voltage states that can be read. Biasing the body of FETs Q1772 and Q2774 with the appropriate voltage values can identify the n possible data values of the n-state ferromagnetic gate FET.

  In the binary case of FIG. 20, when VH is high (0.5 volts), Q1772 is “on”, Q2774 is “off”, and the output is limited high (VDD). When VH is low (-0.5 volts), Q1772 is "off", Q2774 is "on", and the output is limited to low (ground). As a result of reading, the output voltage value is reset to the CMOS level (VDD and ground). Treating each element in FIG. 20 as a single gate, the number of components is three, only half the size of a typical CMOS gate, and the logic gate storage density can be increased. Since no additional memory elements are required to store the results, an additional increase in storage density can be achieved. Furthermore, a single readout cell can be associated with several ferromagnetic gate FETs. Each of the latter can perform a programmed Boolean operation, the results of which are stored and can be recalled in any sequence as desired. The readout circuit shown in FIG. 20 is just one example of several possible circuits.

  Although the present invention has been described in terms of preferred embodiments, those skilled in the art will recognize that numerous changes and modifications can be made to such embodiments without departing from the teachings of the present invention. For example, additional peripheral and supportive circuits (decoders, buffers, latches, equalization, precharges, etc.) that are not shown and discussed here but are commonly associated with semiconductor memory arrays It will be apparent to those skilled in the art that can be easily adapted for the present invention. Furthermore, while the preferred embodiment is shown with enhancement mode FETs, other active devices (depletion mode, p-channel, etc.) can be fabricated using known techniques to include the teachings of the present invention.

  In addition, other suitable FET orientations and shapes can be used with the present invention, including lightly doped source / drains, vertical alignments, etc.

  It will also be apparent to those skilled in the art that the elements can be constructed in a stacked state, that is, in a stacked state such as having the memory cells or logic gates of the present invention in a multilevel configuration. This can be accomplished simply by adding passive elements or similar insulating layers between such multiple levels, with appropriate conventional interconnect circuitry and peripheral support circuitry. Thus, devices constructed in this way can have significant integration advantages over the prior art.

  Accordingly, all such changes and equivalent modifications are intended to be included within the scope and spirit of the invention as defined by the appended claims.

FIG. 1 is a schematic top view of a prior art “spin injection” transistor using spin-polarized electrons. FIG. 2 is a schematic configuration diagram of a magnetic field sensor according to the prior art using a ferromagnetic film and a magnetic transistor. FIG. 3 is a cross-sectional view of the element of FIG. 2 showing the magnetic field distribution in the current carrying region of the magnetic transistor. It is a schematic block diagram and a cross-sectional view of a memory cell according to the prior art using a semiconductor substrate and a ferromagnetic film having magnetic anisotropy in a direction perpendicular to the film surface. 1 is a circuit diagram of a logical AND gate cell including a conventional semiconductor field effect transistor (FET) and an accompanying truth table. FIG. 2 is a schematic top view of a modified Hall plate constructed in accordance with the teachings of the present invention, confirming the general structure therein; It is a perspective view of the conventional hole plate. It is a perspective view of the conventional hole plate. FIG. 7 is a perspective view of the modified Hall plate shown in FIG. 6 showing the spatial relationship between the ferromagnetic layer, the Hall plate, and the magnetic field generated in the element. FIG. 7 is a further top view of the modified Hall plate shown in FIG. 6. FIG. 5 is a further cross-sectional view of the same deformed Hall plate as described above, drawn to scale, where the ferromagnetic layer used in the element has a magnetization of this layer along ^ x It is shown with the magnetic field generated at the end of this layer when oriented in the positive direction. FIG. 12 is a typical schematic diagram of a distribution of magnitudes of orthogonal direction components BZ of the magnetic field B shown in FIG. 11. FIG. 6 is a top view of a further embodiment of the present invention, including a memory array having modified Hall effect elements operating as a single memory cell, wherein writing to the cells is performed using Hall plate sensing leads. Yes. FIG. 6 is a top view of a further embodiment of the present invention, including a memory array having modified Hall effect elements operating as a single memory cell, wherein writing to the cells is performed using additional write conductors. . FIG. 6 is a schematic cross-sectional view of a further embodiment of the present invention, including a ferromagnetic gate FET including a modified Hall plate incorporating a conventional FET. FIG. 6 is a schematic cross-sectional view of a further embodiment of the present invention, including a ferromagnetic gate FET operating as a memory cell and an electromagnetically coupled write line for writing a bit to the cell. FIG. 4 is an exploded view of a write line used to electromagnetically couple to a ferromagnetic layer incorporated in or near a gate of a ferromagnetic gate FET. 1 is a perspective view of one preferred implementation of a ferromagnetic gate FET of the present invention. FIG. FIG. 4 is a schematic diagram of a further embodiment of the present invention in which multiple ferromagnetic gated FETs are used as memory cells and combined with a sensing circuit for reading data bits stored in a single cell. Arranged to form a memory array. FIG. 5 is a schematic configuration diagram of a further embodiment of the present invention, including a ferromagnetic gate type FET used as a logic gate and a readout circuit usable together therewith.

Explanation of symbols

510 Ferromagnetic layer (film)
520 Deformed Hall plate 514,516 Detection terminal 522,524 Bias terminal B Fringe field H (Write) field

Claims (75)

A conductive film layer;
A ferromagnetic layer having a controllable magnetization orientation and covering a first portion of the upper surface of the conductive film but not a second portion, and the conductive layer is formed by an edge portion of the ferromagnetic layer. A ferromagnetic layer that generates a fringe magnetic field substantially perpendicular to the upper surface of the film,
An improved Hall effect element, wherein an electrical signal can be generated in response to the fringing magnetic field acting on a current in the conductive film layer.   A first sensor coupled to the first edge of the conductive film layer and a second sensor coupled to the second edge of the conductive film layer opposite the first edge. The Hall effect element according to claim 1, wherein the electrical signal is a voltage generated substantially along an axis passing through the first sensor and the second sensor.   The Hall effect element according to claim 1, wherein the conductive film layer and the ferromagnetic layer are separated by an insulating layer.   The current is applied to a first bias terminal coupled to a third edge of the conductive film layer and to a fourth edge of the conductive film layer opposite to the third edge. 2. A Hall effect element according to claim 1, wherein the Hall effect element flows between the coupled second bias terminals.   The Hall effect element according to claim 1, further comprising a write line for constituting a magnetization orientation in the ferromagnetic layer.   2. The ferromagnetic layer is coupled to a magnetic field generated by magnetically stored data, the generated electrical signal is related to the value of the data, and the element operates as a magnetic field sensor. Hall effect element described in 1.   The Hall effect element according to claim 2, wherein the ferromagnetic layer has an easy magnetization axis that is substantially parallel to the electrical signal and substantially perpendicular to the axis that connects the first and second sensors. A conductive film layer;
Corresponding to two different values of data items to be stored, at least two controllable and stable magnetization orientations, a part of the upper surface of the conductive film layer having two states and the conductive film A ferromagnetic layer that generates a fringing magnetic field substantially normal to the top surface by the edge portion,
2. A memory device according to claim 1, wherein two different electrical signals corresponding to two different values of the data item are generated in accordance with a state of a fringe magnetic field acting on a current flowing through the conductive film layer.   A first sensor coupled to the first edge of the conductive film layer and a second sensor coupled to the second edge of the conductive film layer opposite the first edge. 9. The memory device of claim 8, wherein the two different electrical signals are voltages that occur approximately along an axis through the first sensor and the second sensor.   The two different electrical signals include a first voltage output signal generated when a first value of two different values of the data item is stored in the memory device, and two different electrical signals of the data item. 10. The memory device according to claim 9, comprising a second voltage output signal generated when a second value is stored in the memory device.   The memory device according to claim 10, further comprising a detection circuit that compares two electrical signals of the memory device with a reference value to determine a value of a data item stored in the memory device.   The current is between a first bias terminal coupled to a third edge of the conductive film layer and a second bias terminal coupled to a fourth edge opposite the third edge. The memory device according to claim 8, wherein the read current flows through the memory device.   The memory device according to claim 8, further comprising a wiring defining two controllable magnetization orientation states in the ferromagnetic layer.   The memory device according to claim 2, wherein the ferromagnetic layer has an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. The magnetization orientation of the ferromagnetic layer is
(I) The first state is set according to the write current having the first amplitude, and the first state is related to the magnetic field;
The memory device according to claim 8, wherein (ii) the second state is set in accordance with a write current having a second amplitude and the second write magnetic field is associated with the second state.   The memory device according to claim 15, wherein the magnetic orientation of the ferromagnetic layer is maintained in one state until the other state is set in the ferromagnetic layer.   The memory device according to claim 8, wherein a plurality of memory devices are combined to form a memory array.   The ferromagnetic layer is a thin film of iron, cobalt or permalloy having a layer thickness of 130 nm, the conductive film layer is a 1 micron wide gallium-arsenide plate, and the two layers are oxidized with a thickness of 50 nm. The memory device according to claim 8, wherein the memory device is separated by a physical insulating layer. A logic device for performing a logic function related to the combination of one or more input signals and output signals,
A conductive film layer;
There are at least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, and a part of the upper surface of the conductive film layer has two states and the conductivity A ferromagnetic layer that generates a fringing magnetic field in a substantially normal direction with respect to the upper surface of the fill by an edge portion; and one of the first and second current values on the ferromagnetic layer and the conductor. It consists of a magnetic field generated by an input data signal and a write line that is dielectrically coupled,
A logic device in which an electrical output signal is generated in response to a current flowing in a conductive film layer employed for a fringe magnetic field, and the electrical output signal is related to the input data signal and the ethical function.   The electrical output signal has a first value when the state of magnetization orientation of the ferromagnetic layer is inverted by a magnetic field corresponding to a first combination of the input data signals associated with the logic function, and has a strong value. 20. The logic device of claim 19, wherein the state of magnetization orientation of the magnetic layer has a second value when not reversed by a magnetic field corresponding to the second combination of input data signals associated with the logic function. .   The magnetization orientation of the ferromagnet corresponds to the result of a logic function performed in the logic device, which results in the logic device while the magnetization orientation state is reversed by a combination of subsequent input signals. 20. The logic device of claim 19 stored in   The logic device of claim 21, wherein the magnetization state of the ferromagnetic layer is set to an initial state based on a logic function performed by the logic device.   A first sensor coupled to the first edge of the conductive film layer and a second sensor coupled to the second edge of the conductive film layer opposite the first edge. 23. The logic device of claim 22, wherein the two different electrical signals are voltages that occur approximately along an axis through the first sensor and the second sensor.   24. The logic device according to claim 21, further comprising a detection circuit that compares two electrical signals of the memory device with a reference value to determine a value of a data item stored in the memory device.   The current is between a first bias terminal coupled to a third edge of the conductive film layer and a second bias terminal coupled to a fourth edge opposite the third edge. 20. A logic device according to claim 19, wherein the logic device is a read current flowing through.   20. The logic device of claim 19, wherein the ferromagnetic layer has an easy magnetization axis that is substantially parallel to the electrical signal and substantially orthogonal to the axis passing through the first and second sensors.   The logic device is configured to perform one predetermined logic function of an OR gate, a NOR gate, a NOT gate, a NAND gate or an AND gate, and the predetermined logic function includes an initial configuration of magnetization orientation and each 20. The logic device of claim 19, wherein the logic device is based on a predetermined logic function based on an amplitude associated with the input data signal.   21. The logic device of claim 20, wherein a plurality of logic devices are combined to form a logic gate array, and the input signal is an output signal from one or more logic devices.   29. The logic device according to claim 28, further comprising a read circuit that reads out a result of the logic function stored in the logic gate array in a predetermined sequence.   28. The logic device of claim 27, further comprising a level shifter circuit that converts the output of the logic device to an acceptable logic level that can be used by a subsequent semiconductor circuit. Related to a voltage potential generated along a first axis connecting a first point coupled to the first edge of the conductive layer and a second point coupled to the second edge of the conductive layer. A method for generating an electrical signal,
Generating a current flowing along the second axis of the conductive film layer substantially orthogonal to the first axis;
Along the edge of the ferromagnetic layer located approximately along the first axis, generating a fringe magnetic field in a substantially normal direction relative to the second axis;
A method for generating an electrical signal, wherein an electrical signal is generated in response to a fringe magnetic field acting on the current.   What is the fringe magnetic field? 32. The method of claim 31, wherein the magnetization state is obtained from a magnetization orientation state of the ferromagnetic layer, and the magnetization state is changed by dielectrically coupling the ferromagnetic layer with a write line that generates a magnetic field.   Due to the fringing magnetic field generated from the write line, the magnetization orientation is changed between a first state which is a nonvolatile state indicating a first value of a binary data item and a nonvolatile state which indicates a second value of the binary data item. 33. The method of claim 32, wherein the electrical signal generated has two different values corresponding to the two values of the binary data item while being set to a second state.   The fringing magnetic field generated from the write line sets the magnetization orientation to one of two stable non-volatile states, and these states are the result of a Boolean function associated with one or more input logic signals. 33. The method of claim 32, wherein the magnetic orientation stores the result of the Boolean function and changes only in response to a predetermined combination of input logic signals.   35. The method of claim 34, comprising reading Boolean function binary data stored in a logic device by measurement of an electrical signal and comparing to a reference value stored in the logic device and determined by a result of the Boolean function.   36. The method of claim 35 including the step of converting the electrical signal to a logic level of an acceptable voltage that can be used by subsequent semiconductor circuitry.   32. The method of claim 31, wherein the ferromagnetic material is coupled to a magnetic field generated by magnetically stored data, and the generated electrical signal is related to a data value. A field effect transistor including a source region, a drain region, a gate and a channel;
A magnetic layer having a controllable magnetization orientation and arranged in relation to the gate and the channel so that a fringing magnetic field substantially normal to the channel is generated by the edge;
An electronic device capable of generating an electrical signal related to the magnetization orientation of a ferromagnetic layer in response to a fringing magnetic field acting on a current flowing between a source region and a drain region of a field effect transistor.   A first sensor coupled to the first edge of the conductive film layer and a second sensor coupled to the second edge of the conductive film layer opposite the first edge. 40. The electronic device of claim 38, wherein the two different electrical signals are voltages that occur approximately along an axis through the first sensor and the second sensor.   40. The electronic device of claim 38, wherein the current flows between a first bias terminal coupled to a source region of the field effect transistor and a second bias terminal coupled to a drain region of the field effect transistor. .   39. The electronic device according to claim 38, further comprising wiring defining two controllable magnetization orientation states in the ferromagnetic layer.   39. The electronic device according to claim 38, wherein the channel and the ferromagnetic layer are separated by a first insulating layer, and the wiring and the gate are separated by a second insulating layer.   39. The electronic device according to claim 38, wherein the gate controls a current flowing between the source region and the drain region in response to a control signal.   40. The ferromagnet is coupled to a magnetic field generated by magnetically stored data, the generated electrical signal is related to the value of the data, and the electronic device operates as a magnetic field sensor. Electronic devices.   40. The electronic device of claim 39, wherein the ferromagnetic layer has an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. A field effect transistor including a source region, a drain region, a gate and a channel;
At least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, a portion of the top surface of the conductive film layer having two states and with respect to the channel It is constituted by a ferromagnetic layer arranged in relation to the gate and the channel so that a fringing magnetic field in a substantially normal direction is generated by the edge,
A memory device, wherein two different electrical signals corresponding to two different values of the data item are generated according to a state of a fringe magnetic field acting on a current flowing through the channel.   A first sensor coupled to the channel and a second sensor coupled to the channel opposite the first edge, wherein the two different electrical signals are substantially the first sensor. 47. The memory device according to claim 46, wherein the voltage is generated along an axis passing through the second sensor.   The two different electrical signals include a first voltage output signal generated when a first value of two different values of the data item is stored in the memory device, and two different electrical signals of the data item. 47. The memory device of claim 46, comprising a second voltage output signal that is generated when a second value of values is stored in the memory device.   47. The memory device according to claim 46, further comprising a detection circuit that compares two electrical signals of the memory device with a reference value to determine a value of a data item stored in the memory device.   47. The current of claim 46, wherein the current is a read current that flows between a first bias terminal coupled to a source region of the field effect transistor and a second bias terminal coupled to a drain region of the field effect transistor. Memory device.   47. The memory device according to claim 46, further comprising wiring defining two controllable magnetization orientation states in the ferromagnetic layer.   52. The memory device according to claim 51, wherein the channel and the ferromagnetic layer are separated by a first insulating layer, and the write line and the gate are separated by a second insulating layer.   47. The memory device according to claim 46, wherein the ferromagnetic layer has an easy magnetization axis substantially parallel to the electrical signal and substantially perpendicular to the axis passing through the first and second sensors. The magnetization orientation of the ferromagnetic layer is
(I) The first state is set according to the write current having the first amplitude, and the first state is related to the magnetic field;
The memory device according to claim 8, wherein (ii) the second state is set in accordance with a write current having a second amplitude and the second write magnetic field is associated with the second state.   47. The memory device according to claim 46, wherein one state is maintained until the magnetization orientation of the ferromagnetic layer and the other state are set in the ferromagnetic layer.   The memory device of claim 46, wherein a plurality of memory devices are combined to form a memory array.   47. The memory device according to claim 46, wherein the gate controls a current flowing between the source region and the drain region in response to a read signal. A logic device for performing a logic function related to the combination of one or more input signals and output signals,
A field effect transistor including a source, a drain, a gate and a channel;
At least two controllable and stable magnetization orientations corresponding to two different values of data items to be stored, a portion of the top surface of the conductive film layer having two states and with respect to the channel It is constituted by a ferromagnetic layer arranged in relation to the gate and the channel so that a fringing magnetic field in a substantially normal direction is generated by the edge,
The ferromagnetic layer and a write line that dielectrically couples with a magnetic field generated by an input data signal having one of the first and second current values on the conductor;
2. A logic device according to claim 1, wherein two different electric signals corresponding to two different values of the data item are generated according to a state of a fringe magnetic field acting on a current flowing through the channel.   The electrical output signal has a first value when the state of magnetization orientation of the ferromagnetic layer is inverted by a magnetic field corresponding to a first combination of the input data signals associated with the logic function, and has a strong value. 59. The logic device of claim 58, wherein the state of magnetization orientation of the magnetic layer has a second value when not reversed by a magnetic field corresponding to the second combination of input data signals associated with the logic function. .   59. The logic device of claim 58, wherein the result of the logic function is stored in the logic device until the magnetization orientation state is inverted by a combination of subsequent input signals.   59. The logic device according to claim 58, wherein the magnetization orientation state of the ferromagnetic layer is set to an initial state based on a logic function performed by the logic device.   A first sensor coupled to the first edge of the conductive film layer and a second sensor coupled to the second edge of the conductive film layer opposite the first edge. 59. The logic device of claim 58, wherein the two different electrical signals are voltages that occur approximately along an axis through the first sensor and the second sensor.   61. The logic device of claim 60, further comprising a detection circuit that compares a reference value of the electrical output signal of the logic device to determine a result stored in the logic device.   59. The logic device of claim 58, wherein the current is a read current that flows between a first bias terminal coupled to a source of the field effect transistor and a second bias terminal coupled to a drain of the field effect transistor.   59. The logic device of claim 58, wherein the ferromagnetic layer has an easy magnetization axis that is substantially parallel to the electrical signal and substantially orthogonal to the axis passing through the first and second sensors.   The logic device is configured to perform one predetermined logic function of an OR gate, a NOR gate, a NOT gate, a NAND gate or an AND gate, and the predetermined logic function includes an initial configuration of magnetization orientation and each 59. The logic device of claim 58, wherein the logic device is based on a predetermined logic function based on an amplitude associated with the input data signal.   59. The logic device of claim 58, wherein the plurality of logic devices are combined to form a logic gate array, and the input signal is an output signal from one or more logic devices.   68. The logic device according to claim 67, further comprising a readout circuit that reads out a result of the logic function stored in the logic gate array in a predetermined sequence.   59. The logic device of claim 58, further comprising a level shifter circuit that converts the output of the logic device to an acceptable logic level that can be used by subsequent semiconductor circuits. Generated along a first axis connecting a first point coupled to the first edge of the channel of the field effect transistor and a second point coupled to the second edge of the channel of the field effect transistor A method for generating an electrical signal related to a voltage potential comprising:
Generating a current that flows from the source of the channel of the field effect transistor through the channel to the drain of the field effect transistor along a second axis perpendicular to the first axis;
The fringe magnetic field generates a fringe magnetic field along the edge of the ferromagnetic layer disposed with respect to the gate oriented substantially normal to the channel,
A method for generating an electrical signal, wherein an electrical signal is generated in response to a fringe magnetic field acting on the current.   The method of claim 70, wherein the fringing magnetic field is obtained from a magnetization orientation state of the ferromagnetic layer, and the magnetization state is changed by dielectrically coupling the ferromagnetic layer by a write line that generates the magnetic field.   Due to the fringing magnetic field generated from the write line, the magnetization orientation is changed between a first state which is a nonvolatile state indicating a first value of a binary data item and a nonvolatile state which indicates a second value of the binary data item. 72. The method of claim 71, wherein the electrical signal generated has two different values corresponding to the two values of the binary data item while setting to a second state.   The fringing magnetic field generated from the write line sets the magnetization orientation to one of two stable non-volatile states, and these states are the result of a Boolean function associated with one or more input logic signals. 71. The method of claim 70, wherein the magnetic orientation stores the result of the Boolean function and changes only in response to a combination of predetermined input logic signals.   74. The method of claim 73, comprising reading Boolean function binary data stored in a logic device by measurement of an electrical signal and comparing to a reference value stored in the logic device and determined by a result of the Boolean function.   75. The method of claim 74, including the step of converting the electrical signal to a logic level of an acceptable voltage usable by subsequent semiconductor circuitry.

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