JP2008227419A - Semiconductor device, semiconductor circuit, electro-optical device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a high ON current, a high-performance semiconductor circuit having the semiconductor device, a high-performance electro-optical device and a highly reliable electronic device. <P>SOLUTION: The semiconductor device 1 comprises a p-n junction body 9 having a p-type organic semiconductor layer 8 and an n-type organic semiconductor layer 7 joined to each other; a source electrode 4 and a drain electrode 5 disposed near an interface between the p-type organic semiconductor layer 8 and the n-type organic semiconductor 7 of the p-n junction body 9; and a gate electrode 3 joined to at least one of the p-type organic semiconductor 8 and the n-type organic semiconductor 7 through a gate insulating layer 6, and the source electrode 4 and the drain electrode 5 are arranged so as to contact with both the p-type organic semiconductor layer 8 and the n-type organic semiconductor 7, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor circuit, an electro-optical device, and an electronic apparatus.

In recent years, development of a semiconductor device using an organic material (organic semiconductor material) exhibiting semiconducting electrical conduction has been promoted. This semiconductor device has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and is expected as a switching element for flexible displays and the like.
Among such semiconductor devices, some organic field effect transistors have a channel having a laminated structure of a p-type organic semiconductor and an n-type organic semiconductor (for example, Patent Document 1).
The purpose of using this structure is to increase the ON / OFF ratio of the transistor and to bring out both the n-type characteristic and the p-type characteristic (bipolar characteristic) according to the positive / negative of the gate voltage.

The structure of the organic field effect transistor will be described in more detail. A structure in which a gate electrode, a gate insulating film, a source electrode and a drain electrode, and an n-type organic semiconductor film and a p-type organic semiconductor film are stacked in this order on a substrate. Consists of.
Note that the stacking order of the n-type organic semiconductor film and the p-type organic semiconductor film may be reversed.
When the gate voltage of such an organic field effect transistor is positive, an open channel is formed in a portion of the n-type organic semiconductor film that is in contact with the gate insulating film. A current using electrons as carriers flows between the source electrode and the drain electrode. This is n-type driving.

  On the other hand, when the gate voltage is negative, an open channel is formed in a portion of the p-type organic semiconductor film that is in contact with the n-type organic semiconductor film. A current using holes as carriers flows between the source electrode and the drain electrode. This is p-type driving. In this case, an open channel is not formed in the n-type organic semiconductor film, and the n-type organic semiconductor film functions as a part of the gate insulating film.

However, in the case of the p-type drive, a pn junction exists between the source electrode and the drain electrode and the opened channel. Moreover, the two pn junctions are connected in series in the opposite direction (back-to-back structure).
Therefore, the current flowing between the source electrode and the drain electrode is blocked by this back-to-back structure. As a result, there arises a problem that the obtained ON current is extremely small.
This problem cannot be solved even if the stacking order of the n-type organic semiconductor film and the p-type organic semiconductor film is changed. When the replacement is performed, the same problem occurs during n-type driving.
Further, even if the source electrode and the drain electrode are formed above the n-type organic semiconductor film and the p-type organic semiconductor film, this problem always occurs in either the p-type driving or the n-type driving.

JP-A-8-228034

  An object of the present invention is to provide a semiconductor device having a high ON current, a high-performance semiconductor circuit including the semiconductor device, a high-performance electro-optical device, and a highly reliable electronic apparatus.

The above object is achieved by the present invention described below.
A semiconductor device according to the present invention includes a pn junction in which a p-type organic semiconductor layer and an n-type organic semiconductor layer are joined to each other;
A source electrode and a drain electrode located in the vicinity of the interface between the p-type organic semiconductor layer and the n-type organic semiconductor layer of the pn junction,
A gate electrode joined to at least one of the p-type organic semiconductor layer and the n-type organic semiconductor layer via a gate insulating layer;
The source electrode and the drain electrode are respectively disposed so as to be in contact with both the p-type organic semiconductor layer and the n-type organic semiconductor layer.
Thereby, since a current is not interrupted by a so-called back-to-back structure, a high ON current can be obtained. As a result, ON / OFF can be improved.

A semiconductor device according to the present invention includes a gate electrode, a source electrode, a drain electrode, a gate insulating layer, a pn junction in which a p-type organic semiconductor layer and an n-type organic semiconductor layer are bonded to each other,
The pn junction is disposed between the source electrode and the drain electrode such that each of the p-type organic semiconductor layer and the n-type organic semiconductor layer is in contact with both the source electrode and the drain electrode. ,
The gate electrode is bonded to at least one of the p-type organic semiconductor layer and the n-type organic semiconductor layer of the pn junction through the gate insulating layer.
As a result, the current is not interrupted by a so-called back-to-back structure, and the distance through which electrons flow is short, so that a higher ON current can be obtained.

In the semiconductor device of the present invention, the gate electrode includes a first gate electrode joined to the n-type organic semiconductor layer via a first gate insulating layer;
It is preferable to have a second gate electrode joined to the p-type organic semiconductor layer through a second gate insulating layer.
Thereby, since two gate electrodes can be driven independently, an n-type organic semiconductor and a p-type organic semiconductor can be controlled independently.

In the semiconductor device of the present invention, it is preferable that each of the source electrode and the drain electrode is formed of a stacked body in which a plurality of layers are stacked.
Thereby, since different materials can be used for each layer, electron injection efficiency and hole injection efficiency into the organic semiconductor can be increased by selecting the material.
In the semiconductor device of the present invention, the stacked body preferably includes two layers made of materials having different work functions.
Thereby, electrons can be efficiently injected into the n-type organic semiconductor layer and holes can be efficiently injected into the p-type organic semiconductor layer, so that the ON current can be further increased.

In the semiconductor device of the present invention, it is preferable to have a protective layer between the two layers.
Thereby, a highly active layer can be protected.
In the semiconductor device of the present invention, the protective layer is preferably made of aluminum or an alloy mainly composed of aluminum.
Thereby, while being able to protect a highly active layer reliably, the adhesiveness of the layer laminated | stacked on a protective layer can be improved.

In the semiconductor device of the present invention, it is preferable that a layer having a large contact area with the n-type organic semiconductor layer among the layers in the stacked body is made of a material having a work function lower than that of the other layers.
Thereby, electrons can be efficiently injected into the n-type organic semiconductor layer, so that the ON current can be further increased.

In the semiconductor device of the present invention, the material having a low work function is preferably composed of aluminum, calcium, or a material containing 70% or more of aluminum or calcium.
Thereby, electrons can be reliably injected into the n-type organic semiconductor layer.
In the semiconductor device of the present invention, it is preferable that a layer having a large contact area with the p-type organic semiconductor layer among the layers in the stacked body is made of a material having a higher work function than the other layers.
Thereby, holes can be efficiently injected into the p-type organic semiconductor layer, so that the ON current can be further increased.

In the semiconductor device of the present invention, it is preferable that the material having a high work function is composed of gold or an alloy mainly composed of gold.
Thereby, holes can be reliably injected into the p-type organic semiconductor layer.
In the semiconductor device of the present invention, it is preferable that each of the p-type organic semiconductor layer and the n-type organic semiconductor layer is composed of a light-emitting organic material having semiconductor characteristics.
Thereby, it can function as a light emitting transistor having high emission intensity.
The semiconductor device of the present invention has a substrate,
The gate electrode is preferably built in the substrate.
Thereby, since the gate electrode and the substrate are integrated, the semiconductor device can be miniaturized and the device can be easily manufactured.

A semiconductor circuit according to the present invention includes the semiconductor device of the present invention.
As a result, a high-performance and small-sized semiconductor circuit with a high degree of design freedom can be obtained.
An electro-optical device according to the present invention includes the semiconductor circuit according to the present invention.
Thereby, a high-performance electro-optical device can be obtained.
An electronic apparatus according to the present invention includes the electro-optical device according to the present invention.
As a result, a highly reliable electronic device can be obtained.

Hereinafter, a semiconductor device, a semiconductor circuit, an electro-optical device, and an electronic apparatus according to the invention will be described in detail based on preferred embodiments.
<Semiconductor device>
<First Embodiment>
First, a first embodiment of the semiconductor device of the present invention will be described.
FIG. 1 is a schematic longitudinal sectional view showing a first embodiment of a semiconductor device of the present invention. In the following description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”.

  In the semiconductor device 1 shown in FIG. 1, a gate insulating layer 6 is formed on the upper surface of a substrate / gate electrode 23 that also serves as the substrate 2 and the gate electrode 3, and an n-type organic semiconductor layer 7 is formed on the upper surface. On top of the n-type organic semiconductor layer 7, a source electrode 4 and a drain electrode 5 formed of a three-layered laminate are provided apart from each other. A p-type organic semiconductor layer 8 is formed so as to cover the upper surface of the n-type organic semiconductor layer 7 including the source electrode 4 and the drain electrode 5. That is, the semiconductor device 1 illustrated in FIG. 1 is a bottom-gate semiconductor device 1.

Hereinafter, the configuration of each part of the semiconductor device 1 will be described sequentially.
The substrate / gate electrode 23 supports each layer (each part) constituting the semiconductor device 1, and has its own conductivity, and functions as the gate electrode 3.
The constituent material of the substrate and gate electrode 23 may be the conductive substrate 2. For example, the insulating substrate 2 such as an n-type or p-type silicon substrate is doped with boron, phosphorus or the like. Examples include a doped substrate, a compound semiconductor substrate such as a gallium arsenide substrate, and a metal substrate. Of these, a doped substrate is preferred. Thereby, since the insulating substrate 2 to be doped is excellent in workability and high in strength, the substrate / gate electrode 23 can be thinned while supporting each layer of the semiconductor device 1.

The substrate / gate electrode 23 may be doped either entirely or partially.
Examples of the insulating substrate 2 include a plastic made of a glass substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), aromatic polyester (liquid crystal polymer) polyimide (PI), and the like. A substrate (resin substrate), a quartz substrate, a silicon substrate, a metal substrate, a gallium arsenide substrate, or the like can be used.

The average thickness of the substrate and gate electrode 23 is not particularly limited, but is preferably 0.5 to 500 μm, and more preferably 10 to 300 μm.
The substrate 2 and the gate electrode 3 may be formed independently rather than integrally.
On the substrate / gate electrode 23, the gate insulating layer 6 is provided.
The gate insulating layer 6 insulates the gate electrode 3 (substrate / gate electrode 23) from a source electrode 4 and a drain electrode 5 described later.
The constituent material of the gate insulating layer 6 is not particularly limited as long as it is an insulating material, and either an organic material or an inorganic material can be used.

Examples of the organic material include polymethyl methacrylate, polyvinyl phenol, polyimide, polystyrene, polyvinyl alcohol, polyvinyl acetate, and polyvinyl phenol, and one or more of these can be used in combination.
Examples of the inorganic material include metal oxides such as silica, silicon nitride, aluminum oxide, and tantalum oxide, and metal composite oxides such as barium strontium titanate and lead zirconium titanate. Can be used in combination.

The average thickness of the gate insulating layer 6 is not particularly limited, but is preferably 10 to 5000 nm, and more preferably 100 to 2000 nm. By setting the thickness of the gate insulating layer 6 within the above range, the thickness of the gate insulating layer 6 becomes a thickness with good dimensional accuracy. Therefore, the source electrode 4 and the drain electrode 5 and the gate electrode 3 (substrate / gate electrode 23) Can be reliably insulated. As a result, the operating voltage of the semiconductor device 1 can be lowered.
Note that the gate insulating layer 6 is not limited to a single layer structure, and may have a multilayer structure.

An n-type organic semiconductor layer 7 is provided on the gate insulating layer 6. The n-type organic semiconductor layer 7 is a layer through which electrons flow as carriers.
the material of the n-type organic semiconductor layer 7 is not particularly limited, for example, compounds represented by the following formula (I), various metal complexes such as phthalocyanine, C _{60, C 82,} dysprosium (Dy) various fullerenes such as C ₈₂ containing therein the various carbon nanotubes, such as a light emitting organic compounds. These compounds can be used in combination of two or more.

（式中、Ｒは、ハロゲン原子などの置換基を有していてもよい炭素数１〜１０のアルキル基、フッ素原子、塩素原子、臭素原子などのハロゲン原子を示す。）

(In formula, R shows halogen atoms, such as a C1-C10 alkyl group which may have a substituent, such as a halogen atom, a fluorine atom, a chlorine atom, and a bromine atom.)

Of these materials, the compound represented by the general formula (I) is particularly preferable, and among them, R is more preferably a trifluoromethyl group bonded to the p-position of the benzene ring.
Since such a compound has a light emitting property, the light emitting semiconductor device 1 can be obtained. In this case, since the semiconductor device 1 has a large ON current, the emission intensity can be further increased.

Although the average thickness of the n-type organic-semiconductor layer 7 is not specifically limited, It is preferable that it is 1-200 nm, and it is more preferable that it is 10-100 nm.
The n-type organic semiconductor layer 7 may be composed of two or more types of n-type organic semiconductor materials, but is preferably composed of a single n-type organic semiconductor material. Thereby, the manufacturing process of the n-type organic-semiconductor layer 7 is simplified, and the semiconductor device 1 can be manufactured easily and at low cost.

On the upper part of the n-type organic semiconductor layer 7, a source electrode 4 and a drain electrode 5 are provided along the channel length L direction with a predetermined distance therebetween. The source electrode 4 and the drain electrode 5 are respectively disposed in contact with the interface between the n-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8 by forming a p-type organic semiconductor layer 8 described later.
Examples of constituent materials of the source electrode 4 and the drain electrode 5 include Ca, Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu, Nb, Ag, In, Ni, Nd, and Co. Or metal materials, such as an alloy containing these, those oxides, etc., conductive organic materials, etc. are mentioned. These can be used in combination of two or more.

Examples of the oxide of the metal material include ITO, FTO, ATO, SnO _{2 and the} like.
Examples of the conductive organic material include polyacetylene, polypyrrole, polythiophene such as PEDOT (poly-ethylenedioxythiophene), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane, or these And conductive polymer materials such as derivatives thereof.

In addition, examples of the constituent material of the source electrode 4 and the drain electrode 5 include carbon materials such as carbon black, carbon nanotube, and fullerene.
Although the average thickness of the source electrode 4 and the drain electrode 5 is not specifically limited, It is preferable that it is 30-300 nm, respectively, and it is more preferable that it is 50-150 nm.
The distance (separation distance) between the source electrode 4 and the drain electrode 5, that is, the channel length L is preferably 2 to 30 μm, and more preferably 5 to 20 μm.

If the channel length L is too smaller than the lower limit value, an error occurs in the channel length L between the obtained semiconductor devices 1 and the semiconductor device characteristics may vary.
On the other hand, if the channel length L is too larger than the upper limit value, the absolute value of the threshold voltage increases, the drain current value decreases, and the characteristics of the semiconductor device 1 may be insufficient.

The channel width in the direction orthogonal to the channel length L is preferably 0.1 to 5 mm, and more preferably 0.5 to 3 mm.
If the channel width is too smaller than the lower limit value, the drain current value becomes small and the characteristics of the semiconductor device 1 may be insufficient.
On the other hand, if the channel width is too larger than the upper limit, the semiconductor device 1 may be increased in size. Moreover, there is a risk of increasing parasitic capacitance and increasing leakage current (gate leakage current) to the substrate / gate electrode 23 via the gate insulating layer 6.

  Each of the source electrode 4 and the drain electrode 5 is preferably composed of a stacked body in which a plurality of layers are stacked. Thereby, different materials can be used for each layer depending on the carriers moving in the channel region. As a result, the efficiency of carrier (electron, hole) injection into the n-type organic semiconductor layer 7 and / or the p-type organic semiconductor layer 8 can be increased.

In the present embodiment, the source electrode 4 and the drain electrode 5 are each configured by a stacked body in which three layers including two layers made of materials having different work functions are stacked.
That is, the source electrode 4 includes a first layer 41 whose lower end surface is in contact with the upper surface of the n-type organic semiconductor layer 7, a second layer 42 whose upper end surface is in contact with the p-type organic semiconductor layer 8, and the first layer 41. And a protective layer 43 located between the first layer 42 and the second layer 42.

The first layer 41 is located in the lower end layer of the stacked body of the source electrodes 4. Therefore, the first layer 41 is a layer having a larger contact area with the n-type organic semiconductor layer 7 than other layers. The first layer 41 has a function of injecting electrons into the n-type organic semiconductor layer 7.
The material constituting the first layer 41 is preferably a material having a lower work function than the other layers, in this embodiment, the second layer 42 and the protective layer 43. Thereby, electrons can be efficiently injected from the first layer 41 into the n-type organic semiconductor layer 7.
The material constituting the first layer 41 is not particularly limited as long as the work function is smaller than the material constituting the second layer 42 and the protective layer 43. For example, Al, Ca, Al and / or Ca are used. Examples thereof include materials containing 70% or more.

In the present embodiment, the first layer 41 is preferably made of calcium, for example. Since calcium has a small work function and high activity, electrons can be efficiently injected into the n-type organic semiconductor layer 7.
The average thickness of the first layer 41 is not particularly limited, but is preferably 2 to 100 nm, and more preferably 5 to 30 nm.

The second layer 42 is located in the upper end layer of the stacked body of the source electrodes 4. Therefore, the second layer 42 is a layer having a larger contact area with the p-type organic semiconductor layer 8 than other layers. The second layer 42 has a function of injecting holes into the p-type organic semiconductor layer 8.
The material constituting the second layer 42 is preferably a material having a higher work function than the other layers, in this embodiment, the first layer 41 and the protective layer 43. Thereby, holes can be efficiently injected into the p-type organic semiconductor layer 8.
The material constituting the second layer 42 is not particularly limited as long as the work function is larger than the material constituting the first layer 41 and the protective layer 43. For example, Pd, Pt, Au, Ni, Cu, and these And alloys mainly composed of

In the present embodiment, the second layer 42 is preferably made of gold, for example. Since gold has a large work function, holes can be efficiently injected into the p-type organic semiconductor layer 8.
The average thickness of the second layer 42 is not particularly limited, but is preferably 2 to 100 nm, and more preferably 5 to 30 nm.

The protective layer 43 is provided in contact with the first layer 41 and the second layer 42. The protective layer 43 has a function of protecting the first layer 41.
The material constituting the protective layer 43 is not particularly limited as long as the material has a work function higher than that of the first layer 41. For example, Al, Pd, Pt, Au, Ni, Cu, or an alloy mainly containing these can be used.

In the present embodiment, the protective layer 43 is preferably made of aluminum, for example. Calcium constituting the first layer 41 is an unstable substance because it has the effects described above and is chemically active. Therefore, the first layer 41 may be deteriorated by driving the semiconductor device 1. Therefore, when the protective layer 43 is made of aluminum, the work function of aluminum is larger than that of calcium, so that the upper end surface of the first layer 41 can be appropriately protected.
In addition, since aluminum has high adhesion to gold, the protective layer 43 and the second layer 42 can be firmly bonded.
Although the average thickness of the protective layer 43 is not specifically limited, It is preferable that it is 2-100 nm, and it is more preferable that it is 5-30 nm.

The drain electrode 5 includes a first layer 51 whose lower end surface is in contact with the upper surface of the n-type organic semiconductor layer 7, a second layer 52 whose upper end surface is in contact with the p-type organic semiconductor layer 8, the first layer 51, and the first layer 51 And a protective layer 53 positioned between the two layers 52.
The first layer 51, the second layer 52, and the protective layer 53 correspond to the first layer 41, the second layer 42, and the protective layer 43 of the source electrode 4, respectively. Therefore, conditions such as a constituent material and a film thickness are the same as those of the first layer 41, the second layer 42, and the protective layer 43 of the source electrode 4, respectively.

  On the n-type organic semiconductor layer 7 including the source electrode 4 and the drain electrode 5, a p-type organic semiconductor layer 8 is formed in contact with the source electrode 4, the drain electrode 5 and the n-type organic semiconductor layer 7. That is, a pn junction including the source electrode 4 and the drain electrode 5 is formed on the gate insulating layer 6 between the n-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8. The p-type organic semiconductor layer 8 is a layer through which holes flow as carriers.

  The constituent material of the p-type organic semiconductor layer is not particularly limited. Low-molecular organic semiconductor materials such as triarylamine, compounds represented by the following general formula (II) or derivatives thereof, poly-N-vinylcarbazole, polyvinylpyrene, fluorene-bithiophene copolymers or derivatives thereof , Polyvinyl anthracene, polythiophene, poly (p-phenylene vinylene), high molecular organic semiconductor materials such as pyrene formaldehyde resin, ethyl carbazole formaldehyde resin, low molecular or high molecular compounds exhibiting luminescence And organic semiconductor material and the like, can be used singly or in combination of two or more of them.

Of these, the compound represented by the general formula (II) or a polymer organic semiconductor material is preferably used as the main material.
Since the compound represented by the general formula (II) has a light emitting property, the light emitting semiconductor device 1 can be obtained. In this case, since the semiconductor device 1 has a large ON current, the emission intensity can be increased.

On the other hand, the polymer organic semiconductor material can reduce the thickness and weight of the p-type organic semiconductor layer 8 and is excellent in flexibility. Therefore, it is suitable for a thin film semiconductor device used as a switching element of a flexible display. Yes.
Moreover, it is preferable that the p-type organic semiconductor layer 8 can be formed at a low temperature. This makes it possible to manufacture at a low cost. In addition, an effect is obtained that a plastic substrate which is an inexpensive flexible substrate can be used.
For this reason, as the high molecular organic semiconductor material (conjugated polymer material), at least one of a fluorene-bithiophene copolymer, a fluorene-arylamine copolymer, a polyarylamine, or a derivative thereof is used. It is particularly preferable to use a material containing as a main component.

The average thickness of the p-type organic semiconductor layer 8 is not particularly limited, but is preferably about 1 to 200 nm, and more preferably about 10 to 100 nm.
The p-type organic semiconductor layer 8 may be composed of two or more types of p-type organic semiconductor materials, but is preferably composed of a single p-type organic semiconductor material. Thereby, the manufacturing process of the p-type organic semiconductor layer 8 is simplified, and the semiconductor device 1 can be manufactured easily and at low cost.

For example, such a semiconductor device 1 operates as follows.
When a gate voltage (positive or negative) is applied to the substrate / gate electrode 23 while the source electrode 4 and the drain electrode 5 are energized, near the interface between the n-type organic semiconductor layer 7 and the gate insulating layer 6 or p-type A channel is formed in the vicinity of the interface between the organic semiconductor layer and the n-type organic semiconductor layer 7. Then, current flows between the source electrode 4 and the drain electrode 5 due to carriers moving in the channel region.

That is, in the OFF state in which no voltage is applied to the substrate / gate electrode 23, even if a voltage is applied between the source electrode 4 and the drain electrode 5, the n-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8 Since there are almost no carriers, only a small current flows.
In the ON state in which a positive voltage is applied to the substrate / gate electrode 23, charges are induced in the portion of the n-type organic semiconductor layer 7 facing the gate insulating layer 6, and a channel (electron flow path) is formed. . When a voltage is applied between the source electrode 4 and the rain electrode 5 in this state, a current flows through the channel region 71. Such an operation is a so-called n-type drive.

On the other hand, in the ON state in which a negative voltage is applied to the substrate / gate electrode 23, charges are induced in a portion of the p-type organic semiconductor layer 8 facing the n-type organic semiconductor layer 7, and a channel (hole flow path) is induced. Is formed. When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel region 81. Such an operation is a so-called p-type drive.
The method for manufacturing the semiconductor device 1 as described above will be described in detail later.

Second Embodiment
Next, a second embodiment of the semiconductor device of the present invention will be described.
FIG. 2 is a schematic view showing a second embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 2 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the second embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

  In the semiconductor device 1 shown in FIG. 2, a first gate insulating layer 61 is formed on the upper surface of the substrate / gate electrode 23 that also serves as the substrate 2 and the first gate electrode 31, and the n-type organic semiconductor layer 7 is formed on the upper surface. Is formed. On top of the n-type organic semiconductor layer 7, a source electrode 4 and a drain electrode 5 formed of a three-layered laminate are provided apart from each other. A p-type organic semiconductor layer 8 is formed so as to cover the upper surface of the n-type organic semiconductor layer 7 including the source electrode 4 and the drain electrode 5. A second gate insulating layer 62 is formed on the upper surface of the p-type organic semiconductor layer 8, and a second gate electrode 32 is formed on the upper surface. That is, the semiconductor device 1 shown in FIG. 2 is a double gate type semiconductor device 1.

Hereinafter, the configuration of each part of the semiconductor device 1 will be described sequentially.
The first gate electrode 31 is synonymous with the gate electrode 3 of the first embodiment, and the first insulating layer 61 is synonymous with the gate insulating layer 6 of the first embodiment.
A second gate insulating layer 62 is provided on the p-type organic semiconductor layer 8 so as to cover a part between the source electrode 4 and the drain electrode 5 and a part of the source electrode 4 and the drain electrode 5. . The second gate insulating layer 62 insulates the second gate electrode 32 from the source electrode 4 and the drain electrode 5.

The constituent material and average thickness of the second gate insulating layer 62 are the same as the constituent material and average thickness of the gate insulating layer 6 of the first embodiment.
Note that the second gate insulating layer 62 is not limited to a single layer structure, and may have a multilayer structure.
On the upper surface of the second gate insulating layer 62, a second gate electrode 32 that is electrically independent from the first gate electrode 31 (substrate / gate electrode 23) is provided.

Examples of the constituent material of the second gate electrode 32 include the same materials as those described for the source electrode 4 and the drain electrode 5 described in the first embodiment.
The average thickness of the second gate electrode 90 is not particularly limited, but is preferably about 0.1 to 5000 nm, more preferably about 1 to 5000 nm, and still more preferably about 10 to 5000 nm. .

In such a semiconductor device 1, the n-type organic semiconductor layer 7 can be controlled using the substrate / gate electrode 23, and the p-type organic semiconductor layer 8 can be controlled using the second gate electrode 32. The p-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8 can be controlled independently. As a result, the semiconductor device 1 can be made highly functional and multifunctional.
In particular, when light-emitting organic materials are used as the constituent material of the n-type organic semiconductor layer 7 and the constituent material of the p-type organic semiconductor layer 8, the injection amounts of electrons and holes necessary for light emission can be controlled independently. Therefore, the emission intensity can be increased and the emission intensity can be easily controlled.

The source electrode 4, the drain electrode 5, the n-type organic semiconductor layer 7, and the p-type organic semiconductor layer 8 are the same as in the first embodiment.
In such a semiconductor device 1, when a gate voltage (positive or negative) is applied to the substrate / gate electrode 23 and the second gate electrode 32 while the source electrode 4 and the drain electrode 5 are energized, the source electrode 4 A channel is formed between the drain electrode 5 and the drain electrode 5. Then, current flows between the source electrode 4 and the drain electrode 5 due to carriers moving in the channel region.

Hereinafter, the operation of the semiconductor device 1 according to the present embodiment will be described for each combination of voltage application to the substrate / gate electrode 23 and the second gate electrode 32.
[1] In the case where no voltage is applied to the substrate / gate electrode 23 and the second gate electrode 32 In this case, the semiconductor device 1 is in an OFF state, and even if a voltage is applied between the source electrode 4 and the drain electrode 5. Since there are almost no carriers in the n-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8, only a very small current flows.

[2] When a voltage is applied only to the substrate / gate electrode 23 In the ON state where a positive voltage is applied to the substrate / gate electrode 23, a charge is applied to the portion of the n-type organic semiconductor layer 7 facing the first insulating layer 61. Is induced to form a channel (electron flow path). When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel region 71. Such an operation is a so-called n-type drive.
On the other hand, in the ON state in which a negative voltage is applied to the substrate / gate electrode 23, charges are induced in the portion of the p-type organic semiconductor layer 8 facing the n-type organic semiconductor layer 7 to form a channel (hole flow path). Is done. When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel region 81. Such an operation is a so-called p-type drive.

[3] When a voltage is applied only to the second gate electrode 32 In the ON state where a positive voltage is applied to the second gate electrode 32, a portion of the n-type organic semiconductor layer 7 facing the p-type organic semiconductor layer 8 An electric charge is induced to form a channel (electron flow path). When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel region 72. Such an operation is a so-called n-type drive.
On the other hand, in the ON state in which a negative voltage is applied to the second gate electrode 32, charges are induced in the portion of the p-type organic semiconductor layer 8 facing the second insulating layer 62, and a channel (hole flow path) is formed. It is formed. When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel region 82. Such an operation is a so-called p-type drive.

[4] When a voltage is applied to the substrate / gate electrode 23 and the second gate electrode 32 [4-1] When a positive voltage is applied to the substrate / gate electrode 23 and the second gate electrode 32 A charge derived from the voltage application of the gate electrode 23 is induced in the portion of the n-type organic semiconductor layer 7 facing the first insulating layer 61, and a channel (electron flow path) is formed.
In addition, a charge derived from the voltage application of the second gate electrode 32 is induced in a portion of the n-type organic semiconductor layer 7 facing the p-type organic semiconductor layer 8 to form a channel (electron flow path).
When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel regions 71 and 72. Such an operation is a so-called n-type drive.

[4-2] When a negative voltage is applied to the substrate / gate electrode 23 and the second gate electrode 32 The charge resulting from the voltage application of the substrate / gate electrode 23 is the n-type organic of the p-type organic semiconductor layer 8. A channel (hole flow path) is formed by being induced in the portion facing the semiconductor layer 7.
In addition, a charge derived from the voltage application of the second gate electrode 32 is induced in a portion of the p-type organic semiconductor layer 8 facing the second insulating layer 62, and a channel (hole flow path) is formed.
When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel regions 81 and 82. Such an operation is a so-called p-type drive.

[4-3] When a positive voltage is applied to the substrate / gate electrode 23 and a negative voltage is applied to the second gate electrode 32, the charge resulting from the voltage application of the substrate / gate electrode 23 is the first of the n-type organic semiconductor layer 7. A channel (electron flow path) is formed by being induced in the portion facing the insulating layer 61.
In addition, a charge derived from the voltage application of the second gate electrode 32 is induced in a portion of the p-type organic semiconductor layer 8 facing the second insulating layer 62, and a channel (hole flow path) is formed.
When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel regions 71 and 82. Such an operation is a so-called p-type or n-type drive.

[4-4] When a negative voltage is applied to the substrate / gate electrode 23 and a positive voltage is applied to the second gate electrode 32, the charge resulting from the voltage application of the substrate / gate electrode 23 is the n-type of the p-type organic semiconductor layer 8. A channel (hole flow path) is formed by being induced in the portion facing the organic semiconductor layer 7.
In addition, a charge derived from the voltage application of the second gate electrode 32 is induced in a portion of the n-type organic semiconductor layer 7 facing the p-type organic semiconductor layer 8 to form a channel (electron flow path).

When a voltage is applied between the source electrode 4 and the drain electrode 5 in this state, a current flows through the channel regions 81 and 72. Such an operation is a so-called p-type or n-type drive.
Such a semiconductor device 1 can be manufactured as follows, for example. Hereinafter, a method for manufacturing the semiconductor device 1 of the present embodiment will be described.

3 and 4 are schematic longitudinal sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. In the following description, the upper side in FIGS. 3 and 4 is referred to as “upper” and the lower side is referred to as “lower”.
The method for manufacturing the semiconductor device 1 shown in FIG. 2 includes: [A1] forming a first gate insulating layer 61 on the substrate / gate electrode 23; [A2] n-type organic on the first gate insulating layer 61. Forming the semiconductor layer 7, [A3] forming the source electrode 4 and the drain electrode 5 on the n-type organic semiconductor layer 7, and [A4] covering the source electrode 4 and the drain electrode 5 with the n-type. A step of forming the p-type organic semiconductor layer 8 on the organic semiconductor layer 7; [A5] a step of forming the second gate insulating layer 62 on the second gate electrode 32; and [A6] a p-type organic semiconductor layer. 8 and the step of bonding the second gate insulating layer 62 on which the second gate electrode 32 is formed. Hereinafter, each process will be described sequentially.
Note that the semiconductor device 1 of the first embodiment is obtained up to the step [A4].

[A1] First Gate Insulating Layer Formation Step First, as shown in FIG. 3A, for example, a silicon substrate (substrate / gate electrode 23) in which boron is heavily doped on the substrate 2 is prepared.
The doping method can be performed by, for example, a microwave plasma CVD method while bubbling a solution of boron oxide with hydrogen.
The boron doping may be, for example, the entire silicon substrate or a part thereof.
Moreover, the material to dope is not specifically limited, For example, phosphorus, aluminum, antimony etc. are mentioned.

Next, as shown in FIG. 3B, a first gate insulating layer 61 is formed on the upper surface of the obtained substrate / gate electrode 23.
For example, when the substrate / gate electrode 23 is made of a silicon substrate, the gate insulating layer 61 made of silica (SiO ₂ ) can be formed on the substrate / gate electrode 23 by thermal oxidation.

When the gate insulating layer 61 is made of an inorganic material, the gate insulating layer 61 can be formed by, for example, a CVD method or an SOG method. Further, by using polysilazane as a raw material, a silica film and a silicon nitride film can be formed as a gate insulating layer 61 by a wet process.
When the gate insulating layer 61 is composed of an organic polymer material, the gate insulating layer 61 is necessary after applying (supplying) a solution containing the organic polymer material or a precursor thereof onto the substrate / gate electrode 23. Accordingly, the coating film can be formed by subjecting it to a post-treatment (for example, heating, irradiation with infrared rays, application of ultrasonic waves, etc.).
As a method for applying (supplying) a solution containing an organic polymer material or a precursor thereof onto the substrate / gate electrode 23, for example, a coating method such as a spin coating method or a dip coating method, an inkjet printing method (droplet) And a printing method such as a screen printing method.

[A2] n-Type Organic Semiconductor Layer Formation Step As shown in FIG. 3C, the n-type organic semiconductor layer 7 is formed on the gate insulating layer 61.
The n-type organic semiconductor layer 7 is formed by a vapor deposition method or a coating method using a spin coater method, a dip method, or a printing method using an ink jet method, a screen printing method, or the like by making it soluble using a precursor. After forming a coating film by using, it can be formed into a desired one by annealing the coating film.

[A3] Source and Drain Electrode Formation Step Next, the source electrode 4 and the drain electrode 5 are formed on the n-type organic semiconductor layer 7.
First, as shown in FIG. 3D, the first layers 41 and 51 are formed. Then, as shown in FIG. 4E, the protective layers 43 and 53 and the second layers 42 and 52 are sequentially laminated on the first layers 41 and 51 in this order.

The method of forming each layer is, for example, a vacuum film forming method such as sputtering using a mask, a chemical vapor deposition method (CVD) such as plasma CVD, thermal CVD, or laser CVD, vacuum plating, or dry plating such as ion plating. It can be formed by a wet plating method such as a method, electrolytic plating, immersion plating, electroless plating, thermal spraying method, sol-gel method, MOD method, bonding of sheet materials, or the like.
The formation of each layer is preferably performed continuously. Thereby, the source electrode 4 and the drain electrode 5 in which the adhesiveness of each layer is favorable can be obtained.

[A4] P-type Organic Semiconductor Layer Formation Step As shown in FIG. 4F, a p-type organic semiconductor layer 8 is formed on the n-type organic semiconductor layer 7 so as to cover the source electrode 4 and the drain electrode 5.
When the p-type organic semiconductor layer 8 is composed of a polymer organic semiconductor material, it is formed using a coating method using a spin coater method, a dip method, or the like, a printing method using an ink jet method, a screen printing method, or the like. Can do.

  Further, when the p-type organic semiconductor layer 8 is composed of a low-molecular organic semiconductor material, a coating method using a spin coater method, a dip method, or the like by making it soluble using a vapor deposition method or a precursor, an inkjet method After forming a coating film using a printing method using a screen printing method or the like, the coating film can be formed into a desired one by annealing the coating film.

Note that the formation region of the p-type organic semiconductor layer 8 is not limited to the illustrated configuration, and may be formed only in a region (channel region) between the source unit 4 and the drain unit 5. Thereby, when a plurality of semiconductor devices 1 are arranged side by side on the same substrate, the p-type machine semiconductor layer 8 of each device 1 is formed independently, thereby suppressing leakage current and crosstalk between elements. be able to. Moreover, the usage-amount of organic-semiconductor material can be reduced and manufacturing cost can also be reduced.
Through the steps as described above, the semiconductor device 1 according to the first embodiment as shown in FIG. 1 can be manufactured.

[A5] Second Gate Insulating Layer Forming Step Next, as shown in FIG. 4G, a second gate insulating layer 62 is formed on the second gate electrode 32.
The second gate insulating layer 62 can be formed by a method similar to that for the first gate insulating layer 61.

[A6] Second Gate Insulating Layer Joining Step Finally, as shown in FIG. 4H, the second gate insulating layer 62 in which the second gate electrode 32 is formed on the upper surface of the p-type organic semiconductor layer 8. Join.
This bonding is performed, for example, by bringing the second gate insulating layer 62 into contact with the p-type organic semiconductor layer 8 and pressing and fixing the second gate insulating layer 62 from above the second gate electrode 32. be able to.
The method of pressing and fixing is not particularly limited. For example, the pressing and fixing method may be attached to the interface between the second gate insulating layer 62 and the p-type organic semiconductor layer 8 via an adhesive or the like. The second gate insulating layer 62 may be pressure bonded to the layer 8.
Through the steps as described above, the semiconductor device 1 shown in FIG. 2 is obtained.

<Third Embodiment>
Next, a third embodiment of the semiconductor device of the present invention will be described.
FIG. 5 is a schematic view showing a third embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 5 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the third embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

The semiconductor device 1 shown in FIG. 5 is the same as that of the first embodiment except that the source electrode 4 and the drain electrode 5 do not have the protective layers 43 and 53, respectively, and are formed of a two-layered laminate.
The source electrode 4 has a first layer 41 whose lower end surface is in contact with the upper surface of the n-type organic semiconductor layer 7 and a second layer 42 whose upper end surface is in contact with the p-type organic semiconductor layer 8.
The drain electrode 5 has a first layer 51 whose lower end surface is in contact with the upper surface of the n-type organic semiconductor layer 7, and a second layer 52 whose upper end surface is in contact with the p-type semiconductor layer 8.

Thus, unlike the first embodiment, since the protective layers 43 and 53 are not provided, the source electrode 4 and the drain electrode 5 can be formed easily and quickly.
In the present embodiment, such first layers 41 and 51 are preferably made of aluminum, for example. Since aluminum is a material having a relatively low work function, electrons can be efficiently injected into the n-type organic semiconductor layer 7.
Note that, in the semiconductor device 1 according to the present embodiment, the same operations and effects as in the first embodiment can be obtained.

<Fourth embodiment>
Next, a fourth embodiment of the semiconductor device of the present invention will be described.
FIG. 6 is a schematic view showing a fourth embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the fourth embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

The semiconductor device 1 shown in FIG. 6 is the same as that of the first embodiment except that the source electrode 4 and the drain electrode 5 are each formed of a single layer instead of being formed of a stacked body.
In this embodiment, the material constituting the source electrode 4 and the drain electrode 5 is preferably aluminum, for example. Since aluminum is a material having a relatively low work function, electrons can be efficiently injected into the n-type organic semiconductor layer 7.
Moreover, since the source electrode 4 and the drain electrode 5 are each a single layer, the source electrode 4 and the drain electrode 5 can be formed more easily and quickly.
Note that, in the semiconductor device 1 according to the present embodiment, the same operations and effects as in the first embodiment can be obtained.

<Fifth Embodiment>
Next, a semiconductor device according to a fifth embodiment of the present invention will be described.
FIG. 7 is a schematic view showing a fifth embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 7 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the fifth embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

The semiconductor device 1 according to the present embodiment is the same except that the stacking order of the n-type organic semiconductor layer 7 and the p-type organic semiconductor layer 8 is different from that of the layers of the source electrode 4 and the drain electrode 5. This is the same as in the first embodiment.
That is, in the semiconductor device 1 of the present embodiment shown in FIG. 7, the gate insulating layer 6 is formed on the upper surface of the substrate / gate electrode 23 that also serves as the substrate 2 and the gate electrode 3, and the p-type organic semiconductor layer 8 is formed on the upper surface. Is formed. On top of this p-type organic semiconductor layer 8, a source electrode 4 and a drain electrode 5 formed of a three-layered laminate are provided apart from each other. An n-type organic semiconductor layer 7 is formed so as to cover the upper surface of the p-type organic semiconductor layer 8 including the source electrode 4 and the drain electrode 5.

The source electrode 4 includes a second layer 42 having a lower end surface in contact with the upper surface of the p-type organic semiconductor layer 8, a first layer 41 having an upper end surface in contact with the n-type semiconductor layer 7, a first layer 41, and a second layer. And a protective layer 43 positioned between the first layer 42 and the second layer 42.
The drain electrode 5 includes a second layer 52 whose lower end surface is in contact with the upper surface of the p-type organic semiconductor layer 8, a first layer 51 whose upper end surface is in contact with the n-type organic semiconductor layer 7, the first layer 51, and the first layer 51. And a protective layer 53 positioned between the two layers 52.
In such a manufacturing method of the semiconductor device 1, the order of the steps [A2] to [A4] described in the second embodiment may be performed in the order of the steps [A4] to [A2].
Note that, in the semiconductor device 1 according to the present embodiment, the same operations and effects as in the first embodiment can be obtained.

<Sixth Embodiment>
Next, a sixth embodiment of the semiconductor device of the present invention will be described.
FIG. 8 is a schematic view showing a sixth embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 8 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the sixth embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

The semiconductor device 1 shown in FIG. 8 is the same as that of the first embodiment except that the substrate 2 and the gate electrode 3 are used separately instead of using the substrate and gate electrode 23.
That is, in the semiconductor device 1 of this embodiment shown in FIG. 8, the gate electrode 3 is formed on the upper surface of the substrate 2, and the gate insulating layer 6 is formed on the substrate 2 including the gate electrode 3 so as to cover the gate electrode 3. Is formed. An n-type organic semiconductor layer 7 is formed on the upper surface of the gate insulating layer 6. On top of the n-type organic semiconductor layer 7, a source electrode 4 and a drain electrode 5 formed of a three-layered laminate are provided apart from each other. A p-type organic semiconductor layer 8 is formed so as to cover the upper surface of the n-type organic semiconductor layer 7 including the source electrode 4 and the drain electrode 5.

Thus, by forming the gate electrode 3 on the substrate 2, the gate electrode 3 made of a predetermined conductive material exists in the semiconductor device 1. It can be driven reliably.
Examples of the constituent material of the substrate 2 include the insulating substrate described in the first embodiment.
The average thickness of the substrate 2 is the same as that of the substrate / gate electrode 23 described in the first embodiment.

Examples of the constituent material of the gate electrode 3 include the same materials as those of the source electrode 4 and the drain electrode 5 described in the first embodiment.
The average thickness of the gate electrode 3 is the same as that of the second gate electrode 32 described in the second embodiment.
Note that, in the semiconductor device 1 according to the present embodiment, the same operations and effects as in the first embodiment can be obtained.

<Seventh embodiment>
Next, a seventh embodiment of the semiconductor device of the present invention will be described.
FIG. 9 is a schematic view showing a seventh embodiment of the semiconductor device of the present invention. In the following description, the upper side in FIG. 9 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the semiconductor device according to the seventh embodiment will be described. However, differences from the semiconductor device according to the first embodiment will be mainly described, and description of similar matters will be omitted.

The semiconductor device 1 shown in FIG. 9 has a pn junction in which an n-type organic semiconductor layer 7 and a p-type organic semiconductor layer 8 are bonded to each other between a source electrode 4 and a drain electrode 5. This is the same as in the first embodiment.
That is, in the semiconductor device 1 of this embodiment, the gate insulating layer 6 is formed on the upper surface of the substrate / gate electrode 23 that also serves as the substrate 2 and the gate electrode 3, and the source electrode is formed of a three-layer laminate on the upper portion. 4 and the drain electrode 5 are provided apart from each other. A pn junction is formed so as to fill between the source electrode 4 and the drain electrode 5. The pn junction 9 is disposed on the upper surface of the gate layer insulating layer 6 in contact with the source electrode 4 and the drain electrode 5.

In this way, by arranging the pn junction between the source electrode 4 and the drain electrode 5, the vicinity of the interface between the n-type organic semiconductor layer 7 and the gate insulating layer 6 (channel region 71) and the p-type organic semiconductor. The vicinity of the interface between the layer 8 and the n-type organic semiconductor layer 7 (channel region 81) is formed between the source electrode 4 and the drain electrode 5. Therefore, the distance that the electrons move and the distance that the holes move can be made shorter. As a result, the ON current of the semiconductor device 1 can be increased, and ON / OFF is improved.
Note that, in the semiconductor device 1 according to the present embodiment, the same operations and effects as in the first embodiment can be obtained.
Such a semiconductor device 1 can be manufactured as follows, for example.

Hereinafter, a method for manufacturing the semiconductor device 1 of the present embodiment will be described.
The manufacturing method of the semiconductor device 1 of the present embodiment shown in FIG. 9 includes [B1] a step of forming the gate insulating layer 6 on the substrate / gate electrode 23, and [B2] an n-type organic semiconductor layer on the gate insulating layer 6. 7, [B3] a step of forming a p-type organic semiconductor layer 8 on the n-type organic semiconductor layer 7, and [B4] an n-type organic semiconductor layer 7 and a p-type organic semiconductor layer 8 are stacked. Forming the source electrode 4 and the drain electrode 5 so as to sandwich the pn junction 9. Hereinafter, each process will be described sequentially.

[B1] Gate Insulating Layer Formation Step The gate insulating layer is formed by the same method as in the [A1] step.
[B2] n-type Organic Semiconductor Layer Formation Step The n-type organic semiconductor layer 7 is formed by, for example, placing a mask having an opening corresponding to the pn junction 9 on the upper surface of the gate insulating layer 6 [A2] It can be performed by the same method as in the step.

[B3] Step of forming p-type organic semiconductor layer The formation of the p-type organic semiconductor layer 8 can be performed by the same method as the step [A4] using the mask following the step [B2]. Thereby, the pn junction body 9 is obtained.
[B4] Source and drain electrode formation step The mask is removed from the gate insulating layer 6. When a plate-like mask is used, it can be removed by separating the mask from the gate insulating layer 6, for example.

Next, a mask having openings corresponding to the source electrode 4 and the drain electrode 5 is provided on the upper surfaces of the p-type organic semiconductor layer 8 and the gate insulating layer 6, and the source electrode 4 and the drain are formed in the same manner as in the step [A3]. The electrode 5 is formed.
Thereafter, the mask is removed from the p-type organic semiconductor layer 8 and the gate insulating layer 6.
Through the steps as described above, the semiconductor device 1 shown in FIG. 9 is obtained.
In addition, after forming the source electrode 4 and the drain electrode 5 on the gate insulating layer 6 ([B4] process), between the source electrode 4 and the drain electrode 5, the n-type organic-semiconductor layer 7 ([B2] process) and The p-type organic semiconductor layer 8 ([B3] step) may be joined to form the pn junction 9.

<Semiconductor circuit and electro-optical device>
Next, an electrophoretic display device will be described as an example of the electro-optical device of the present invention in which the active matrix device (semiconductor circuit of the present invention) including the semiconductor device 1 as described above is incorporated.
FIG. 10 is a longitudinal sectional view showing an embodiment of the electrophoretic display device, and FIG. 11 is a block diagram showing a configuration of an active matrix device included in the electrophoretic display device shown in FIG.
An electrophoretic display device 200 shown in FIG. 10 includes an active matrix device provided on a substrate 500 and an electrophoretic display unit 400 electrically connected to the active matrix device.

As shown in FIG. 11, the active matrix device 300 includes a plurality of data lines 301 orthogonal to each other, a plurality of scanning lines 302, and a semiconductor device provided near each intersection of the data lines 301 and the scanning lines 302. 1.
The gate electrode 3 of the semiconductor device 1 is connected to the scanning line 302, the source electrode 4 is connected to the data line 301, and the drain electrode 5 is connected to a pixel electrode (individual electrode) 401 described later.

As shown in FIG. 10, the electrophoretic display unit 400 includes a pixel electrode 401, a microcapsule 402, a transparent electrode (common electrode) 403, and a transparent substrate 404 that are sequentially stacked on a substrate 500. Yes.
The microcapsule 402 is fixed between the pixel electrode 401 and the transparent electrode 403 by a binder material 405.

The pixel electrodes 401 are divided so as to be regularly arranged in a matrix, that is, vertically and horizontally.
In each capsule 402, an electrophoretic dispersion liquid 420 including a plurality of types of electrophoretic particles having different characteristics, and in this embodiment, two types of electrophoretic particles 421 and 422 having different charges and colors (hues) are encapsulated. Has been.

In such an electrophoretic display device 200, when a selection signal (selection voltage) is supplied to one or a plurality of scanning lines 302, the semiconductor connected to the scanning line 302 to which the selection signal (selection voltage) is supplied. The device 1 is turned on.
Thereby, the data line 301 and the pixel electrode 401 connected to the semiconductor device 1 are substantially conducted. At this time, if desired data (voltage) is supplied to the data line 301, this data (voltage) is supplied to the pixel electrode 401.

As a result, an electric field is generated between the pixel electrode 401 and the transparent electrode 403, and the electrophoretic particles 421 and 422 are either one of the electrophoretic particles 421 and 422 depending on the direction and strength of the electric field and the characteristics of the electrophoretic particles 421 and 422. Electrophoresis towards the electrode.
On the other hand, when the supply of the selection signal (selection voltage) to the scanning line 302 is stopped from this state, the semiconductor device 1 is turned off, and the data line 301 and the pixel electrode 401 connected to the semiconductor device 1 are not conductive. It becomes a state.

Therefore, by appropriately combining the supply and stop of the selection signal to the scanning line 302 or the supply and stop of the data to the data line 301, the display surface side (transparent substrate 404 side) of the electrophoretic display device 200 is provided. A desired image (information) can be displayed.
In particular, in the electrophoretic display device 200 according to the present embodiment, it is possible to display a multi-tone image by changing the colors of the electrophoretic particles 421 and 422.

In addition, since the electrophoretic display device 200 according to the present embodiment has the active matrix device 300, the semiconductor device 1 connected to the specific scanning line 302 can be selectively turned on and off. Since the problem of crosstalk hardly occurs and the speed of circuit operation can be increased, a high-quality image (information) can be obtained.
In addition, since the electrophoretic display device 200 according to the present embodiment operates with a low driving voltage, power saving can be achieved.

Note that the electro-optical device in which the active matrix device including the semiconductor device 1 as described above is incorporated is not limited to the application to the electrophoretic display device 200, for example, a liquid crystal device, organic or inorganic The present invention can also be applied to a display device such as an EL device or a light emitting device.
In each of the above embodiments, the semiconductor device including two gate electrodes has been described. However, the semiconductor device of the present invention may include three or more gate electrodes.

<Electronic equipment>
Such an electrophoretic display device 200 can be incorporated into various electronic devices. Hereinafter, an electronic apparatus of the present invention including the electrophoretic display device 200 will be described.
<< Electronic Paper >>
First, an embodiment when the electronic apparatus of the present invention is applied to electronic paper will be described.

FIG. 12 is a perspective view showing an embodiment when the electronic apparatus of the present invention is applied to electronic paper.
An electronic paper 600 shown in this figure includes a main body 601 composed of a rewritable sheet having the same texture and flexibility as paper, and a display unit 602.
In such electronic paper 600, the display unit 602 includes the electrophoretic display device 200 as described above.

<< Display >>
Next, an embodiment when the electronic apparatus of the present invention is applied to a display will be described.
13A and 13B are diagrams showing an embodiment in which the electronic apparatus of the present invention is applied to a display. FIG. 13A is a cross-sectional view, and FIG. 13B is a plan view.
A display 800 shown in this figure includes a main body 801 and an electronic paper 600 that is detachably provided to the main body 801. The electronic paper 600 has the same configuration as described above, that is, the configuration shown in FIG.

  The main body 801 has an insertion port 805 into which the electronic paper 600 can be inserted on its side (right side in the drawing), and two pairs of conveying rollers 802a and 802b are provided inside. When the electronic paper 600 is inserted into the main body 801 through the insertion port 805, the electronic paper 600 is installed in the main body 801 in a state of being sandwiched between the transport roller pairs 802a and 802b.

  In addition, a rectangular hole 803 is formed on the display surface side of the main body 801 (the front side of the drawing in the lower diagram (b)), and a transparent glass plate 804 is fitted into the hole 803. Thereby, the electronic paper 600 installed in the main body 801 can be viewed from the outside of the main body 801. That is, in the display 800, the display surface is configured by visually recognizing the electronic paper 600 installed in the main body 801 on the transparent glass plate 804.

In addition, a terminal portion 806 is provided at the leading end portion (left side in the drawing) of the electronic paper 600, and the terminal portion with the electronic paper 600 installed on the main body portion 801 is provided inside the main body portion 801. A socket 807 to which 806 is connected is provided. A controller 808 and an operation unit 809 are electrically connected to the socket 807.
In such a display 800, the electronic paper 600 is detachably installed on the main body 801, and can be carried and used while being detached from the main body 801.
Further, in such a display 800, the electronic paper 600 is configured by the electrophoretic display device 200 as described above.

  Note that the electronic apparatus of the present invention is not limited to the application to the above, and for example, a television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, an electronic Examples include newspapers, word processors, personal computers, workstations, videophones, POS terminals, and devices equipped with touch panels. The electrophoretic display device 200 can be applied to the display units of these various electronic devices. is there.

Although the semiconductor device, the semiconductor circuit, the electro-optical device, and the electronic apparatus according to the invention have been described above, the invention is not limited to these.
For example, the configuration of each part of the semiconductor device, the semiconductor circuit, the electro-optical device, and the electronic apparatus of the present invention can be replaced with any component that can exhibit the same function, or can be added with any configuration. You can also.
Further, the configuration of the semiconductor device of the present invention may be a configuration in which two or more of the above embodiments are combined.
In the semiconductor device of the present invention, the strength of the substrate may be given to the gate electrode 3 itself without using the substrate 2.

Next, specific examples of the present invention will be described.
1. Manufacturing of a semiconductor device (Example 1)
<1> Step of forming gate insulating layer First, a heavily doped silicon substrate was prepared.
The surface of this silicon substrate was thermally oxidized at 400 ° C. for 3 hours. As a result, a silicon oxide film (gate insulating layer) was formed.
Note that the thickness of the silicon oxide film was 400 nm.
<2> Step of forming n-type organic semiconductor layer Next, a compound represented by the following formula (III) was supplied onto the silicon oxide film by vacuum deposition (vacuum degree: 2 × 10 ⁻⁴ Pa) to form a film. Thereby, an n-type organic semiconductor layer was obtained.
The n-type organic semiconductor layer had a thickness of 100 nm.

<3> Source electrode and drain electrode formation process On the obtained n-type organic-semiconductor layer, the mask which has the opening part corresponding to a source electrode and a drain electrode was installed.
And calcium was supplied to the site | part corresponding to the source electrode and drain electrode of an n-type organic-semiconductor layer by vacuum evaporation (vacuum degree 2 * 10 < ^-4 > Pa). Thereby, the first layer of the source electrode and the first layer of the drain electrode were formed on the n-type organic semiconductor layer.

The film thickness of each of the first layer of the source electrode and the first layer of the drain electrode was 30 nm.
Subsequently, aluminum was vacuum-deposited on each first layer by the same method. Thereby, the protective layer was laminated | stacked on each 1st layer. The thickness of this protective layer was 30 nm.
Furthermore, gold was vacuum-deposited on each protective layer by the same method. Thereby, the second layer was laminated on each protective layer. The thickness of this second layer was 30 nm.
The channel width was 1 mm and the channel length was 10 μm.

<4> p-type organic semiconductor layer formation process Next, the compound represented by the following formula is vacuum-deposited (vacuum degree 2 × 10 ⁻⁴ Pa) on the n-type organic semiconductor layer on which the source electrode and the drain electrode are formed. Supply and film formation. Thereby, a p-type organic semiconductor layer was formed.
The p-type organic semiconductor layer had a thickness of 100 nm.

Through the above steps, a semiconductor device as shown in FIG. 1 was obtained.
(Example 2)
It carried out similarly to the <1> process of Example 1, and obtained the silicon substrate in which the silicon oxide film was formed.
Next, the surface on the oxide film side of the silicon substrate was pressed onto the p-type organic semiconductor layer of the semiconductor device obtained in Example 1 to be fixed and bonded. Thus, a double gate type semiconductor device as shown in FIG. 2 was obtained.

(Example 3)
In Example 1, the same procedure as in Example 1 was performed except that the first layer of the source electrode and the drain electrode was replaced with aluminum and no protective layer was formed, and a semiconductor device as shown in FIG. 5 was obtained.
Example 4
In Example 1, except that the first layer of the source electrode and the drain electrode is replaced with aluminum and the protective layer and the second layer are not formed, the semiconductor device as shown in FIG. Obtained.

(Example 5)
In Example 1, except that the order of forming the n-type organic semiconductor layer, forming the first layer of the source electrode and the drain electrode, forming the protective layer, forming the second layer, and forming the p-type organic semiconductor layer was reversed. In the same manner as in Example 1, a semiconductor device as shown in FIG. 7 was obtained.
(Example 6)
In Example 1, instead of using a heavily doped silicon substrate, the same as in Example 1 except that a gate electrode was formed by depositing gold on the silicon substrate by vacuum deposition (vacuum degree 2 × 10 ⁻⁴ Pa). The semiconductor device as shown in FIG. 8 was obtained.
The thickness of the gate electrode was 30 nm.

(Example 7)
<1> Step of forming gate insulating layer The same process as in Example 1 was performed to form a gate insulating layer on a silicon substrate.
<2> Step of forming n-type organic semiconductor layer A mask having an opening corresponding to the pn junction was placed on the gate insulating layer.
Next, an n-type organic semiconductor layer was formed in the same manner as in Example 1.

<3> Step of forming p-type organic semiconductor layer Subsequently, a p-type organic semiconductor layer was formed in the same manner as in Example 1.
<4> Source and drain electrode formation process The mask was removed from the gate insulating layer. Next, a mask having openings corresponding to the source electrode and the drain electrode was provided on the upper surfaces of the p-type organic semiconductor layer and the gate insulating layer.
And it carried out similarly to Example 1 and formed the source electrode and the drain electrode.
Thus, a semiconductor device as shown in FIG. 9 was obtained.

(Comparative Example 1)
<1> Step of forming gate insulating layer The same process as in Example 1 was performed to form a gate insulating layer on a silicon substrate.
<2> Source electrode and drain electrode formation process On this gate insulating layer, the mask which has the opening part corresponding to a source electrode and a drain electrode was installed.
Next, in the same manner as in Example 1, a source electrode and a drain electrode were formed.

<3> Step of forming n-type organic semiconductor layer Next, the mask was removed from the gate insulating layer.
And it carried out similarly to Example 1, and formed the n-type organic-semiconductor layer on the gate insulating layer so that a source electrode and a drain electrode might be covered.
<4> p-type organic semiconductor layer formation process It carried out similarly to Example 1 and formed the p-type organic-semiconductor layer.
Thus, a conventional semiconductor device was obtained.

2. Evaluation About the semiconductor device manufactured by each Example and the comparative example, using the semiconductor parameter analyzer (Agilent Technology company_made: 4156C), ON current value and OFF current value were measured, and ON / OFF ratio was calculated | required. A specific measuring method is shown below.
<1> ON Current A gate voltage was set to −40V, a potential difference between the source electrode and the drain electrode was set to 30V, and a value of a current flowing between the source electrode and the drain electrode was measured.
<2> OFF current The value of the current flowing between the source electrode and the drain electrode when no gate voltage was applied was measured.
<3> ON / OFF ratio The ON / OFF ratio was determined from the ratio of the drain current when the gate voltage was 0V and when the gate voltage was -40V.
As a result, the semiconductor device of each example had an ON current value of about 10 to 20% higher than the semiconductor device of the comparative example. Therefore, the ON / OFF ratio was also about 10 to 20% higher.
From the above results, since the source electrode and the drain electrode are in contact with the n-type organic semiconductor layer and the p-type organic semiconductor layer, a semiconductor device having a high ON current can be obtained.

1 is a schematic longitudinal sectional view showing a first embodiment of a semiconductor device of the present invention. It is a schematic longitudinal cross-sectional view which shows 2nd Embodiment of the semiconductor device of this invention. It is a figure (longitudinal sectional drawing) for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a figure (longitudinal sectional drawing) for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic longitudinal cross-sectional view which shows 3rd Embodiment of the semiconductor device of this invention. It is a schematic longitudinal cross-sectional view which shows 4th Embodiment of the semiconductor device of this invention. It is a schematic longitudinal cross-sectional view which shows 5th Embodiment of the semiconductor device of this invention. It is a schematic longitudinal cross-sectional view which shows 6th Embodiment of the semiconductor device of this invention. It is a schematic longitudinal cross-sectional view which shows 7th Embodiment of the semiconductor device of this invention. It is a longitudinal cross-sectional view which shows embodiment of an electrophoretic display apparatus. FIG. 11 is a block diagram illustrating a configuration of an active matrix device included in the electrophoretic display device illustrated in FIG. 10. It is a perspective view which shows embodiment at the time of applying the electronic device of this invention to electronic paper. It is a figure which shows embodiment at the time of applying the electronic device of this invention to a display.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Substrate 23 ... Substrate and gate electrode 3 ... Gate electrode 31 ... First gate electrode 32 ... Second gate electrode 4 ... Source electrode 41 ... First layer 42 ...... Second layer 43 ...... Protective layer 5 ...... Drain electrode 51 ...... First layer 52 ...... Second layer 53 ...... Protective layer 6 ...... Gate insulating layer 61 ...... First gate insulating layer 62... Second gate insulating layer 7... N-type organic semiconductor layer 71 and 72... Channel region 8... P-type organic semiconductor layer 81 and 82. Display device 300... Active matrix device 301... Data line 302... Scanning line 400... Electrophoretic display section 401. Electrophoretic particles 403 ... Transparent electrode 404 ... Transparent substrate 405 ... Binder material 500 ... Substrate 600 ... Electronic paper 601 ... Main body 602 ... Display unit 800 ... Display 801 ... Main body 802a, 802b ... Transport roller pair 803 ... Hole 804 ... Transparent glass plate 805 ... Insertion slot 806 ... Terminal part 807 ... Socket 808 ... Controller 809 ... Operation part

Claims (16)

a pn junction in which a p-type organic semiconductor layer and an n-type organic semiconductor layer are bonded to each other;
A source electrode and a drain electrode located in the vicinity of the interface between the p-type organic semiconductor layer and the n-type organic semiconductor layer of the pn junction,
A gate electrode joined to at least one of the p-type organic semiconductor layer and the n-type organic semiconductor layer via a gate insulating layer;
The semiconductor device, wherein the source electrode and the drain electrode are disposed so as to be in contact with both the p-type organic semiconductor layer and the n-type organic semiconductor layer, respectively. A gate electrode, a source electrode, a drain electrode, a gate insulating layer, and a pn junction in which a p-type organic semiconductor layer and an n-type organic semiconductor layer are bonded to each other;
The pn junction is disposed between the source electrode and the drain electrode such that each of the p-type organic semiconductor layer and the n-type organic semiconductor layer is in contact with both the source electrode and the drain electrode. ,
The semiconductor device, wherein the gate electrode is bonded to at least one of the p-type organic semiconductor layer and the n-type organic semiconductor layer of the pn junction through the gate insulating layer. The gate electrode includes a first gate electrode joined to the n-type organic semiconductor layer via a first gate insulating layer;
The semiconductor device according to claim 1, further comprising a second gate electrode joined to the p-type organic semiconductor layer via a second gate insulating layer.   4. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode includes a stacked body formed by stacking a plurality of layers.   The semiconductor device according to claim 4, wherein the stacked body includes two layers made of materials having different work functions.   The semiconductor device according to claim 5, further comprising a protective layer between the two layers.   The semiconductor device according to claim 6, wherein the protective layer is made of aluminum or an alloy mainly containing aluminum.   8. The layer according to claim 4, wherein a layer having a large contact area with the n-type organic semiconductor layer among the layers in the stacked body is made of a material having a work function lower than that of the other layers. Semiconductor device.   The semiconductor device according to claim 8, wherein the material having a low work function is made of aluminum, calcium, or a material containing 70% or more of aluminum or calcium.   10. The layer according to claim 4, wherein a layer having a large contact area with the p-type organic semiconductor layer among the layers in the stacked body is made of a material having a higher work function than the other layers. Semiconductor device.   The semiconductor device according to claim 10, wherein the material having a high work function is made of gold or an alloy mainly containing gold.   The semiconductor device according to claim 1, wherein each of the p-type organic semiconductor layer and the n-type organic semiconductor layer is composed of a light-emitting organic material having semiconductor characteristics. Having a substrate,
The semiconductor device according to claim 1, wherein the gate electrode is built in the substrate.   A semiconductor circuit comprising the semiconductor device according to claim 1.   An electro-optical device comprising the semiconductor circuit according to claim 14.   An electronic apparatus comprising the electro-optical device according to claim 15.

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