JP2008227406A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of applying a universal tensile distortion not depending on a size of a transistor, to a n-channel type MOS transistor. <P>SOLUTION: A high dielectric insulating film is used as a gate insulating film of an n-channel type MOS transistor, and by directly forming this high dielectric insulating film on a semiconductor substrate not through an interface layer, a tensile distortion is given to a channel region. By combining this n-channel type MOS transistor and a p-channel type MOS transistor having a compressive distortion in a channel region, a complementary high performance semiconductor device can be constituted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a complementary MOS transistor having a strained Si channel.

  Advances in Si-LSI elements have been made with higher performance of MOS transistors, which are the basic structural units. Since the performance of the MOS transistor and the carrier (electron, hole) mobility traveling in the channel are closely related, a technique for improving the carrier mobility has attracted attention. One of the mobility enhancement techniques is a strained Si technique. For example, in an n-channel MOS transistor, in order to apply tensile strain to channel Si, a Si layer is formed on the strain-relieved SiGe layer. In a p-channel MOS transistor, a SiN film is formed on the gate electrode. Electron mobility is improved by applying a stressor.

In Patent Document 1, a crystalline metal oxide insulating film having a lattice spacing different from that of the substrate is formed on the channel as a gate insulating film, thereby modulating the lattice spacing of the channel region and improving carrier mobility. I am letting.
JP 2004-214386 A

  However, in the case of a method of forming a Si layer on a strain-relieved SiGe layer, for example, the strained Si layer surface has a high dislocation density, which causes an increase in leakage current. In addition, in the case of the method of covering the stressor with the SiN film, the FET manufacturing process becomes complicated, but the strain amount changes as the FET size changes. For example, the strain amount is changed by changing the SiN film thickness. In addition to redesigning for adjustment, there is a problem that the film peels off if the SiN film is too thick.

  Here, when the gate insulating film is polycrystalline, there is a concern about an increase in leakage current. In addition, in Patent Document 1, since the gate insulating film is an epitaxial film, the Si substrate contains a strain amount of approximately 0.7% almost uniformly from the interface to a region of 50 nm. If such a strain exists over 50 nm, it is vulnerable to mechanical shock, and a slight shock may cause dislocation, that is, crystal defect, to relax the strain and deteriorate device characteristics. As a result, the variation between elements increases.

  In order to fabricate an n-channel MOS transistor and a p-channel MOS transistor, it is necessary to use a gate insulating film made of a different material in order to apply a tensile strain and compressive strain to the channel. Extremely complicated.

  Therefore, an object of the present invention is to provide a complementary MOS transistor that can apply tensile strain independent of the size of the transistor to the channel of the n-channel MOS transistor.

In order to solve the above problems, a first semiconductor device of the present invention includes a semiconductor substrate, a p-type first semiconductor region formed on the semiconductor substrate, and the first semiconductor region on the semiconductor substrate. An n-type second semiconductor region formed insulated from the semiconductor region, an n-channel MOS transistor formed in the first semiconductor region, and a p-channel MOS formed in the second semiconductor region The n-channel MOS transistor is sandwiched between a pair of first source / drain regions formed opposite to each other in the first semiconductor region and the first source / drain region. A first gate insulating film formed on the surface of the first semiconductor region in direct contact and formed of an amorphous insulating film containing at least La; and formed on the first gate insulating film. First made And over gate electrode,
The P-channel MOS transistor includes a pair of second source / drain regions formed opposite to each other in the second semiconductor region and the second source / drain region sandwiched between the second source / drain regions. A second gate insulating film including a silicon oxide film and the amorphous insulating film formed thereon on the surface of the second semiconductor region; and a second gate insulating film formed on the second gate insulating film. 2 gate electrodes.

A second semiconductor device of the present invention is formed by insulating a semiconductor substrate, a p-type first semiconductor region formed on the semiconductor substrate, and the first semiconductor region on the semiconductor substrate. An n-type second semiconductor region, an n-channel MOS transistor formed in the first semiconductor region, a p-channel MOS transistor formed in the second semiconductor region,
The n-channel MOS transistor includes a pair of first source / drain regions formed opposite to each other in the first semiconductor region, and the first source / drain region sandwiched between the first source / drain regions. A first gate insulating film formed on the surface of the first semiconductor region in direct contact and formed of an amorphous insulating film containing at least La; and formed on the first gate insulating film. The p-channel MOS transistor includes a pair of second source / drain regions formed opposite to the second semiconductor region, and the second source / drain. A second gate insulating film including the amorphous insulating film directly formed on the surface of the second semiconductor region sandwiched between the regions, and a second gate insulating film formed on the second gate insulating film. Gate electrode and the second gate Formed on the electrode of the upper and side surfaces, characterized by comprising a stressor insulating film applying compressive stress to the second surface of the second semiconductor substrate under the gate insulating film.

  A third aspect of the semiconductor device of the present invention is a semiconductor substrate, a p-type first Si semiconductor region formed on the semiconductor substrate, and formed on the semiconductor substrate so as to be insulated from the first semiconductor region. An n-type second Si semiconductor region formed; an n-channel MOS transistor formed in the first Si semiconductor region; and a p-channel MOS transistor formed in the second Si semiconductor region. The n-channel MOS transistor includes a pair of first source / drain regions formed opposite to each other in the first Si semiconductor region, and the first source / drain region sandwiched between the first source / drain regions. A first gate insulating film formed of an amorphous insulating film containing at least La and formed on the surface of one Si semiconductor region; and formed on the first gate insulating film. First game The p-channel MOS transistor is formed opposite to the second Si semiconductor region and includes a pair of SiGe layers containing Ge at a concentration of 10% to 20% by atomic ratio. A silicon oxide film and an amorphous insulating film formed thereon on the surface of the second Si semiconductor region sandwiched between the second source / drain region and the second source / drain region. A second gate insulating film, and a second gate electrode formed on the second gate insulating film.

  According to the present invention, it is possible to provide a complementary MOS transistor that can apply tensile strain independent of the size of the transistor to the channel of the n-channel MOS transistor.

Prior to the description of the embodiment, an explanation will be given of the phenomenon in which the LaAlO ₃ film directly bonded to the Si substrate causes tensile strain on the Si substrate based on the knowledge of the present inventors. 1, on a silicon substrate that is removing the natural oxide film with dilute HF treatment, LaAlO ₃ laser ablation method using a single crystal substrate target is a cross-sectional TEM photograph of depositing a LaAlO ₃ film. From this figure, it can be seen that the LaAlO ₃ film is amorphous. When an interface layer made of Si oxide such as SiO ₂ exists between the LaAlO ₃ film and the Si substrate, it is observed as white contrast, but since it is not shown in the figure, It can be seen that there is no direct bonding.

In particular, the LaAlO ₃ film is a stable compound at the Si interface and not only has the property of not generating an interface layer, but also is a high dielectric constant insulating film having a higher dielectric constant than Si. It is a material that can make the equivalent film thickness extremely thin. The present inventors have already published a paper on this (M. Suzuki et al. Ultra thin (EOT = 3Å) and low leakage dielectrics of La-Aluminate directly on Si substrate fabricated by high temperature deposition. Tech. Dig. IEDM. 2005, p.445-448).

FIG. 2 shows the depth profile of each element obtained from RBS (Rutherford Backscattering) analysis. The RBS analysis was performed under so-called channeling conditions in which He ⁺ ions having an energy of 450 keV were incident in the Si <111> axis direction. It can be seen that the composition in the LaAlO ₃ film is the stoichiometric ratio, that is, La: Al: O = 1: 1: 3. Furthermore, the interface with the Si substrate has a steep profile, indicating that it is a direct bond.

Here, in order to analyze the strain of the Si substrate, He ⁺ ions having an energy of 450 keV are 0.2 ° in a range of ± 2 ° from the Si <111> axis (54.7 ° with respect to the normal of the sample surface). The sample was irradiated at a step angle, and He ⁺ ions back-scattered under each irradiation angle condition were detected by a deflection magnetic field type energy analyzer at a scattering angle of 50 °. A plot of the backscattering yield from Si against the He ⁺ ion irradiation angle is shown in FIG. 3 separately for the interface and 1 nm, 2 nm, 3 nm, and 5 nm depth positions from the interface.

When He ⁺ ions are irradiated, if they are irradiated at an angle along the Si crystal axis, the backscattering yield decreases due to the channeling effect. That is, in this measurement, in the case of an undistorted Si substrate, the backscattering yield from Si gives a minimum value on the <111> axis (that is, when the horizontal axis is 0).

  By the way, when the Si substrate has tensile strain, the minimum value shifts from the <111> axis in a positive angle direction. When the Si substrate has compressive strain, the minimum value may shift in the negative angle direction. Are known. From this, it can be seen that in the case of direct bonding this time, the minimum value is shifted in the direction of a positive angle, so that tensile strain is applied to the substrate. Furthermore, it turns out that distortion becomes large as it approaches an interface.

FIG. 4 is a profile in the depth direction by RBS after the film shown in FIG. 1 is heat-treated in an oxygen atmosphere at 600 ° C. for 30 minutes in an oxygen atmosphere. In the figure, there is a region in which only Si and oxygen exist only in the vicinity of the interface (shown as an interface layer in FIG. 4). This indicates that the Si substrate was oxidized by the heat treatment in the oxygen atmosphere, and the interface layer made of SiO ₂ was grown.

In the same manner as in FIG. 3, the backscattered yield from Si with respect to the He ⁺ ion irradiation angle in the sample after the oxygen heat treatment is plotted separately for each depth position in the same manner as in FIG. From the comparison with FIG. 3, in the case of having an interface layer, it can be seen that the minimum value of the curve corresponds substantially to the <111> axis (irradiation angle 0 degree), so that almost no strain is applied.

  Further, the amount of distortion is calculated by the following equation from the magnitude of deviation from the <111> axis of the minimum value of the curve shown in FIGS.

ε = 2Δθ / sin2θ (1)
Here, ε represents a strain amount, Δθ represents an angle amount deviated from the <111> axis, and θ represents a <111> axis, that is, 54.7 ° here.

FIG. 6 shows a depth profile of the distortion amount obtained from this equation. As shown in this figure, it can be seen that a strain of 0.5% or more is applied in the region from the interface to 3 nm, and conversely, when the interface layer is provided, there is almost no strain. This result shows that the strain does not depend on the thickness of the SiO ₂ layer that is the interface layer, so that the Si strain is hardly applied as long as the interface is formed by Si—O—Si bonds. It can be said.

Further, 0 from the interface between the SiO ₂ layer contains tensile strain of 0.8% or more in the region of the Si substrate within at least 1 nm, at least in the region of 3nm deeper Si substrate from the interface between the SiO ₂ layer. It can also be seen that it contains less than 5% tensile strain.

From these facts, it can be said that the large amount of strain in the direct bonding shown in FIG. 6 is caused by the direct bonding of LaAlO ₃ . More specifically, it is considered that Si and La having greatly different atomic radii form a bond called La—O—Si at the bonding interface. Since this amount of strain is determined by the bonding of atoms, it does not depend on the film thickness of the LaAlO ₃ film but also does not depend on the transistor size. Specifically, it does not depend on the area of Si serving as a channel. It is universal. As described above, as a result of directly bonding an insulating film containing La, which is stable at the Si interface and greatly different in atomic radius from Si, to the Si substrate, mobility is improved in an n-channel MOS transistor that requires tensile strain. The

In addition, although direct bonding works disadvantageously for improving the mobility of p-channel MOS transistors that require compressive strain, it can be eliminated by providing a SiO ₂ layer of one atomic layer or more at the interface. If a compressive strain application technique is used, a structure capable of improving mobility in both the n-channel MOS transistor and the p-channel MOS transistor can be realized.

  Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following embodiments, and various modifications can be made without departing from the spirit of the invention.

(First embodiment)
FIG. 7 is a cross-sectional view showing a configuration of a complementary MOS transistor (CMOS transistor) according to the first embodiment. A p-type semiconductor layer 3 and an n-type semiconductor layer 5 are formed on an Si substrate 1 via an element isolation layer 7 made of SiO ₂ . Note that a substrate having an SOI (Silicon On Insulator) structure may be used as the substrate. The n-type semiconductor layer 5 may be a SiGe layer. At this time, the SiGe layer needs to have an atomic ratio of 10% or more in order to contain strain for realizing high mobility, and in order to obtain a defect amount that does not affect the transistor characteristics, The Ge concentration needs to be 20% or less.

An n-channel MOS transistor is formed on the p-type semiconductor layer, and a p-channel MOS transistor is formed on the n-type semiconductor layer. In an n-channel MOS transistor, the gate insulating film on the p-type semiconductor layer has a dielectric constant higher than that of Si, and an amorphous LaAlO ₃ film is directly bonded without having an interface layer, so that Si serving as a channel is formed. The substrate has a tensile strain of 0.5 to 1% at least from the interface to a region of 3 nm. At this time, the thickness of the LaAlO ₃ film can be freely changed according to the device application.

On the LaAlO ₃ film, a gate electrode made of segregated Al and Ni ₂ Si is formed. The configuration of the gate electrode is not limited to this, and a composition and material that provide a threshold voltage according to the device application can be freely selected.

Source / drain regions are formed so as to sandwich a channel region directly under the n-channel MOS transistor gate insulating film. Here, tensile strain due to the LaAlO ₃ film is applied to the channel portion. A gate sidewall made of SiN is formed around the gate insulating film and the gate electrode.

In the p-channel MOS transistor, a single atomic layer of SiO ₂ is formed as an interface layer on an n-type semiconductor layer, and a LaAlO ₃ film is further formed thereon. At this time, the film thicknesses of the SiO ₂ layer and the LaAlO ₃ film can be freely changed so as to be compatible with various devices.

Ni ₂ Si is formed as a gate electrode on the LaAlO ₃ film, and a gate insulating film made of SiO ₂ and LaAlO ₃ layer and a gate side wall insulating film made of SiN are formed around the gate electrode. Even in the p-channel MOS transistor, the configuration of the gate electrode is not limited to this, and the material can be freely selected according to the device application.

Further, an SiN film serving as a stressor is formed on the gate sidewall insulating film and the gate electrode so as to cover them. Source / drain regions are formed so as to sandwich the channel region immediately below the SiO ₂ interface layer. Here, the tensile strain caused by the LaAlO ₃ film due to SiO ₂ is relaxed in the channel region, and further, the compressive strain is applied by the deposition of the SiN film as a stressor.

In addition, when the stressor effect is great and the tensile strain when the LaAlO ₃ film is directly bonded can be canceled, the SiO ₂ layer at the interface may be omitted. According to the first embodiment, the optimum strain is applied to both n-channel and p-channel MOS transistors, so that the mobility can be greatly improved as compared with the case where there is no strain. .

  Next, the manufacturing process of the semiconductor device of the first embodiment will be described. First, as shown in FIG. 8, the p-type semiconductor layer 3 and the n-type semiconductor layer 5 are formed on the semiconductor substrate 1 by ion implantation or the like. Next, an element isolation layer 7 made of a silicon oxide layer is formed on the boundary surface between the p-type semiconductor layer 3 and the n-type semiconductor layer 5.

Subsequently, as shown in FIG. 9, for example, SiO ₂ and polycrystalline Si are deposited as the dummy gate insulating film 9 and the dummy gate electrode 11 on the p-type semiconductor layer 3 and the n-type semiconductor layer 5, respectively. Thereafter, as shown in FIG. 10, a dummy gate electrode is formed by processing the SiO ₂ layer 9 and the polycrystalline Si layer 11 using a known etching technique such as RIE.

  Next, n-type impurities and p-type impurities are ion-implanted into the nMOS transistor region and the pMOS transistor region, respectively, using the dummy gate electrode 11 as a mask by a known method, thereby forming diffusion layers 13 and 15 serving as source / drain. . Needless to say, when ions are implanted into one FET, the opposite FET is masked by a resist (not shown).

  Thereafter, a SiN layer is deposited on the entire surface by a known method, and etched by RIE, thereby forming a gate sidewall insulating film 17 as shown in FIG. Thereafter, n-type impurities and p-type impurities are ion-implanted into each of the n-channel MOS transistor region and the p-channel MOS transistor region using the dummy gate electrode 11 and the gate sidewall insulating film 17 as a mask, and heat treatment for activation is performed. Then, as shown in FIG. 13, source / drain regions 19 and 21 including shallow extension source / drain portions 13 and 15 are formed.

  The extension portions 13 and 15 may be formed by using an selective source epitaxial growth method and an elevated source / drain structure capable of suppressing the short channel effect in terms of device characteristics. Further, impurities may be introduced simultaneously with the formation of the elevated source / drain structure.

  Next, the gate electrode 1 is masked with a resist 23 by PEP (Photo Engraving Process). Next, a Ni layer 25 of about 10 nm is deposited on the entire surface by a known method such as sputtering. Thereafter, Ni and Si are reacted by performing a heat treatment at about 400 ° C., and then the unreacted Ni and the resist 23 on the gate electrode 11 are removed by a chemical solution or the like, so that the source / drain regions are formed as shown in FIG. A NiSi layer 27 is formed as a contact on the surfaces of 19 and 21. The source / drain region surface may be a metal silicide formed in a self-aligned manner by heat treatment, such as CoSi. The heat treatment conditions for silicidation can be changed as appropriate.

Thereafter, after forming an interlayer insulating film 29 made of SiO ₂ , the surface is planarized by a CMP (Chemical Mechanical Polishing) method or the like to expose the surface of the dummy gate electrode 11 as shown in FIG. After that, the dummy gate electrode 11 is selectively removed by CDE (Chemical Dry Etching) using an etching gas of CF ₄ , and then the dummy gate insulating film 9 is dissolved and removed by hydrofluoric acid. As shown in FIG. 2, a gate burying groove 31 is formed.

Next, the gate insulating film 33 is amorphous as a gate insulating layer by sputtering using LaAlO ₃ single crystal as a target at a substrate temperature of 600 ° C. and in vacuum (1 × 10 ⁻⁶ Pa). The LaAlO ₃ film is formed at the bottom of the gate embedding trench 31 with a thickness of about 3 nm without forming an interface layer as shown in FIG.

The film forming method is not limited to the sputtering method, and a CVD (Chemical Vapor Deposition) method, an MBE (molecular beam epitaxy) method, a laser ablation method, or the like may be used. Further, the ratio of La and Al can be appropriately changed as the composition of the gate insulating film 33. Further, as the gate insulating film 33, La ₂ O ₃ , LaSiO, LaHfO, or the like which is an insulating film containing La may be used.

Thereafter, Si having a thickness of about 50 nm is formed on the entire surface by, eg, CVD, followed by patterning this Si by PEP, and a mask made of Si on the n-channel MOS transistor region as shown in FIG. A material 35 is formed. Here, by performing heat treatment in oxygen at atmospheric pressure at 600 ° C., as shown in FIG. 20, only in the p-channel MOS transistor region, an SiO ₂ layer 37 serving as an interface layer is formed between the substrate and LaAlO _3. A thickness of 0.2 to 2 nm (about 1 to 10 atomic layers) is formed. The heat treatment conditions here and the thickness of the interface layer can be freely set according to the device application.

Next, the mask material 35 formed on the n-type MOS transistor region is removed. As long as the mask material 35 and the mask removing material that removes the mask material 35 are a combination that brings about the same effect, the materials are not limited. Thereafter, polycrystalline Si and Ni are deposited on the LaAlO ₃ film 33 in the trench for gate embedding, and heat treatment is performed to form a Ni ₂ Si layer 39 as shown in FIG.

Thereafter, the p-channel MOS transistor region is masked with a resist 41, and Al is ion-implanted from above the gate electrode 39 of the n-channel MOS transistor as shown in FIG. Segregation occurs at the interface of the film 33 to form a segregation layer 43. The Al uneven stack 43 is formed to adjust the work function of the gate electrode in the n-type MOS transistor. The combination of the ion implantation conditions and the subsequent heat treatment conditions can be arbitrarily set so that segregation of Al is possible. However, in order to segregate Al at the interface without diffusing in the LaAlO ₃ film, at least LaAlO ₃ The film needs to be amorphous. Further, an Al film may be deposited on the Ni ₂ Si layer 39 instead of ion implantation.

  Next, using a known PEP technique, as shown in FIG. 23, the interlayer insulating film 29 in the p-channel MOS transistor region is removed, and a resist mask 45 is formed on the n-channel MOS transistor region. Further, as a stressor for compressive strain in the p-channel MOS transistor region, a 100 nm SiN layer 47 is formed on the entire surface by CVD or the like. As the stressor, the material and the film thickness thereof are not limited as long as they apply compressive strain to the substrate. Thereafter, the resist 45 is lifted off to remove the SiN layer 47 on the n-channel MOS transistor region. Thereby, a CMOS transistor as shown in FIG. 24 is formed.

  According to the first embodiment described above, in the n-channel MOS transistor, the p-type semiconductor layer is formed by directly bonding the high dielectric constant gate insulating film 33 on the p-type semiconductor layer 3 without forming the interface layer. Tensile strain can be introduced into Si of 3. In addition, in a p-channel MOS transistor, a Si channel having a compressive strain can be easily formed using a known technique, so that a complementary MOS transistor having excellent mobility can be provided.

(Second Embodiment)
In the second embodiment, a MOS transistor having a Schottky source / drain made of silicide and a manufacturing process thereof will be described. In order to facilitate understanding, the same portions as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

FIG. 25 is a cross-sectional view showing a configuration of a semiconductor device (CMOS transistor) according to the second embodiment. A p-type semiconductor layer 3 and an n-type semiconductor layer 5 are formed on an Si substrate 1 via an element isolation layer 7 made of SiO ₂ . Note that a substrate having an SOI (Silicon On Insulator) structure may be used as the substrate. An n-channel MOS transistor is formed on the p-type semiconductor layer, and a p-channel MOS transistor is formed on the n-type semiconductor layer.

  The second embodiment differs from the first embodiment in that the source / drain layers have Schottky source drains 28 and 29 made of CoSi. The other parts are the same as those in the first embodiment, so that the description of the structure is omitted and the manufacturing method will be described.

First, as in FIG. 8 of the first embodiment, after forming an element isolation layer 7 made of a silicon oxide layer at the boundary between the p-type semiconductor layer 3 and the n-type semiconductor layer 5, as shown in FIG. A known method such as sputtering or sputtering is used to deposit an amorphous LaAlO ₃ film 9 as a gate insulating layer with a thickness of about 3 nm without forming an interface layer. Thereafter, a polycrystalline Si layer 11 is formed on the LaAlO ₃ film 9 by a CVD method or the like.

Thereafter, as shown in FIG. 27, the LaAlO ₃ film 9 and the polycrystalline Si layer 11 are processed using a known etching technique such as RIE to form a dummy gate electrode. Subsequently, a gate sidewall insulating film 18 made of SiN is formed by a CVD method or the like, and etched by a known RIE method or the like to thin the sidewall insulating film. Next, the dummy gate electrode is masked with a resist (not shown), and Co is deposited to a thickness of about 15 nm on the entire surface by a known method such as sputtering.

  Thereafter, a heat treatment process at 600 ° C. forms a CoSi layer 28 in the source / drain region as shown in FIG. Turn into. At this time, a metal that forms a silicide, such as Ni, may be used instead of Co.

  Next, after forming an interlayer insulating film 29 by a known method, as shown in FIG. 29, the polycrystalline Si 11 which is a dummy gate electrode is removed. The subsequent steps are the same as those in FIG. 18 and thereafter in the first embodiment.

  According to the second embodiment, as in the first embodiment, in the n-channel MOS transistor, the high dielectric constant gate insulating film 33 is directly bonded without forming an interface layer on the p-type semiconductor layer 3. Tensile strain can be introduced into Si of the p-type semiconductor layer 3. In addition, since it has a Schottky source / drain structure, a complementary MOS transistor with excellent performance in which parasitic resistance is suppressed can be provided.

  Also in the second embodiment, the semiconductor regions 3 and 5 can be made of SiGe (Ge composition of 10% or more and 20% or less) as in the first embodiment.

(Third embodiment)
In the third embodiment, a semiconductor device having a SiGe layer epitaxially grown in a source / drain region of a p-type MOS transistor as a stressor and a manufacturing process thereof will be described. In order to facilitate understanding, the same portions as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

FIG. 30 is a cross-sectional view showing a configuration of a semiconductor device (CMOS transistor) according to the third embodiment. A p-type semiconductor layer 3 and an n-type semiconductor layer 5 are formed on an Si substrate 1 via an element isolation layer 7 made of SiO ₂ . Note that a substrate having an SOI (Silicon On Insulator) structure may be used as the substrate. An n-channel MOS transistor is formed on the p-type semiconductor layer, and a p-channel MOS transistor is formed on the n-type semiconductor layer.

  The third embodiment is different from the first embodiment in that an SiGe layer epitaxially grown as a stressor is provided on the source / drain of a p-channel MOS transistor. The other parts are the same as those in the first embodiment, so that the description of the structure is omitted and the manufacturing method will be described.

  First, after processing the dummy gate electrode 11 and the gate insulating film 9 in the same manner as in FIGS. 9 and 10 of the first embodiment, the p-channel MOS transistor region is made into a resist (not shown) as in FIG. Then, n-type impurities are ion-implanted into the n-channel MOS transistor region using the dummy gate electrode 11 as a mask to form the source / drain diffusion layer 13 as an extension region.

  Next, after removing the resist in the p-channel MOS transistor region, as shown in FIG. 31, the n-channel MOS transistor is masked with a resist 14, and the source / drain regions of the p-channel MOS transistor are etched. It is desirable that the etching depth at this time be deeper than the impurity distribution by the subsequent ion implantation.

  Next, as shown in FIG. 32, SiGe containing Ge at an atomic ratio of 10% is epitaxially grown in the etching region. At this time, Ge needs to be 10% or more in atomic ratio in order to apply compressive strain to Si serving as a channel, and in order to make a defect amount that does not affect the transistor characteristics, the Ge amount is 20%. Must be:

  Next, ions are implanted into the p-channel MOS transistor region to form an extension region 15 of the p-channel MOS transistor as shown in FIG. Next, the resist 14 on the nMOS transistor is removed. The subsequent steps are the same as the steps after FIG. 12 in the first embodiment, but the SiN film that is a compressive strain stressor in the first embodiment may be omitted. If used together, stronger strain can be applied to the channel region of the p-channel MOS transistor.

  According to the third embodiment, as in the first embodiment, in the n-channel MOS transistor, the high dielectric constant gate insulating film 33 is directly bonded without forming an interface layer on the p-type semiconductor layer 3. A tensile strain can be introduced into Si of the p-type semiconductor layer 3. Further, since the p-channel MOS transistor region has the SiGe layer 22 as a stressor, compressive strain can be applied to the Si channel as in the first embodiment.

  As described above, the present invention has been described through the embodiments. However, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

It shows that the LaAlO ₃ film and the Si substrate are directly bonded. FIG. 2 is a diagram showing the relationship between the depth from the surface of the sample of FIG. 1 and the atomic concentration of the constituent elements, and showing that no interface layer is generated between the LaAlO ₃ film and the Si substrate. The figure which shows the relationship between He ion irradiation angle and a RBS yield, and shows that the tension | tensile_strength exists in a board | substrate. A diagram showing a relationship between the atomic concentration depth and configuration element from the surface of the sample for the case of performing the heat treatment in oxygen, shows that the interface layer is formed during the LaAlO ₃ film and the Si substrate. The figure which shows the relationship between He ion irradiation angle and RSB yield when an interface layer produces | generates, and a figure which shows that there is almost no distortion. The figure which shows the relationship between the depth from an interface, and the amount of tensile strain, and is a figure which shows the difference in the amount of tensile strain with the presence or absence of an interface layer. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. Sectional drawing for demonstrating the manufacturing process of the semiconductor device of 1st Embodiment. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. FIG. 21 is a cross-sectional view of the process following FIG. 20. FIG. 22 is a sectional view of a step following FIG. 21. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23. Sectional drawing of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 27 is a sectional view of a step following FIG. 26; FIG. 28 is a sectional view of a step following FIG. 27. FIG. 29 is a sectional view of a step following FIG. 28. Sectional drawing of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. FIG. 32 is a cross-sectional view of the process following FIG. 31. FIG. 33 is a sectional view of a step following FIG. 32.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... p-type semiconductor layer 5 ... n-type semiconductor layer 7 ... Element isolation layer 9 ... Gate insulating film 11 ... Gate electrode 13 ... Source-drain extension region 15 of n-channel MOS transistor ... p-channel MOS Transistor source / drain / extension regions 17, 18 ... sidewall insulating film 19 ... n-channel MOS transistor source / drain region 21 ... p-channel MOS transistor source / drain region 22 ... p-channel MOS transistor stressor region 23 ... resist mask 25 ... Ni layer 27 ... silicide layer 28 ... silicide layer (source / drain layer)
29 ... Interlayer insulating film 31 ... Groove 33 ... High dielectric constant gate insulating film 35 ... Silicon mask 37 ... Interface layer (silicon oxide film)
39 ... Ni silicide layers 41, 45 ... resist mask 43 ... segregation layer (Al layer)
47 ... SiN layer

Claims (10)

A semiconductor substrate;
A p-type first semiconductor region formed on the semiconductor substrate;
An n-type second semiconductor region formed on the semiconductor substrate so as to be insulated from the first semiconductor region;
An n-channel MOS transistor formed in the first semiconductor region;
A p-channel MOS transistor formed in the second semiconductor region;
The n-channel MOS transistor comprises:
A pair of first source / drain regions formed opposite to the first semiconductor region;
A first gate insulating film formed of an amorphous insulating film containing at least La and formed in direct contact with the surface of the first semiconductor region sandwiched between the first source / drain regions; ,
A first gate electrode formed on the first gate insulating film;
And the P-channel MOS transistor comprises:
A pair of second source / drain regions formed opposite to the second semiconductor region;
A second gate insulating film including a silicon oxide film and the amorphous insulating film formed thereon on the surface of the second semiconductor region sandwiched between the second source / drain regions;
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising: A semiconductor substrate;
A p-type first semiconductor region formed on the semiconductor substrate;
An n-type second semiconductor region formed on the semiconductor substrate so as to be insulated from the first semiconductor region;
An n-channel MOS transistor formed in the first semiconductor region;
A p-channel MOS transistor formed in the second semiconductor region;
The n-channel MOS transistor comprises:
A pair of first source / drain regions formed opposite to the first semiconductor region;
A first gate insulating film formed of an amorphous insulating film containing at least La and formed in direct contact with the surface of the first semiconductor region sandwiched between the first source / drain regions; ,
A first gate electrode formed on the first gate insulating film;
The p-channel MOS transistor comprises:
A pair of second source / drain regions formed opposite to the second semiconductor region;
A second gate insulating film including the amorphous insulating film directly formed on the surface of the second semiconductor region sandwiched between the second source / drain regions;
A second gate electrode formed on the second gate insulating film;
A stressor insulating film formed on an upper surface and a side surface of the second gate electrode and applying compressive stress to a surface of the second semiconductor substrate under the second gate insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 2, wherein the stressor film includes a silicon nitride film.   The first semiconductor region and the second semiconductor region are formed of either Si or SiGe having a Ge atomic ratio of 10% or more and 20% or less. A semiconductor device according to 1. A semiconductor substrate;
A p-type first Si semiconductor region formed on the semiconductor substrate;
An n-type second Si semiconductor region formed on the semiconductor substrate so as to be insulated from the first semiconductor region;
An n-channel MOS transistor formed in the first Si semiconductor region;
A p-channel MOS transistor formed in the second Si semiconductor region;
The n-channel MOS transistor comprises:
A pair of first source / drain regions formed opposite to the first Si semiconductor region;
A first gate insulating film formed of an amorphous insulating film containing at least La and formed in direct contact with the surface of the first Si semiconductor region sandwiched between the first source / drain regions When,
A first gate electrode formed on the first gate insulating film;
The p-channel MOS transistor comprises:
A pair of second source / drain regions formed opposite to the second Si semiconductor region and made of SiGe containing Ge at a concentration of 10% to 20% by atomic ratio;
A second gate insulating film including a silicon oxide film and the amorphous insulating film formed thereon on the surface of the second Si semiconductor region sandwiched between the second source / drain regions; ,
A second gate electrode formed on the second gate insulating film;
A semiconductor device comprising: 6. The semiconductor device according to claim 1, wherein the amorphous insulating film is a LaAlO ₃ film.   The first semiconductor region is made of Si, and the first semiconductor region within at least 3 nm from the interface with the first gate insulating film contains a tensile strain of 0.5% or more. The semiconductor device according to claim 1, wherein: The first semiconductor region is formed of Si, and the first semiconductor region within at least 1 nm from the interface with the first gate insulating film contains a tensile strain of 0.8% or more,
7. The semiconductor device according to claim 1, wherein the first semiconductor region deeper than at least 3 nm from the interface with the first gate insulating film contains a tensile strain of less than 0.5%. . The first gate electrode includes Ni silicide, the amorphous insulating film includes a LaAlO ₃ film, and an Al uneven lamination is further provided between the first gate electrode and the amorphous insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The p-channel MOS transistor further includes a stressor insulating film that is formed on an upper surface and a side surface of the second gate electrode and applies compressive stress to the second semiconductor substrate below the second gate insulating film. The semiconductor device according to claim 1, wherein:

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