JP2008227292A - Ion implantation mask, ion implantation method and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ion implantation mask which can suppress variations of a characteristic of a semiconductor device manufactured by utilizing an ion implantation, and can suppress reduction of an yield, an ion implantation method, and a manufacturing method of the semiconductor device. <P>SOLUTION: The ion implantation mask is provided on a semiconductor for precluding the ion implantation onto the semiconductor, and the ion implantation mask contains: a first ion implantation mask layer, a second ion implantation mask layer which is harder to be etched than the first ion implantation mask layer, and a third ion implantation mask layer which is easier to be etched than the second ion implantation mask layer in this order from the semiconductor side. Further, the ion implantation method using the ion implantation mask and the manufacturing method of the semiconductor device are provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an ion implantation mask, an ion implantation method, and a method for manufacturing a semiconductor device, and in particular, can suppress variation in characteristics of a semiconductor device manufactured by using ion implantation and also suppress a decrease in yield. The present invention relates to an ion implantation mask, an ion implantation method, and a method for manufacturing a semiconductor device.

  MOSFETs (Metal Oxide Semiconductor Field Effect Transistors; hereinafter referred to as “SiC-MOSFETs”) using SiC (silicon carbide), which is a kind of semiconductor device, are roughly classified into selective ion implantation and activation annealing. It is fabricated through the steps of gate oxide film formation and electrode formation.

  Hereinafter, an example of a conventional method for manufacturing a SiC-MOSFET will be described with reference to the schematic cross-sectional views of FIGS.

  First, as shown in FIG. 22, ion implantation mask 203 is formed on the entire surface of n-type SiC substrate 202.

  Next, as shown in FIG. 23, a resist 204 having a predetermined opening 205 is formed on the ion implantation mask 203 by using a photolithography technique.

  Subsequently, as shown in FIG. 24, a portion of the ion implantation mask 203 located below the opening 205 is removed by etching, and a part of the surface of the SiC substrate 202 is exposed.

  Thereafter, as shown in FIG. 25, the resist 204 is removed, and ions of an n-type dopant such as phosphorus are ion-implanted into the exposed surface of the SiC substrate 202, whereby an n-type dopant implanted region 206 is implanted into the surface of the SiC substrate 202. Form.

  Next, as shown in FIG. 26, all of ion implantation mask 203 is removed from the surface of SiC substrate 202. Thereafter, as shown in FIG. 27, ion implantation mask 203 is formed again on the entire surface of SiC substrate 202.

  Then, as shown in FIG. 28, a resist 204 is partially formed on the surface of the ion implantation mask 203 by using a photolithography technique. Here, the formation position of the resist 204 may deviate from the set position depending on the accuracy of the photolithography apparatus.

  Next, as shown in FIG. 29, a portion of the surface of SiC substrate 202 is exposed by removing the portion of ion implantation mask 203 where resist 204 is not formed by etching.

  Subsequently, as shown in FIG. 30, p-type dopant implantation region 207 is formed on the surface of SiC substrate 202 by ion-implanting ions of a p-type dopant such as aluminum into the exposed surface of SiC substrate 202.

  Thereafter, the ion implantation mask 203 and the resist 204 are removed, and activation annealing is performed to recover the crystallinity of the wafer after the ion implantation mask 203 and the resist 204 are removed.

Then, as shown in FIG. 31, gate oxide film 208 and source electrode 209 are formed on the surface of SiC substrate 202, and gate electrode 210 is formed on the surface of gate oxide film 208. Then, the drain electrode 211 is formed on the back surface of the SiC substrate 202, and then the wafer is divided into chips to complete the SiC-MOSFET.
Edited by Hiroyuki Matsunami, "Semiconductor SiC Technology and Applications", Nikkan Kogyo Shimbun

  Since SiC has a small dopant diffusion coefficient, it is necessary to introduce an n-type dopant and a p-type dopant not by a diffusion method but by an ion implantation method.

  However, as described above, the formation position of the resist serving as an ion implantation mask for ion implantation of the n-type dopant and the p-type dopant varies depending on the accuracy of the photolithography apparatus. There is a problem in that the relative positional relationship varies, and the gate length of the SiC-MOSFET varies, resulting in a variation in the characteristics of the SiC-MOSFET.

  Therefore, in order to solve such a problem, the following method is considered. First, as shown in FIG. 25, after the n-type dopant implantation region 206 is formed, the width of the ion implantation mask 203 is reduced by dry etching without removing the ion implantation mask 203, thereby forming the surface of the SiC substrate 202. Enlarge the exposed area. Then, p-type dopant implantation region 207 is formed on the surface of SiC substrate 202 by ion-implanting p-type dopant ions into the expanded exposed region of the surface of SiC substrate 202.

  According to this method, it is possible to suppress the variation in the relative positional relationship between the n-type dopant implantation region and the p-type dopant implantation region due to the variation in the resist formation position. Variation in characteristics of the SiC-MOSFET due to variation can be suppressed.

  However, in the above method, the step of reducing the width of the ion implantation mask 203 is performed by dry etching, but at this time, the surface of the ion implantation mask 203 is roughened. When the surface of the ion implantation mask 203 is roughened, a portion where the thickness of the ion implantation mask 203 is locally thinned is generated, and ions are implanted from the thinned portion during ion implantation of the p-type dopant. There is a risk of injection through the mask 203.

  Further, in the step of reducing the width of the ion implantation mask 203, the ion implantation mask 203 is etched not only in the width direction but also in the thickness direction, so that not only the width direction but also the etching in the thickness direction is controlled. I have to do it. This makes it difficult to accurately control the amount of decrease in the width direction of the ion implantation mask 203, and it is assumed that the amount of decrease varies.

  Therefore, even in the above method, it is considered that it is not sufficient to suppress variations in characteristics of semiconductor devices such as SiC-MOSFETs due to variations in the amount of reduction in the width direction of the ion implantation mask 203 and the ion implantation mask 203. There is also concern about the decline.

  Accordingly, an object of the present invention is to provide an ion implantation mask, an ion implantation method, and a semiconductor device that can suppress variation in characteristics of a semiconductor device manufactured by using ion implantation and also suppress a decrease in yield. It is to provide a manufacturing method.

  The present invention is an ion implantation mask provided on a semiconductor to prevent ion implantation into a semiconductor, and includes a first ion implantation mask layer and a second layer that is less easily etched than the first ion implantation mask layer. The ion implantation mask includes an ion implantation mask layer and a third ion implantation mask layer that is more easily etched than the second ion implantation mask layer in this order from the semiconductor side. When a semiconductor device is manufactured using the ion implantation mask of the present invention, variation in characteristics of the semiconductor device can be suppressed and a decrease in yield can also be suppressed.

  Here, in the ion implantation mask of the present invention, as the second ion implantation mask layer, a layer that is less likely to be etched by the fluorine-containing gas than each of the first ion implantation mask layer and the third ion implantation mask layer is used. be able to. In this case, the first ion implantation mask layer tends to be easily etched in the width direction during the second etching described later.

In the present invention, the fluorine-containing gas means a fluorine compound gas.
In the ion implantation mask of the present invention, at least one of the first ion implantation mask layer and the third ion implantation mask layer may be made of tungsten or silicon. In this case, the first ion implantation mask layer and the third ion implantation mask layer are easily etched by a fluorine-containing gas such as SF ₆ (sulfur hexafluoride) gas.

In the ion implantation mask of the present invention, the second ion implantation mask layer may be made of titanium or aluminum. In this case, the second ion implantation mask layer is hardly etched by a fluorine-containing gas such as SF ₆ gas.

  In the ion implantation mask of the present invention, it is preferable that the etching selectivity of the third ion implantation mask layer with respect to the second ion implantation mask layer is 2 or more. In this case, even if the third ion implantation mask layer is completely etched in the second etching described later, the first ion implantation mask layer tends to be protected.

  In the ion implantation mask of the present invention, it is preferable that the etching selectivity of the first ion implantation mask layer with respect to the second ion implantation mask layer is 2 or more. In this case, the directivity of etching in the width direction of the first ion implantation mask layer tends to be improved during the second etching described later.

  In the ion implantation mask of the present invention, the thickness of the first ion implantation mask layer is preferably 100 nm or more and 30000 nm or less. In this case, the ion implantation tends to be effectively prevented during the second ion implantation described later.

  In the ion implantation mask of the present invention, the thickness of the second ion implantation mask layer is preferably 5 nm or more and 100 nm or less. In this case, the second ion implantation mask layer tends to be easily removed by etching during the first etching described later, and the first ion implantation mask layer is removed during the second etching described later. It tends to be able to effectively prevent etching in the thickness direction.

  In the ion implantation mask of the present invention, the thickness of the third ion implantation mask layer is preferably 50 nm or more and 30000 nm or less. In this case, the ion implantation tends to be effectively prevented during the first ion implantation described later.

  Further, the ion implantation mask of the present invention includes a fourth ion implantation mask layer on the semiconductor side of the first ion implantation mask layer, and the fourth ion implantation mask layer is more than the first ion implantation mask layer. It is preferable that etching is difficult. In this case, the damage to the surface of the semiconductor tends to be reduced.

  In the ion implantation mask of the present invention, it is preferable that the fourth ion implantation mask layer is less likely to be etched by the fluorine-containing gas than each of the first ion implantation mask layer and the third ion implantation mask layer. In this case, the tendency to reduce damage to the surface of the semiconductor is further increased.

In the ion implantation mask of the present invention, the fourth ion implantation mask layer may be made of titanium or aluminum. In this case, the fourth ion implantation mask layer is hardly etched by a fluorine-containing gas such as SF ₆ gas.

  In the ion implantation mask of the present invention, it is preferable that the thickness of the fourth ion implantation mask layer is larger than the thickness of the second ion implantation mask layer. In this case, the fourth ion implantation mask layer tends not to be removed during the first etching described later and the second etching described later.

  In the ion implantation mask of the present invention, when the thickness of the fourth ion implantation mask layer is thicker than that of the second ion implantation mask layer, the thickness of the fourth ion implantation mask layer is 30 nm or more and 300 nm or less. It is preferable that In this case, ions tend to be implanted at an appropriate depth from the surface of the semiconductor during the first ion implantation described later.

  In the ion implantation mask of the present invention, the semiconductor is preferably silicon carbide. In this case, a semiconductor device having a high breakdown voltage, low loss, and excellent heat resistance tends to be manufactured.

  The present invention is also an ion implantation method in which an ion implantation is performed on a semiconductor after the ion implantation mask of the present invention is formed on the surface of the semiconductor. When a semiconductor device is manufactured using the ion implantation method of the present invention, variation in characteristics of the semiconductor device can be suppressed and a decrease in yield can also be suppressed.

  Furthermore, the present invention provides a first step of forming the ion implantation mask of the present invention on a part of a surface of a semiconductor, and at least a part of a semiconductor region corresponding to a region other than a region where the ion implantation mask is formed. A second step of implanting ions of the first dopant to form a first dopant implantation region, a third step of removing a portion of the ion implantation mask in the width direction after the formation of the first dopant implantation region, and ion implantation And a fourth step of forming a second dopant implantation region by implanting ions of the second dopant into at least a part of the semiconductor region corresponding to the region removed in the width direction of the mask. It is. According to the method for manufacturing a semiconductor device of the present invention, it is possible to suppress variations in characteristics of the semiconductor device and to suppress a decrease in yield.

  Here, the semiconductor device manufacturing method of the present invention preferably includes a step of removing the second ion implantation mask layer and the third ion implantation mask layer between the third step and the fourth step. In this case, the second ion implantation described later tends to be easy.

  According to the present invention, an ion implantation mask, an ion implantation method, and a method for manufacturing a semiconductor device that can suppress variation in characteristics of a semiconductor device manufactured by using ion implantation and also suppress a decrease in yield. Can be provided.

  Hereinafter, an example of a method for manufacturing a semiconductor device using the ion implantation mask of the present invention will be described. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

  First, as shown in the schematic cross-sectional view of FIG. 1, on the surface of the n-type SiC substrate 101, a fourth ion implantation mask layer 102 made of titanium, a first ion implantation mask layer 103 made of tungsten, and titanium. A second ion implantation mask layer 104 made of and a third ion implantation mask layer 105 made of tungsten are stacked in this order from the SiC substrate 101 side.

  Here, as a method of stacking the fourth ion implantation mask layer 102, the first ion implantation mask layer 103, the second ion implantation mask layer 104, and the third ion implantation mask layer 105, for example, conventionally known sputtering is used. The law etc. can be used.

  Next, as shown in the schematic cross-sectional view of FIG. 2, a resist 106 having an opening 112 is formed on the surface of the third ion implantation mask layer 105 using, for example, a photolithography technique or the like.

  Subsequently, as shown in the schematic cross-sectional view of FIG. 3, the third ion implantation mask layer 105, the second ion implantation mask layer 104, and the first ion implantation are performed from the opening 112 toward the SiC substrate 101 side. The surface of the fourth ion implantation mask layer 102 is exposed by removing the mask layer 103 by etching (first etching).

  Thereafter, as shown in the schematic cross-sectional view of FIG. 4, by removing the resist 106, a fourth ion implantation mask layer 102, a first ion implantation mask layer 103, a second ion is formed on the surface of the SiC substrate 101. The ion implantation mask 107 of the present invention is formed by laminating the ion implantation mask layer 104 and the third ion implantation mask layer 105 in this order from the SiC substrate 101 side.

  Here, the thickness of the first ion implantation mask layer 103 is preferably 100 nm or more and 30000 nm or less. When the thickness of the first ion implantation mask layer 103 is not less than 100 nm and not more than 30000 nm, ion implantation at the time of second ion implantation described later tends to be effectively prevented.

  The thickness of the second ion implantation mask layer 104 is preferably 5 nm to 100 nm. When the thickness of the second ion implantation mask layer 104 is not less than 5 nm and not more than 100 nm, the second ion implantation mask layer 104 tends to be easily removed by etching during the first etching. In the second etching which will be described later, the first ion implantation mask layer 103 tends to be effectively prevented from being etched in the thickness direction.

  The thickness of the third ion implantation mask layer 105 is preferably 50 nm or more and 30000 nm or less. When the thickness of the third ion implantation mask layer 105 is not less than 50 nm and not more than 30000 nm, ion implantation during the first ion implantation described later tends to be effectively prevented.

  The fourth ion implantation mask layer 102 is preferably thicker than the second ion implantation mask layer 104. When the thickness of the fourth ion implantation mask layer 102 is thicker than the thickness of the second ion implantation mask layer 104, the fourth ion implantation mask layer 102 is etched during the first etching described above and in the first to be described later. This is preferable in that it tends not to be removed in each of the second etching.

  When the thickness of the fourth ion implantation mask layer 102 is larger than the thickness of the second ion implantation mask layer 104, the thickness of the fourth ion implantation mask layer 102 is 30 nm or more and 300 nm or less. Is preferred. When the thickness of the fourth ion implantation mask layer 102 is larger than the thickness of the second ion implantation mask layer 104 and the thickness of the fourth ion implantation mask layer 102 is less than 30 nm, the first time described above. In the step of removing the fourth ion implantation mask layer 102 before the second ion implantation described later, when it is thicker than 300 nm, it is easily removed at the time of the etching and the second etching described later. The fourth ion implantation mask layer 102 may be difficult to remove.

  Then, as shown in the schematic cross-sectional view of FIG. 5, ions 108 of n-type dopant such as phosphorus are implanted from above the third ion implantation mask layer 105 (first ion implantation). Thereby, n-type dopant implantation region 109 is formed on the surface of SiC substrate 101.

  Here, the n-type dopant implantation region 109 is a region of the SiC substrate 101 corresponding to a region other than the region where the ion implantation mask 107 is formed (that is, below the region other than the region where the ion implantation mask 107 is formed). At least part of the region of the SiC substrate 101 located on the substrate.

Subsequently, as shown in the schematic cross-sectional view of FIG. 6, the first ion implantation mask layer 103 is removed in the width direction by etching using a fluorine-containing gas such as SF ₆ gas, for example, so that the first ion implantation is performed. The width of the mask layer 103 is reduced (second etching).

In the present invention, the upper surface of the first ion implantation mask layer 103 made of etched easily tungsten with fluorine-containing gas such as SF ₆ gas is made of the etched hard titanium by fluorine-containing gas such as SF ₆ gas The second ion implantation mask layer 104 is covered.

  Therefore, at the time of the second etching, the first ion implantation mask layer 103 whose upper surface is covered with the second ion implantation mask layer 104 tends to be etched in the width direction. In the present invention, the controllability is improved and the width of the first ion implantation mask layer 103 in the width direction is improved. Variations in the amount of decrease can be suppressed.

  Note that since the upper surface of the third ion implantation mask layer 105 is not covered with the second ion implantation mask layer 104, etching in the thickness direction and the width direction proceeds, and the third ion implantation mask layer 105 Both the thickness and width of 105 will be reduced.

  Further, the etching selectivity of the first ion implantation mask layer 103 with respect to the second ion implantation mask layer 104 ((etching speed of the first ion implantation mask layer 103) / (etching speed of the second ion implantation mask layer 104). )) Is preferably 2 or more, more preferably 5 or more, and even more preferably 10 or more. When the etching selection ratio of the first ion implantation mask layer 103 to the second ion implantation mask layer 104 is preferably 2 or more, more preferably 5 or more, and further preferably 10 or more, the first ion implantation mask. Etching directivity in the width direction of the layer tends to be improved.

  Further, the etching selectivity of the third ion implantation mask layer 105 with respect to the second ion implantation mask layer 104 ((etching rate of the third ion implantation mask layer 105) / (etching rate of the second ion implantation mask layer 104). )) Is preferably 2 or more, more preferably 5 or more, and even more preferably 10 or more. When the etching selection ratio of the third ion implantation mask layer 105 to the second ion implantation mask layer 104 is preferably 2 or more, more preferably 5 or more, and even more preferably 10 or more, Even if the third ion implantation mask layer is completely etched, the first ion implantation mask layer tends to be protected.

Note that as the etching rate used for the above calculation of the etching selection ratio, each of the first ion implantation mask layer 103, the second ion implantation mask layer 104, and the third ion implantation mask layer 105 is subjected to a fluorine-containing gas ( For example, the etching rate in the thickness direction when etching is performed under the same conditions using SF ₆ gas) is used.

  Thereafter, as shown in the schematic cross-sectional view of FIG. 7, the exposed portions of the second ion implantation mask layer 104 and the fourth ion implantation mask layer 102 made of titanium above the first ion implantation mask layer 103 are etched. (Third etching). Here, along with the removal of the second ion implantation mask layer 104, the third ion implantation mask layer 105 laminated on the second ion implantation mask layer 104 is also removed.

  The exposed portions of the second ion implantation mask layer 104 and the fourth ion implantation mask layer 102 can be removed by etching, for example, by wet etching using a conventionally known buffered hydrofluoric acid or the like. Buffered hydrofluoric acid can be produced, for example, by mixing hydrofluoric acid and ammonium fluoride.

  Subsequently, as shown in the schematic cross-sectional view of FIG. 8, ions 110 of a p-type dopant such as boron are implanted from above the first ion implantation mask layer 103 (second ion implantation). Thereby, p-type dopant implantation region 111 is formed on the surface of SiC substrate 101.

  Here, the p-type dopant implantation region 111 is a region of the SiC substrate 101 corresponding to a region where the first ion implantation mask layer 103 of the ion implantation mask 107 is removed in the width direction (that is, the first ion implantation mask 107 has a first region). The ion implantation mask layer 103 is formed on at least a part of the region of the SiC substrate 101 located below the region removed in the width direction.

  Here, in the present invention, since the upper surface of the first ion implantation mask layer 103 was covered with the second ion implantation mask layer 104 during the second etching, the second ion implantation was performed. The upper surface of the first ion implantation mask layer 103 after the removal of the mask layer 104 is hardly roughened, and the etching in the thickness direction of the first ion implantation mask layer 103 is not performed.

  Therefore, in the present invention, variation in the thickness of the first ion implantation mask layer 103 that functions as an ion implantation mask for the ions 110 of the p-type dopant is reduced, and the thickness of the first ion implantation mask layer 103 is locally increased. Therefore, it is possible to effectively prevent the penetration of ions.

  Thus, when the ion implantation mask of the present invention is used, variation in characteristics of a semiconductor device manufactured using ion implantation can be suppressed, and the variation in characteristics of the semiconductor device caused by variation in characteristics of the semiconductor device can be suppressed. A decrease in yield can also be suppressed.

  Next, as shown in the schematic cross-sectional view of FIG. 9, the fourth ion implantation mask layer 102 remaining on the surface of the SiC substrate 101 is removed by etching (fourth etching). Here, along with the removal of the fourth ion implantation mask layer 102, the first ion implantation mask layer 103 stacked on the fourth ion implantation mask layer 102 is also removed.

  The removal of the fourth ion implantation mask layer 102 can be performed, for example, by wet etching using a conventionally known buffered hydrofluoric acid or the like.

  Thereafter, activation annealing for recovering the crystallinity of the wafer after the removal of the fourth ion implantation mask layer 102 is performed. Then, as shown in the schematic cross-sectional view of FIG. 10, a gate oxide film 113 is formed on the surface of the p-type dopant implantation region 111, and a gate electrode 114 is formed on the gate oxide film 113. Further, source electrode 115 is formed on the surface of n-type dopant implantation region 109, and drain electrode 116 is formed on the back surface of SiC substrate 101. Then, by dividing the wafer into chips, a SiC-MOSFET which is an example of a semiconductor device is completed.

  As described above, the semiconductor device such as the SiC-MOSFET manufactured as described above has reduced variations in characteristics, and can suppress a decrease in yield due to the variations in characteristics.

  In the above, SiC is used as the semiconductor on which the ion implantation mask of the present invention is formed, but the present invention is not limited to this. However, it is preferable to use SiC as the semiconductor on which the ion implantation mask of the present invention is formed. In this case, a semiconductor device having a high breakdown voltage, low loss, and excellent heat resistance tends to be manufactured.

In the above description, tungsten is used as the material of the first ion implantation mask layer 103 and the material of the third ion implantation mask layer 105, but the present invention is not limited to this. For example, SF ₆ Tungsten, silicon, or the like that is easily etched with a fluorine-containing gas such as a gas can be used. Note that the material of the first ion implantation mask layer 103 and the material of the third ion implantation mask layer 105 may be the same or different.

In the above, titanium is used as the material of the second ion implantation mask layer 104 and the material of the fourth ion implantation mask layer 102, but the present invention is not limited to this. For example, SF ₆ Titanium or aluminum that is difficult to be etched with a fluorine-containing gas such as a gas can be used. Note that the material of the second ion implantation mask layer 104 and the material of the fourth ion implantation mask layer 102 may be the same or different.

  In the above, the fourth ion implantation mask layer 102, the first ion implantation mask layer 103, the second ion implantation mask layer 104, and the third ion implantation mask layer 105 are sequentially stacked. Although an ion implantation mask is used, in the present invention, an ion implantation mask having a three-layer structure that is not formed for the fourth ion implantation mask layer 102 may be used. In the present invention, in addition to the above four layers (fourth ion implantation mask layer 102, first ion implantation mask layer 103, second ion implantation mask layer 104, and third ion implantation mask layer 105). Alternatively, an ion implantation mask having a structure of five or more layers including one or more other layers may be used.

Example 1
First, as shown in FIG. 1, on the surface of the SiC substrate 101, a fourth ion implantation mask layer 102 made of titanium having a thickness of 100 nm, a first ion implantation mask layer 103 made of tungsten having a thickness of 1600 nm, and titanium. A second ion implantation mask layer 104 made of 20 nm thick and a third ion implantation mask layer 105 made of tungsten having a thickness of 1600 nm are sequentially stacked by sputtering.

  Next, after a resist 106 is formed on the entire surface of the third ion implantation mask layer 105, a part of the resist 106 is removed by using a photolithography technique, thereby opening an opening as shown in FIG. A portion 112 is formed, and the surface of the third ion implantation mask layer 105 is exposed from the opening 112.

  Next, as shown in FIG. 3, the third ion implantation mask layer 105, the second ion implantation mask layer 104, and the first ion implantation mask layer 103 are removed from the opening 112 downward by dry etching. Then, the surface of the fourth ion implantation mask layer 102 is exposed.

  Next, as shown in FIG. 4, by removing all the resist 106, the fourth ion implantation mask layer 102, the first ion implantation mask layer 103, the second ion implantation mask layer 104, and the third ions are removed. An ion implantation mask 107 in which the implantation mask layer 105 is laminated in this order is formed. FIG. 11 shows an SEM (Scanning Electron Microscope) photograph of the ion implantation mask 107 at this stage as seen from obliquely above.

  Next, as shown in FIG. 5, an n-type dopant implantation region 109 is formed on the surface of the SiC substrate 101 by implanting phosphorus ions 108 as an n-type dopant from above the third ion implantation mask layer 105. . Here, n-type dopant implantation region 109 is formed in at least a part of the region of SiC substrate 101 corresponding to a region other than the region where ion implantation mask 107 is formed.

Subsequently, as shown in FIG. 6, the width of the first ion implantation mask layer 103 is reduced by removing the first ion implantation mask layer 103 in the width direction by dry etching using SF ₆ gas. . FIG. 12 shows an SEM photograph of the ion implantation mask 107 at this stage as viewed from obliquely above.

  After that, as shown in FIG. 7, the second ion implantation mask layer 104 is removed by wet etching using buffered hydrofluoric acid, and the third ion implantation mask layer 105 is also removed together with the second ion implantation mask layer 104. To do.

  Next, as shown in FIG. 8, a p-type dopant implantation region 111 is formed on the surface of the SiC substrate 101 by implanting boron ions 110 from above the first ion implantation mask layer 103. Here, the p-type dopant implantation region 111 is formed in at least a part of the region of the SiC substrate 101 corresponding to the region where the first ion implantation mask layer 103 of the ion implantation mask 107 is removed in the width direction.

  Next, as shown in FIG. 9, the fourth ion implantation mask layer 102 is removed by wet etching using buffered hydrofluoric acid, and the first ion implantation mask layer 103 is also formed together with the fourth ion implantation mask layer 102. Remove.

  Thereafter, activation annealing for recovering the crystallinity of the wafer after the removal of the fourth ion implantation mask layer 102 is performed. Then, as shown in FIG. 10, a gate oxide film 113 is formed on the surface of the p-type dopant implantation region 111, and a gate electrode 114 is formed on the gate oxide film 113. Further, source electrode 115 is formed on the surface of n-type dopant implantation region 109, and drain electrode 116 is formed on the back surface of SiC substrate 101. Then, the SiC-MOSFET is completed by dividing the wafer into chips.

  As described above, the SiC-MOSFET manufactured in this way has reduced variations in characteristics, and can suppress a decrease in yield due to the variations in characteristics.

(Comparative Example 1)
First, as shown in the schematic cross-sectional view of FIG. 13, a titanium layer 302 having a thickness of 100 nm and a tungsten layer 303 having a thickness of 3000 nm are sequentially stacked on the surface of the SiC substrate 301 by a sputtering method.

  Next, after a resist 304 is formed on the entire surface of the tungsten layer 303, a part of the resist 304 is removed by using a photolithography technique, thereby opening an opening as shown in the schematic cross-sectional view of FIG. A portion 309 is formed, and the surface of the tungsten layer 303 is exposed from the opening 309.

  Next, as shown in the schematic cross-sectional view of FIG. 15, the surface of the titanium layer 302 is exposed by removing the tungsten layer 303 by dry etching downward from the opening 309.

  Next, as shown in the schematic cross-sectional view of FIG. 16, by removing all the resist 304, an ion implantation mask 310 including a titanium layer 302 and a tungsten layer 303 is formed. FIG. 17 shows an SEM photograph of the ion implantation mask 310 at this stage as viewed from obliquely above.

  Next, as shown in the schematic cross-sectional view of FIG. 18, by implanting phosphorus ions 305 that are n-type dopants from above the tungsten layer 303, an n-type dopant implantation region 306 is formed on the surface of the SiC substrate 301. .

Subsequently, as shown in the schematic cross-sectional view of FIG. 19, the width of the tungsten layer 303 is reduced by removing the tungsten layer 303 in the width direction by dry etching using SF ₆ gas. FIG. 20 shows an SEM photograph of the ion implantation mask 310 at this stage as viewed from obliquely above. As shown in FIG. 20, the surface of the tungsten layer 303 above the ion implantation mask 310 is rough, and it can be seen that the thickness of the tungsten layer 303 varies.

  Next, as shown in the schematic cross-sectional view of FIG. 21, a p-type dopant implantation region 308 is formed on the surface of the SiC substrate 301 by implanting boron ions 307 from above the tungsten layer 303.

  Here, as described above, since the thickness of the tungsten layer 303 varies, the tungsten layer 303 has a portion where the thickness is locally reduced. The portion penetrates through the tungsten layer 303 from that portion and is implanted into the region of the SiC substrate 301 below the tungsten layer 303.

  Therefore, in Comparative Example 1, boron ions 307 are implanted into a region of SiC substrate 301 where boron ions 307 should not be implanted. Thereafter, the SiC-MOSFET is manufactured in the same manner as in the first embodiment.

  In the first comparative example, boron ions 307 are implanted into various portions of the SiC substrate 301 due to variations in the thickness of the tungsten layer 303. Therefore, SiC-MOSFETs having various characteristics are extracted from one wafer. And since SiC-MOSFET with a low characteristic is discarded as a defective article, the yield of SiC-MOSFET will also fall.

  Therefore, as is clear from comparison between Example 1 and Comparative Example 1, when the SiC-MOSFET is manufactured using the ion implantation mask according to the present invention, variation in characteristics of the SiC-MOSFET is reduced, It can be seen that a decrease in yield due to characteristic variation can also be suppressed.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the ion implantation mask, the ion implantation method, and the semiconductor device manufacturing method of the present invention, it is possible to suppress variation in characteristics of a semiconductor device manufactured using ion implantation, and to suppress a decrease in yield. it can.

  Therefore, the present invention can be suitably used for manufacturing a semiconductor device such as a SiC-MOSFET.

It is typical sectional drawing for demonstrating a part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing for illustrating another part of manufacturing process of an example of the method of manufacturing a semiconductor device using the ion implantation mask of this invention. It is typical sectional drawing of SiC-MOSFET of this invention. It is the SEM photograph which looked at the ion implantation mask before the 1st ion implantation of the example of the method of manufacturing a semiconductor device using the ion implantation mask of the present invention from the slanting upper part. It is the SEM photograph which looked at the ion implantation mask after the 2nd etching of an example of the method of manufacturing a semiconductor device using the ion implantation mask of the present invention from the slanting upper part. It is typical sectional drawing for demonstrating a part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for demonstrating another part of manufacturing process of the manufacturing method of SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is the SEM photograph which looked at the ion implantation mask before the 1st ion implantation in the manufacturing method of SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET from diagonally upward. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is the SEM photograph which looked at the ion implantation mask after the 2nd etching in the manufacturing method of SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET from diagonally upward. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the SiC-MOSFET which improved the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating a part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing for illustrating another part of manufacturing process of the manufacturing method of the conventional SiC-MOSFET. It is typical sectional drawing of the conventional SiC-MOSFET.

Explanation of symbols

  101, 202, 301 SiC substrate, 102 4th ion implantation mask layer, 103 1st ion implantation mask layer, 104 2nd ion implantation mask layer, 105 3rd ion implantation mask layer, 106, 204, 304 resist 107, 203, 310 ion implantation mask, 108, 110, 305, 307 ions, 109, 206, 306 n-type dopant implantation region, 111, 207, 308 p-type dopant implantation region, 112, 205, 309 opening, 113 , 208 Gate oxide film, 114, 210 Gate electrode, 115, 209 Source electrode, 116, 211 Drain electrode, 302 Titanium layer, 303 Tungsten layer.

Claims (18)

An ion implantation mask provided on a semiconductor to prevent ion implantation into the semiconductor,
A first ion implantation mask layer;
A second ion implantation mask layer that is less etched than the first ion implantation mask layer;
A third ion implantation mask layer that is easier to etch than the second ion implantation mask layer;
An ion implantation mask including, in this order, from the semiconductor side.   2. The second ion implantation mask layer according to claim 1, wherein the second ion implantation mask layer is less likely to be etched by a fluorine-containing gas than each of the first ion implantation mask layer and the third ion implantation mask layer. Ion implantation mask.   The ion implantation mask according to claim 1, wherein at least one of the first ion implantation mask layer and the third ion implantation mask layer is made of tungsten or silicon.   The ion implantation mask according to claim 1, wherein the second ion implantation mask layer is made of titanium or aluminum.   5. The ion implantation mask according to claim 1, wherein an etching selectivity of the third ion implantation mask layer with respect to the second ion implantation mask layer is 2 or more.   The ion implantation mask according to claim 1, wherein an etching selectivity ratio of the first ion implantation mask layer to the second ion implantation mask layer is 2 or more.   The ion implantation mask according to claim 1, wherein a thickness of the first ion implantation mask layer is not less than 100 nm and not more than 30000 nm.   8. The ion implantation mask according to claim 1, wherein a thickness of the second ion implantation mask layer is not less than 5 nm and not more than 100 nm.   9. The ion implantation mask according to claim 1, wherein a thickness of the third ion implantation mask layer is not less than 50 nm and not more than 30000 nm. A fourth ion implantation mask layer on the semiconductor side of the first ion implantation mask layer;
The ion implantation mask according to claim 1, wherein the fourth ion implantation mask layer is less likely to be etched than the first ion implantation mask layer.   11. The fourth ion implantation mask layer according to claim 10, wherein the fourth ion implantation mask layer is less likely to be etched by a fluorine-containing gas than each of the first ion implantation mask layer and the third ion implantation mask layer. Ion implantation mask.   The ion implantation mask according to claim 10 or 11, wherein the fourth ion implantation mask layer is made of titanium or aluminum.   13. The ion implantation mask according to claim 10, wherein a thickness of the fourth ion implantation mask layer is larger than a thickness of the second ion implantation mask layer.   The ion implantation mask according to claim 13, wherein a thickness of the fourth ion implantation mask layer is 30 nm or more and 300 nm or less.   The ion implantation mask according to claim 1, wherein the semiconductor is silicon carbide.   An ion implantation method, comprising: forming an ion implantation mask according to any one of claims 1 to 15 on a semiconductor surface, and performing ion implantation on the semiconductor. A first step of forming the ion implantation mask according to claim 1 on a part of a surface of a semiconductor;
A second step of forming a first dopant implantation region by implanting ions of a first dopant into at least a part of the semiconductor region corresponding to a region other than the region where the ion implantation mask is formed;
A third step of removing a portion of the ion implantation mask in the width direction after the formation of the first dopant implantation region;
A fourth step of forming a second dopant implantation region by implanting ions of a second dopant into at least a part of the semiconductor region corresponding to the region removed in the width direction of the ion implantation mask;
A method for manufacturing a semiconductor device, comprising:   The semiconductor according to claim 17, further comprising a step of removing the second ion implantation mask layer and the third ion implantation mask layer between the third step and the fourth step. Device manufacturing method.