JP2008227197A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a protection circuit, by which an internal circuit formed in a semiconductor device is protected from a high voltage by an ESD. <P>SOLUTION: In a drain region 32 of a MOS for protection, there are arranged insulating regions 40, 42 of patterns which meander a current route 44 passing through the drain region 32. A resistance value of the broken-down MOS can be adjusted by adjusting pattern shapes of the insulating regions 40, 42. Even when a large resistance is needed, it is not necessary to lengthen the drain region 32. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which a protection circuit for protecting a circuit formed in the semiconductor device is formed in the semiconductor device.

The semiconductor device includes a circuit that realizes a function required for the semiconductor device (hereinafter referred to as an internal circuit) and an input pad for connecting and fixing an external wiring that connects the semiconductor device and the external device. The pads are connected by internal wiring.
When a semiconductor device is used, an abnormal high voltage may be applied to external wiring connected to the input pad. For example, a very large voltage may be applied when charged static electricity is discharged to the external wiring.
If an abnormal high voltage is applied to the external wiring connected to the input pad due to static electricity or the like, the internal circuit may be damaged. In particular, when the internal circuit uses a gate insulating film, a high voltage acts on the gate insulating film and the gate insulating film is easily destroyed.

  Therefore, a technique for forming a protection circuit in a semiconductor device is known, and an example thereof is disclosed in Patent Document 1. In this technique, a protection circuit is formed between the input pad and the ground pad. The protection circuit is connected in parallel to the internal circuit protected by the protection circuit. The protection circuit can be composed of a MOS. If the input pad and ground pad are connected in parallel to the internal circuit to be protected, the protective MOS will break if an abnormal high voltage is applied to the input pad via the external wiring. To go down. As a result, it is possible to prevent an abnormal high voltage from being applied to the internal circuit.

Japanese Patent Laid-Open No. 2004-273974

  When the MOS is used for the protection circuit, the MOS breaks down when an abnormal high voltage is applied to the input pad, so that the internal circuit can be protected from the abnormal high voltage. In order to appropriately protect the internal circuit, the resistance value of the MOS after the breakdown of the MOS is also important. This is because the slope of the snapback waveform changes depending on the breakdown resistance of the MOS, and the internal circuit (especially the gate insulating film) can be properly protected when the slope is adjusted to an appropriate value. is there.

The resistance value of the broken down MOS is mainly determined by the distance of the drain region. The drain region here refers to a region existing between a drain contact to which a drain wiring is connected and a region where an inversion layer is formed by a gate potential because it faces the gate electrode.
In order to adjust the resistance value of the broken down MOS to an appropriate value, it may be necessary to lengthen the drain region. In this case, it is necessary to increase the distance between the drain contact and the gate electrode, and the range in which the protective MOS is formed is increased. When the formation range of the protective MOS is increased, the semiconductor device is increased in size, and the manufacturing cost of the semiconductor device is increased.
There is a need for a technique for forming a protective MOS that requires a large resistance value after breakdown in a small area.

The present invention protects an internal circuit when an abnormal high voltage is applied to the input pad through an input pad, an internal circuit connected to the input pad, and an external wiring connected to the input pad. The present invention relates to a semiconductor device including a protection circuit. The protection circuit is composed of a MOS connected in parallel with the internal circuit between the input pad and the ground pad. When a semiconductor device is used, a ground wire is connected to the ground pad.
The present invention is characterized in that an insulating region having a pattern that meanders a current path passing through the drain region is disposed in the drain region of the protective MOS.
If an insulating region that meanders the current path is arranged in the drain region, a long current path can be secured in the short drain region, and the resistance value can be adjusted to a large value.

  The drain region can be formed of a layer extending along a predetermined range of the surface of the semiconductor substrate. In this case, the insulating region that meanders the current path can be formed by the field oxide film that reaches from the surface of the semiconductor substrate to the bottom of the layer forming the drain region. The field oxide film has a property of penetrating in the thickness direction of the semiconductor substrate and can reach the bottom of the layer forming the drain region. The pattern of the field oxide film when the semiconductor substrate is viewed in plan can be arbitrarily adjusted. When a pair of comb-shaped field oxide films are formed facing each other in the drain region, an insulating region having a pattern for meandering the current path can be prepared in advance.

According to the present invention, the protective MOS can be reduced in size. The number of semiconductor devices that can be manufactured from one wafer can be increased, and the manufacturing cost of the semiconductor device can be reduced.
When an insulating region is formed by a field oxide film, since the field oxide film is a member necessary for forming an internal circuit in many cases, a small MOS is not required without an extra process or an extra mask. Can be adjusted to a required value.

The main features of the techniques described in the following examples are listed.
(Embodiment 1) A pair of comb-shaped field oxide films are disposed facing each other in the drain region.
(Mode 2) The internal circuit to be protected includes a gate insulating film. The pattern of the insulating region formed in the drain region is adjusted according to the thickness of the gate insulating film.
(Mode 3) A plurality of types of gate insulating films are formed in the internal circuit, and a plurality of types of protective MOSs are formed correspondingly. A corresponding gate insulating film and a corresponding MOS are connected in parallel.

A semiconductor device according to an embodiment embodying the present invention will be described. FIG. 1 schematically shows a layout in plan view of a semiconductor device 1 of this embodiment.
The semiconductor device 1 is formed in a chip 2 obtained by dicing a semiconductor substrate, and connects and fixes an internal circuit 12 that realizes a function necessary for the semiconductor device 1 and an external wiring 8 that connects the semiconductor device 1 and the external device. An input pad 6 is provided. The internal circuit 12 and the input pad 6 are connected by the internal wiring 4.

  An abnormal high voltage may be applied to the external wiring 8. For example, charged static electricity may be discharged to the external wiring 8. The above phenomenon is referred to as ESD in this specification. When an abnormally high voltage due to ESD is applied to the external wiring 8, if the voltage is applied as it is to the internal circuit 12 via the input pad 6, the internal circuit 12 may be destroyed. In particular, when the internal circuit 12 includes a gate insulating film, the gate insulating film is easily broken. The thickness of the gate insulating film affects the operating voltage of the internal circuit 12. In order to realize an operating voltage at a low level, it is necessary to make the gate insulating film thin. Since it is often not allowed to increase the thickness of the gate insulating film in order to protect it from high voltage, the gate insulating film is easily broken.

  Therefore, the semiconductor device 1 includes a protection circuit 20 that protects the internal circuit 12 from a high voltage. The protection circuit 20 is formed between the input pad 6 and the grounding pad 16 by the internal wirings 10 and 14. When the semiconductor device 1 is used, a ground wire 18 is connected to the ground pad 16 and grounded. The protection circuit 20 is connected in parallel to the internal circuit 12.

FIG. 2B shows a cross-sectional view of the protection circuit 20 formed in the chip 2. For convenience of explanation, a conventional protection circuit 60 will be described first with reference to FIG. The protection circuit 60 has a MOS structure. That is, a p-type well 64 formed in the n-type semiconductor substrate 62, an n-type source region 66 formed in the p-type well 64, and a p-type well 64. An n-type drain region 72 is provided. The n-type source region 66 and the n-type drain region 72 are spaced apart from each other, and a gate insulating film 68 is formed on the p-type region that separates the n-type source region 66 and the n-type drain region 72. Is formed, and a gate electrode 70 is formed thereon. The drain contact 74 is formed at a position farthest from the gate electrode 70 in the drain region 72.
The source region 66 is connected to the grounding pad 16 by the internal wiring 14. The gate electrode 70 is connected to the source region 66. The drain contact 74 is connected to the input pad 6 by the internal wiring 10.

  The MOS constituting the protection circuit 60 breaks down when a high voltage is applied to the drain contact 74. The resistance value of the broken down MOS is determined by the distance between the gate electrode 70 and the drain contact 74 (that is, the distance between the drain regions 72). When the resistance value necessary for protecting the internal circuit 12 is high, the long drain region 72 is required, and the protection circuit 60 is enlarged.

FIG. 2B shows a longitudinal sectional view of the protection circuit 20 of this embodiment. The protection circuit 20 also has a MOS structure. A p-type well 24 formed in the n-type semiconductor substrate 22, an n-type source region 26 formed in the p-type well 24, and an n-type formed in the p-type well 24. The drain region 32 is provided. The n-type source region 26 and the n-type drain region 32 are spaced apart from each other, and the gate insulating film 28 is formed on the p-type region that separates the n-type source region 26 and the n-type drain region 32. Is formed, and a gate electrode 30 is formed thereon. The drain contact 34 is formed at a position farthest from the gate electrode 30 in the drain region 32.
The source region 26 is connected to the grounding pad 16 by the internal wiring 14. The gate electrode 30 is connected to the source region 26. The drain contact 34 is connected to the input pad 6 by the internal wiring 10.

In the drain region 32, field oxide films 40 and 42 reaching the bottom surface of the n layer forming the drain region 32 are formed. The field oxide films 40 and 42 penetrate into the p-type well 24 through the bottom surface of the drain region 32.
FIG. 3 shows a cross section taken along line III-III in FIG. The pair of field oxide films 40 and 42 extend from both sides of the drain region 32 to the vicinity of the position beyond the center in the width direction. The pair of field oxide films 40 and 42 has a shape in which comb-like patterns are arranged to face each other. In this case, the current passing through the drain region 32 meanders as indicated by an arrow 44. The distance of the current path from the gate electrode 30 to the drain contact 34 is long.
For this reason, as shown in comparison with FIG. 2, even though the resistance value necessary to protect the internal circuit 12 is the same, the long drain region 72 is required according to the prior art. On the other hand, according to the present embodiment, a short drain region 32 is sufficient. The protection circuit 20 is smaller than the protection circuit 60.

  The MOS constituting the protection circuit 20 breaks down when a high voltage is applied to the drain region 34. At this time, the parasitic transistor 36 including the n-type source region 26, the p-type well 24, and the n-type drain region 32 is turned on. When the parasitic transistor 36 is turned on, a high voltage is not applied to the internal circuit 12. The internal circuit 12 can be protected. In order to protect the internal circuit 12, not only the parasitic transistor 36 is turned on, but also the resistance value when the parasitic transistor 36 is turned on is important. This is because the slope of the snapback waveform changes depending on the resistance value when the parasitic transistor 36 is turned on, and the internal circuit can be appropriately protected when the slope is adjusted to an appropriate value.

  In this embodiment, the field oxide films 40 and 42 are formed in the drain region 32 to adjust the resistance value of the drain region 32. Even if the drain region 32 is short, a resistance value necessary to protect the internal circuit 12 can be realized. With the short drain region 32, the protection circuit 20 can be realized.

  When a plurality of types of gate insulating films are formed in the internal circuit 12 to be protected, the required resistance value may differ depending on the type of the gate insulating film. In this case, a plurality of types of protective MOSs are required. According to the present embodiment, the resistance value of the MOS can be adjusted depending on the shape of the field oxide films 40 and 42, so that a plurality of types of protective MOSs having different resistance values can be easily manufactured.

  The field oxide films 40 and 42 are often required to manufacture the internal circuit 12. In this case, the field oxide films 40 and 42 can be formed simultaneously with the formation of the field oxide film for the internal circuit 12. No extra man-hours are required for forming the field oxide films 40 and 42.

  In the present embodiment, as shown in FIG. 3, the current path 44 meanders in the drain region 32 in a state where the chip 2 or the semiconductor substrate 22 is viewed in plan. The shape of the current path 44 is determined by the planar shape of the field oxide films 40 and 42, and the thickness of the field oxide films 40 and 42 has little influence. Due to the nature of the manufacturing technology, it is not easy to accurately manage the thickness of the field oxide films 40 and 42, but the planar shape of the field oxide films 40 and 42 is easy to manage accurately. In this embodiment, since the resistance of the drain region 32 is adjusted by the planar shape of the field oxide films 40 and 42 that are easy to manage, variations in the drain resistance when the semiconductor device 1 is mass-produced can be suppressed.

In FIG. 2B, the drain region 32 is formed with a stacked structure of a surface layer having a high impurity concentration and a deep layer having a low impurity concentration, and a field oxide film 40 that reaches the deep layer across the surface layer is formed. Then, the current path in the drain region 32 can be meandered in the vertical plane. This structure also makes it possible to secure the necessary drain resistance with a small drain region. However, in this structure, the thickness of the field oxide film 40 directly affects the drain resistance. As described above, since it is not easy to accurately manage the thickness of the field oxide film 40, it is difficult to manage the drain resistance. According to the structure in which the current path is meandered in the vertical plane, the drain resistance is deviated from a desired value, and the internal circuit cannot be properly protected.
Furthermore, the structure in which the current path meanders in the vertical plane requires a surface layer having a high impurity concentration and a deep layer having a low impurity concentration, which complicates the manufacturing process. A surface layer having a high impurity concentration is also required for the source region, whereas a deep layer having a low impurity concentration is not required in the source region. Since the surface layer formation range and the deep layer formation range are different, different masks are required, and different impurity implantation steps are required. The structure of this embodiment also has an advantage that the manufacturing process is simple.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

The top view of a semiconductor device. The figure which contrasts and shows sectional drawing of protection MOS. III-III sectional view taken on the line of FIG.

Explanation of symbols

1: Semiconductor device 2: Chip 4: Internal wiring 6: Input pad 8: External wiring 10: Internal wiring 14: Internal wiring 16: Grounding pad 18: Grounding wire 20: Protection circuit 22: Semiconductor substrate 24: p-type well 26: source region 28: gate insulating film 30: gate electrode 32: drain region 34: drain contact 36: parasitic transistors 40, 42: field oxide film

Claims (2)

An input pad;
An internal circuit connected to the input pad;
A semiconductor device including a protection circuit that protects the internal circuit when an abnormal high voltage is applied to the input pad via an external wiring connected to the input pad;
The protection circuit is composed of a MOS connected in parallel with the internal circuit between the input pad and the ground pad,
A semiconductor device characterized in that an insulating region having a pattern that meanders a current path passing through the drain region is arranged in the drain region of the MOS. The drain region is formed of a layer extending along a predetermined range of the surface of the semiconductor substrate,
2. The semiconductor device according to claim 1, wherein an insulating region that causes the current path to meander is formed by a field oxide film reaching from the surface of the semiconductor substrate to the bottom of the layer.

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