JP2008226211A5 - - Google Patents

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Publication number
JP2008226211A5
JP2008226211A5 JP2007070523A JP2007070523A JP2008226211A5 JP 2008226211 A5 JP2008226211 A5 JP 2008226211A5 JP 2007070523 A JP2007070523 A JP 2007070523A JP 2007070523 A JP2007070523 A JP 2007070523A JP 2008226211 A5 JP2008226211 A5 JP 2008226211A5
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JP
Japan
Prior art keywords
clock
memory
memory controller
read
host system
Prior art date
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Application number
JP2007070523A
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English (en)
Japanese (ja)
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JP5152466B2 (ja
JP2008226211A (ja
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Application filed filed Critical
Priority to JP2007070523A priority Critical patent/JP5152466B2/ja
Priority claimed from JP2007070523A external-priority patent/JP5152466B2/ja
Publication of JP2008226211A publication Critical patent/JP2008226211A/ja
Publication of JP2008226211A5 publication Critical patent/JP2008226211A5/ja
Application granted granted Critical
Publication of JP5152466B2 publication Critical patent/JP5152466B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2007070523A 2007-02-13 2007-03-19 メモリコントローラ Expired - Fee Related JP5152466B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007070523A JP5152466B2 (ja) 2007-02-13 2007-03-19 メモリコントローラ

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007031879 2007-02-13
JP2007031879 2007-02-13
JP2007070523A JP5152466B2 (ja) 2007-02-13 2007-03-19 メモリコントローラ

Publications (3)

Publication Number Publication Date
JP2008226211A JP2008226211A (ja) 2008-09-25
JP2008226211A5 true JP2008226211A5 (https=) 2010-08-05
JP5152466B2 JP5152466B2 (ja) 2013-02-27

Family

ID=39844686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007070523A Expired - Fee Related JP5152466B2 (ja) 2007-02-13 2007-03-19 メモリコントローラ

Country Status (1)

Country Link
JP (1) JP5152466B2 (https=)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6134638A (en) * 1997-08-13 2000-10-17 Compaq Computer Corporation Memory controller supporting DRAM circuits with different operating speeds
JP4373595B2 (ja) * 2000-09-25 2009-11-25 株式会社東芝 コンピュータシステム
JP4841069B2 (ja) * 2001-07-24 2011-12-21 パナソニック株式会社 記憶装置
JP2006091940A (ja) * 2004-09-21 2006-04-06 Matsushita Electric Ind Co Ltd メモリ制御装置

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