JP2008224796A - Ram incorporated drive ic, display unit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a RAM incorporated drive IC which employs a differential pulse encode modulation system and is high in flexibility of the panel used. <P>SOLUTION: The RAM incorporated drive IC includes an encoder 110 which encodes input image data by the differential pulse code modulation system and outputs the encoded data; a RAM 120 which stores the encoded data; a decoder 130 which decodes and outputs the encoded data stored in the RAM 120; and an information storage unit 150, which stores positional information on the RAM storing head data of the encoded data, the data area of one line of the encoded data. The IC is such that direction information wherein data right after the head data are present, where the encoder 110 stores the encoded data in the RAM 120, on the basis of the positional information, the data area of one line, and the direction information in the information storage unit 150, and the decoder 130 decodes and outputs the encoded data from the RAM 120 on the basis of the positional information, the data area of one line, and the direction information in the information storage unit 150. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a driver IC with a built-in RAM, a display unit, and an electronic device used for a display device such as a liquid crystal, a plasma, an organic EL display, a printer, and the like.

  For example, taking a liquid crystal display device of a mobile phone as an example, the number of pixels on a display has increased in recent years and the number of gradations per pixel has increased in order to perform high-definition display. The current mainstream QVGA (240 x 320 dots) will be shifted to VGA (480 x 640 dots) or WVGA (480 x 800 dots). In QVGA, the gradation value per pixel is 16 bits or 18 bits. However, with VGA or WVGA, the gradation is increased to 18 bits or 24 bits. The increase in the number of pixels and the gradation value causes an increase in the frame memory capacity and has a serious effect.

  The increase in the frame memory cannot be found unless the driver IC with built-in RAM is fundamentally reconsidered. For example, the change of QVGA → VGA increases the memory area by a factor of 4, and the area of the RAM built-in driver IC also increases significantly. In that case, a driver IC with a built-in RAM mounted on a glass substrate by COG (Chip On Grass) increases the glass substrate area of the liquid crystal panel only for mounting the driver IC, and the number of panels to be taken when divided from the manufacturing substrate. Decrease. In addition, the shape of the rectangular conventional driver IC whose long axis is the short side of the glass substrate cannot be maintained. COG mounting is no longer possible, and it must be completely changed to COF (Chip On Film).

  The above problem is not limited to liquid crystal display devices, but high-definition image data is transferred between an integrated circuit serving as an image output source that receives or generates an image and an integrated circuit that drives a display unit or a printer. Is common.

  In order to solve this problem, for example, Patent Document 1 and Patent Document 2 describe a method of compressing the memory capacity to nearly half of the original image data by encoding the image data by the differential pulse code modulation method. Has been.

  Differential pulse code modulation (DPCM) is a method of taking the difference between adjacent samples, and between the first pixel data and the next pixel data of one line of image data. The difference is sequentially calculated and the data is compressed. For example, when the image data is composed of 8 bits for each of RGB, the original pixel data requires a 24-bit memory area. In the case of a VGA panel, a memory capacity of 480 × 640 × 24 bits = 73732800 bits is required. However, according to the differential pulse code modulation method, only the first pixel data in one row is 24 bits, and the subsequent pixel data is Since the data can be compressed to 12 bits, the memory capacity is 1 × 640 × 24 bits + 479 × 640 × 12 bits = 36994080 bits, and a memory capacity of about 50.1% without compression is sufficient.

Japanese Patent Laid-Open No. 1-112377 JP 2001-257888 A

  However, in a driver IC with a built-in RAM using the differential pulse code modulation method, the storage position of the first pixel data must be placed at the end of the RAM, and a plurality of panels (for example, widths) having different widths with a single driver IC with a built-in RAM. However, it is necessary to completely align the edge of the panel and the edge of the driver IC, and the freedom of routing from the driver output to the pixels of the panel is completely eliminated. There's a problem.

  The present invention has been made in view of such circumstances, and provides a driver IC with a built-in RAM, a display unit, and an electronic device that can reduce the memory capacity by a differential pulse code modulation method and have a high degree of freedom for a panel to be used. It is intended to do.

  In order to solve the above-mentioned problems, the RAM built-in driver IC according to the present invention encodes input image data by a differential pulse code modulation method and outputs the encoded data, and stores the encoded data. A RAM for decoding, a decoder for decoding and outputting the encoded data stored in the RAM, position information of the RAM for storing leading data of the encoded data, and a data area for one line of the encoded data And an information storage unit that stores direction information with next data with respect to the head data, and the encoder includes the position information of the information storage unit, the data area for the one row, and the information The encoded data is stored in the RAM based on direction information, and the decoder is based on the position information of the information storage unit, the data area for one row, and the direction information. And summarized in that the can the RAM outputs to decoding the encoded data.

  According to this configuration, the position of the top data, the data area for one line, and the direction information can be freely changed according to the specifications of the panel. Can be provided.

  In order to solve the above problems, in the RAM built-in driver IC of the present invention, the input image data is divided into k blocks (k is a natural number of 1 or more) in the row direction, and differential pulse code modulation is performed for each block. One or more encoders that encode and output the encoded data, a RAM that stores the encoded data, and the encoded data stored in the RAM for each block are decoded and output One or more decoders, position information of the RAM for storing the head data of the encoded data for each of the k blocks, the data area of the encoded data, and the next data with respect to the head data Direction information, and an information storage unit that stores the direction information, and the encoder includes, for each of the k blocks, the position information of the information storage unit and the data area for one row. The encoded data is stored in the RAM based on the direction information, and the decoder is based on the position information of the information storage unit, the data area for one row, and the direction information for each of the k blocks. The gist is to decode and output the encoded data from the RAM.

  According to this configuration, the position, data area, and direction information of the head data can be freely changed for every k blocks according to the panel specifications. A driver IC with a built-in RAM having a high degree of freedom can be provided when rewriting an image.

  In addition, the display unit of the present invention includes a panel having an electro-optic element and the above-described RAM built-in driver IC that drives the panel.

  The electronic device of the present invention includes the display unit described above.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.

(First embodiment)
<Configuration of electronic equipment>
First, the configuration of the electronic apparatus according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to the first embodiment of the present invention. FIG. 1 shows an embodiment in which an electronic device of the present invention is applied to a mobile phone. As shown in FIG. 1, the electronic device 1 includes a display unit 10 and a baseband engine 200. The display unit 10 includes a liquid crystal panel 2 and a RAM built-in driver IC 100. The driver IC 100 with built-in RAM is connected to the baseband engine 200 through a plurality of bus lines 6 and transfers image data, horizontal / vertical synchronization signals, clock signals, and various commands.

  A baseband engine (BBE: image supply-side IC in a broad sense) 200 is an LSI circuit (Large Scale Integrated Circuit) that controls the basic functions of a mobile phone. This is an output source of various image data such as characters and graphic information such as icons and menu screens necessary for operation of mobile phones.

  The liquid crystal panel 2 is a liquid crystal sealed between two glass substrates 3 and 4. The large glass substrate 3 is an active matrix substrate, for example, and each pixel is provided with a TFT (Thin Film Transistor) which is an active element. A transparent pixel electrode is connected to the drain terminal of the TFT of each pixel, a source line that is a data line is connected to the source terminal, and a gate line that is a scanning line is connected to the gate terminal. A transparent electrode is provided on the glass substrate 4 facing the glass substrate 3. On the glass substrate 3, a driver IC 100 with a built-in RAM is COG mounted along the short side of the glass substrate 3. The RAM built-in driver IC 100 supplies the scanning signal to the gate line of the liquid crystal panel 2 and supplies the data signal to the source line to drive the liquid crystal panel 2 for display.

<Configuration of driver IC with built-in RAM>
Next, the configuration of the RAM built-in driver IC will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the RAM built-in driver IC. As shown in FIG. 2, the RAM built-in driver IC 100 includes an encoder 110 that encodes image data output from the baseband engine 200, and a RAM (Random Access Memory) 120 that stores the encoded data encoded by the encoder 110. A decoder 130 that decodes encoded data stored in the RAM 120 into original image data, a driver unit 140 that drives the liquid crystal panel 2 based on the decoded image data, a register 150 that is an information storage unit, It is composed of The encoder 110 and the RAM 120 are connected by a plurality of bus lines 7, the RAM 120 and the decoder 130 are connected by a plurality of bus lines 8, and the decoder 130 and the driver unit 140 are connected by a plurality of bus lines 9.

  The encoder 110 that encodes the image data from the baseband engine 200 is guaranteed to compress and encode the image data of each frame for one frame at a compression rate equal to or higher than a specified compression rate (for example, 50%). Yes. The encoder 110 can also ensure that the image data of each line for one line is compressed and encoded at a compression rate equal to or higher than a specified compression rate.

<Operation of differential pulse code modulation method>
Next, the operation of the differential pulse code modulation method of the RAM built-in driver IC will be described with reference to FIGS.

  FIG. 3 is a block diagram showing processing of the head image data. As shown in FIG. 3, the baseband engine 200 sends 24-bit image data P01 to PXX for one row (for example, PXX is P240 if the number of pixels in the short side direction of the liquid crystal panel 2 is 240) to the bus line 6. To the encoder 110 sequentially.

  The encoder 110 includes an encoding circuit 111, a 24-bit register 112 that stores the image data output from the baseband engine 200, and a 24-bit register 113 that stores the previous image data for difference calculation. Have. The encoding circuit 111 calculates a difference from the image data in the register 112 on the basis of the image data in the register 113 and outputs the encoded data compressed to 12 bits to a predetermined address in the RAM 120 via the bus line 7. However, the first image data is output as 24 bits. Thereafter, the image data in the register 112 is stored in the register 113 as the previous image data after encoding.

  The decoder 130 includes a decoding circuit 131, a 24-bit register 133 for storing the decoded image data, and a 24-bit register 132 for storing the previous image data for difference calculation. The decode circuit 131 reads 12-bit encoded data at a predetermined address from the RAM 120 via the bus line 8, performs a difference calculation based on the image data in the register 132, and stores the image data decoded into 24 bits in the register 133. Store. However, the first image data is read as 24 bits and stored in the register 133. The image data stored in the register 133 is output to the driver unit 140. Thereafter, the image data in the register 133 is stored in the register 132 as the previous image data after decoding.

  When the head image data P01 from the baseband engine 200 is stored in the register 112, the encoder 110 is transferred from the encoding circuit 111 to the head address of the RAM 120 without being compressed. The first image data P01 is stored in the register 113 as the previous image data.

  The decoder 130 reads the leading image data P01 from the RAM 120, stores it in the register 133 via the decoding circuit 131, and outputs it to the driver unit 140. The head image data P01 of the register 133 is stored in the register 132 as the previous image data.

  FIG. 4 is a block diagram showing the processing of the second image data.

  When the second image data P02 from the baseband engine 200 is stored in the register 112, the encoder 110 performs a difference calculation with the previous image data P01 stored in the register 113 by the encoding circuit 111, and obtains 12 bits. The encoded data p02 compressed and encoded to the next address is transferred to the address next to the head image data P01 in the RAM 120. The second image data P02 is stored in the register 113 as the previous image data.

  The decoder 130 reads the encoded data p02 from the RAM 120, calculates a difference from the previous image data P01 stored in the register 132 by the decoding circuit 131, and stores the decoded 24-bit image data P02 in the register 133. And output to the driver unit 140. The image data P02 in the register 133 is stored in the register 132 as the previous image data.

  FIG. 5 is a block diagram showing the processing of the third image data.

  When the third image data P03 from the baseband engine 200 is stored in the register 112, the encoder 110 performs a difference calculation with the previous image data P02 stored in the register 113 by the encoding circuit 111, and obtains 12 bits. The encoded data p03 compressed and encoded to the next address is transferred to the address next to the encoded data p02 in the RAM 120. The third image data P03 is stored in the register 113 as the previous image data.

  The decoder 130 reads the encoded data p03 from the RAM 120, calculates a difference from the previous image data P02 stored in the register 132 by the decoding circuit 131, and stores the decoded 24-bit image data P03 in the register 133. And output to the driver unit 140. The image data P03 in the register 133 is stored in the register 132 as the previous image data.

  Similarly, image data P01 to PXX for one line are processed.

<Register configuration>
Next, the register configuration of the RAM built-in driver IC will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the register of the RAM built-in driver IC. As shown in FIG. 6, the register 150 of the driver IC 100 with a built-in RAM has a storage area 151 for storing address information of the RAM 120 for storing the leading image data, and a storage area for storing a data area for one line of encoded data. 152, and a storage area 153 for storing direction information in which the next data is present with respect to the head image data. The encoder 110 and the decoder 130 obtain from the register 150 the position of the top image data, the data area for one line of the encoded data, and the direction information with the next data for the top image data. , Exchange data with the RAM 120.

  FIG. 6A is a block diagram showing the setting of the register 150 for the conventional configuration in which the width W01 of the RAM 120 is fully used. As shown in FIG. 6A, the leading image data P01 is arranged at the leading address H01 of the RAM 120, and the encoded data P01, p02 to pXX for one row is arranged in the right direction D01 with the data area width W01. In the register 150, H01 is set in the storage area 151, W01 is set in the storage area 152, and D01 is set in the storage area 153.

  FIG. 6B is a block diagram showing the setting of the register 150 for the configuration of the present invention that uses the RAM 120 less than the width W01. As shown in FIG. 6B, the leading image data P01 is arranged at the address H02 of the RAM 120, and the encoded data P01, p02 to pXX for one line is arranged in the right direction D02 with the data area width W02. In the register 150, H02 is set in the storage area 151, W02 is set in the storage area 152, and D02 is set in the storage area 153.

  FIG. 6C is a block diagram showing the setting of the register 150 for a configuration in which encoded data is arranged in the left direction using the RAM 120 less than the width W01. As shown in FIG. 6C, the leading image data P01 is arranged at the address H03 of the RAM 120, and the encoded data P01, p02 to pXX for one row with the data area width W03 is arranged in the left direction D03. In the register 150, H03 is set in the storage area 151, W03 is set in the storage area 152, and D03 is set in the storage area 153.

  According to the embodiment described above, the following effects can be obtained.

  In this embodiment, the memory capacity can be reduced by the differential pulse code modulation method, and the position of the top data, the data area for one row, and the direction information can be freely changed according to the specifications of the panel. In contrast, a driver IC with a built-in RAM having a high degree of freedom can be provided. For example, a panel built-in RAM driver IC having 240 pixel data in the width direction can be used and used for a panel having 220 or 200 pixel data in the width direction.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, In the range which does not deviate from the meaning of this invention, it can be implemented with various forms. Hereinafter, a modification will be described.

  (Modification 1) Modification 1 of the electronic apparatus according to the present invention will be described. In the first embodiment, the case where the electronic device is applied to a mobile phone has been described.

  (Modification 2) Modification 2 of the electronic apparatus according to the present invention will be described. In the first embodiment, the case where the storage location of the first image data P01 in the RAM 120 is set to one location has been described, but two or more locations may be set in advance.

  (Modification 3) Modification 3 of the electronic apparatus according to the present invention will be described. In the first embodiment, it has been described that the subsequent image data is arranged next to the head image data P01.

  (Modification 4) Modification 4 of the electronic apparatus according to the present invention will be described. In the first embodiment, one row of image data is defined as one block, and there is one encoder 110, one decoder 130, and one register 150. However, image data is divided into a plurality of blocks in the row direction. May be. For example, as shown in FIG. 7, the row direction is divided into three blocks. As information of the first block, H01 is set in the storage area 151 of the register 150, W01 is set in the storage area 152, and D01 is set in the storage area 153. As information of the second block, H11 is set in the storage area 161 of the register 150, W11 is set in the storage area 162, and D11 is set in the storage area 163. As the information of the third block, H21 is set in the storage area 171 of the register 150, W21 is set in the storage area 172, and D21 is set in the storage area 173. It should be noted that encoding and decoding may be sequentially performed with respect to three blocks by one encoder 110 and one decoder 130, and an encoder 110 and a decoder 130 may be provided for each of the three blocks.

  (Modification 5) Modification 5 of the electronic apparatus according to the present invention will be described. In the first embodiment, the case where the image data of all the pixels of the liquid crystal panel 2 is rewritten has been described. However, for example, only the image in the subwindow in the area smaller than the previous image data that has already been displayed is rewritten. Also good. If the image data is divided into a plurality of blocks in the row direction, the blocks necessary for displaying the sub-window may be decoded, the image data replaced with new image data, and encoded again.

1 is a block diagram showing a configuration of an electronic device according to a first embodiment of the present invention. The block diagram which shows the structure of driver IC with built-in RAM. The block diagram which shows the process of the top image data. The block diagram which shows the process of 2nd image data. The block diagram which shows the process of 3rd image data. The block diagram which shows the structure of the register | resistor of driver IC with built-in RAM. The block diagram which shows the structure of the register | resistor of RAM built-in driver IC of the modification 5. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Liquid crystal panel, 3, 4 ... Glass substrate, 110 ... Encoder, 111 ... Encoding circuit, 112, 113 ... Register, 120 ... RAM, 130 ... Decoder, 131 ... Decoding circuit, 132, 133 ... Register 140 ... Driver unit, 150 ... Register, 200 ... Baseband engine.

Claims (4)

An encoder that encodes input image data using a differential pulse code modulation method and outputs encoded data;
RAM for storing the encoded data;
A decoder for decoding and outputting the encoded data stored in the RAM;
Information storage for storing position information of the RAM for storing the head data of the encoded data, a data area for one row of the encoded data, and direction information for the next data with respect to the head data And
Including
The encoder stores the encoded data in the RAM based on the position information of the information storage unit, the data area for one row, and the direction information,
The decoder decodes and outputs the encoded data from the RAM based on the position information in the information storage unit, the data area for one row, and the direction information.
A driver IC with a built-in RAM. The input image data is divided into k blocks (k is a natural number of 1 or more) in the row direction,
One or more encoders that encode the differential pulse code modulation method for each block and output the encoded data;
RAM for storing the encoded data;
One or more decoders that decode and output the encoded data stored in the RAM for each block;
For each of the k blocks, position information of the RAM that stores the head data of the encoded data, a data area of the encoded data, and direction information that has next data with respect to the head data An information storage unit for storing;
Including
The encoder stores the encoded data in the RAM based on the position information of the information storage unit, the data area for one row, and the direction information for each of the k blocks.
The decoder decodes and outputs the encoded data from the RAM based on the position information of the information storage unit, the data area for one row, and the direction information for each of the k blocks.
A driver IC with a built-in RAM. A panel having an electro-optic element;
The RAM built-in driver IC according to claim 1 or 2, which drives the panel;
including,
A display unit characterized by that.   An electronic device comprising the display unit according to claim 3.

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