JP2008222509A - METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM - Google Patents

METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM Download PDF

Info

Publication number
JP2008222509A
JP2008222509A JP2007064765A JP2007064765A JP2008222509A JP 2008222509 A JP2008222509 A JP 2008222509A JP 2007064765 A JP2007064765 A JP 2007064765A JP 2007064765 A JP2007064765 A JP 2007064765A JP 2008222509 A JP2008222509 A JP 2008222509A
Authority
JP
Japan
Prior art keywords
epitaxial film
sic epitaxial
single crystal
crystal substrate
sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007064765A
Other languages
Japanese (ja)
Inventor
Tsutomu Kiyozawa
努 清澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2007064765A priority Critical patent/JP2008222509A/en
Publication of JP2008222509A publication Critical patent/JP2008222509A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a single crystal substrate with an SiC epitaxial film by which crystal defects in the SiC epitaxial film can be reduced and the crystal quality of the film can be improved. <P>SOLUTION: The method comprises: a film deposition process for depositing an SiC epitaxial film 2 on an off-cut SiC single crystal substrate 1; and a heating process for reducing crystal defects by heating the deposited SiC epitaxial film 2 so as to generate step bunching 3 on the surface of the SiC epitaxial film 2. Further, the method may include a flattening process for removing the step bunching 3 generated on the surface of the SiC epitaxial film 2 by CMP (chemomechanical polishing), gas etching in a hydrogen atmosphere, or the like, for producing a device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ＳｉＣエピタキシャル膜付き単結晶基板の製造方法に関するもので、より詳細には、ＣＶＤ（化学的気相成長）法を用いて、ＳｉＣ単結晶基板上へのＳｉＣエピタキシャル膜をエピタキシャル成長させるＳｉＣエピタキシャル膜付き基板の製造技術に関するものである。   The present invention relates to a method for manufacturing a single crystal substrate with an SiC epitaxial film, and more specifically, SiC by epitaxially growing an SiC epitaxial film on an SiC single crystal substrate using a CVD (chemical vapor deposition) method. The present invention relates to a manufacturing technique of a substrate with an epitaxial film.

ＳｉＣ単結晶基板上にＳｉＣエピタキシャル膜を成膜する際には、従来はＣＭＰ（化学的機械研磨）と水素エッチングによってＳｉＣ単結晶基板の表面処理を行った後、ＣＶＤによりＳｉＣエピタキシャル膜を成膜していた。このように成膜の前にＳｉＣ単結晶基板の表面処理を行うことにより、ＳｉＣエピタキシャル膜中のＢＰＤ（基底面転位）を減少させて結晶品質の良いＳｉＣエピタキシャル膜を得ていた（例えば、特許文献１参照）。
特開２００５―３１１３４８号公報 Conventionally, when an SiC epitaxial film is formed on an SiC single crystal substrate, surface treatment of the SiC single crystal substrate is performed by CMP (chemical mechanical polishing) and hydrogen etching, and then the SiC epitaxial film is formed by CVD. Was. Thus, by performing the surface treatment of the SiC single crystal substrate before film formation, the BPD (basal plane dislocation) in the SiC epitaxial film is reduced to obtain a SiC epitaxial film having a good crystal quality (for example, a patent) Reference 1).
JP 2005-31348 A

しかしながら、従来の方法においては、ＳｉＣ単結晶基板とＳｉＣエピタキシャル膜との界面の状態に起因して発生するＢＰＤを減少させることはできるが、ＳｉＣエピタキシャル膜の成膜中に発生する結晶欠陥を減少させることができない。従って、成膜後の結晶品質は満足できるものではなかった。   However, in the conventional method, BPD generated due to the state of the interface between the SiC single crystal substrate and the SiC epitaxial film can be reduced, but the crystal defects generated during the deposition of the SiC epitaxial film are reduced. I can't let you. Therefore, the crystal quality after film formation was not satisfactory.

本発明は、前記従来技術の課題を解決するもので、ＳｉＣエピタキシャル膜の成膜中に発生する結晶欠陥を減少させ、成膜後の結晶品質に優れたＳｉＣエピタキシャル膜付き単結晶基板を提供することを目的とする。   The present invention solves the above-mentioned problems of the prior art, and provides a single crystal substrate with an SiC epitaxial film that reduces crystal defects generated during the film formation of an SiC epitaxial film and is excellent in crystal quality after film formation. For the purpose.

従来の課題を解決するために、本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造方法は、オフ角を有するＳｉＣ単結晶基板が設置されている反応容器内に珪化水素ガスおよび炭化水素ガスを水素と共に導入しながら第１の温度で且つ第１の圧力で加熱することによりＳｉＣエピタキシャル膜を成膜する第１の工程と、第２の温度で前記ＳｉＣエピタキシャル膜の表面粗さＲａが１ｎｍ以上になるまで加熱を行う第２の工程と、を含むことを特徴とする。   In order to solve the conventional problems, a method for producing a single crystal substrate with an SiC epitaxial film according to the present invention includes hydrogen silicide gas and hydrocarbon gas in a reaction vessel in which an SiC single crystal substrate having an off angle is installed. A first step of forming a SiC epitaxial film by heating at a first temperature and a first pressure while being introduced together with the surface roughness Ra of the SiC epitaxial film at 1 nm or more at a second temperature. And a second step of heating until.

さらに、本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造方法は、オフ角を有するＳｉＣ単結晶基板が設置されている反応容器内に珪化水素ガスおよび炭化水素ガスを水素と共に導入しながら第１の温度で且つ第１の圧力で加熱することによりＳｉＣエピタキシャル膜を成膜する第１の工程と、第２の温度で且つ前記第１の圧力以下で前記ＳｉＣエピタキシャル膜の表面粗さＲａが１ｎｍ以上になるまで加熱を行う第２の工程と、を含むことを特徴とする。   Furthermore, the method for producing a single crystal substrate with an SiC epitaxial film according to the present invention includes a first method while introducing hydrogen silicide gas and hydrocarbon gas together with hydrogen into a reaction vessel in which an SiC single crystal substrate having an off angle is installed. A first step of forming a SiC epitaxial film by heating at a temperature and a first pressure; and a surface roughness Ra of the SiC epitaxial film at a second temperature and below the first pressure is 1 nm or more And a second step of heating until.

本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造方法によれば、ＳｉＣエピタキシャル膜の成膜後に加熱処理を行うことによってＳｉＣエピタキシャル膜の成膜中に発生した結晶欠陥を減少させることができる。   According to the method for manufacturing a single crystal substrate with an SiC epitaxial film of the present invention, the crystal defects generated during the film formation of the SiC epitaxial film can be reduced by performing the heat treatment after the film formation of the SiC epitaxial film.

以下に、本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造方法の実施の形態を図面とともに詳細に説明する。
（実施の形態１）
本発明における実施の形態１について説明する。図１は、本発明の工程フローの概略図を示したものである。図１に示すように、本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造方法は、オフカットされたＳｉＣ単結晶基板１上にＳｉＣエピタキシャル膜２を成膜する成膜工程（図１ａ）と、ＳｉＣエピタキシャル膜２を加熱することでＳｉＣエピタキシャル膜２の表面にステップバンチング３を発生させて結晶欠陥を減少させる加熱工程（図１ｂ）とからなる。また、デバイスを作製するために、このＳｉＣエピタキシャル膜２の表面に発生させたステップバンチング３をＣＭＰ等により除去する平坦化工程（図１ｃ）を追加しても良い。 Hereinafter, embodiments of a method for producing a single crystal substrate with an SiC epitaxial film according to the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
A first embodiment of the present invention will be described. FIG. 1 shows a schematic diagram of the process flow of the present invention. As shown in FIG. 1, the method for manufacturing a single crystal substrate with an SiC epitaxial film of the present invention includes a film forming step (FIG. 1 a) for forming an SiC epitaxial film 2 on an off-cut SiC single crystal substrate 1, It consists of a heating step (FIG. 1b) in which step bunching 3 is generated on the surface of the SiC epitaxial film 2 by heating the SiC epitaxial film 2 to reduce crystal defects. In order to fabricate a device, a planarization step (FIG. 1c) for removing the step bunching 3 generated on the surface of the SiC epitaxial film 2 by CMP or the like may be added.

各工程のより詳細な説明を、以下に記載する。図１ａは、オフカットされたＳｉＣ単結晶基板１上にＳｉＣエピタキシャル膜２を成膜する成膜工程である。ＳｉＣ単結晶基板１は、（０００１）結晶面あるいは（０００−１）結晶面から約１〜９度の範囲でオフカットされたものを使用する。このＳｉＣ単結晶基板１をＣＶＤ装置の反応容器（リアクタ）内に設置する。ＳｉＣエピタキシャル膜２を成膜する条件としては、反応容器内にシランガスとプロパンガスをキャリアガスである水素と共に導入し、反応容器を１４００〜１７００℃の範囲で、圧力は１０〜１０００ｍｂａｒの範囲で保つことによって、ＳｉＣ単結晶基板１上にＳｉＣエピタキシャル膜２を成膜する。また、シランガスおよびプロパンガスの流量は前記水素の流量の１００〜１００００分の１の流量とするのが好ましい。この条件で成膜されるＳｉＣエピタキシャル膜２の表面粗さＲａは１．０ｎｍ未満であり、ＳｉＣエピタキシャル膜２の成膜中に新たな転位など致命的な欠陥が誘発されることを防止することができる。   A more detailed description of each step is described below. FIG. 1 a shows a film forming process of forming an SiC epitaxial film 2 on an off-cut SiC single crystal substrate 1. As the SiC single crystal substrate 1, a substrate that is off-cut within a range of about 1 to 9 degrees from the (0001) crystal plane or the (000-1) crystal plane is used. This SiC single crystal substrate 1 is placed in a reaction vessel (reactor) of a CVD apparatus. The conditions for forming the SiC epitaxial film 2 are that silane gas and propane gas are introduced into the reaction vessel together with hydrogen as the carrier gas, and the reaction vessel is kept in the range of 1400 to 1700 ° C. and the pressure is kept in the range of 10 to 1000 mbar. Thereby, SiC epitaxial film 2 is formed on SiC single crystal substrate 1. Moreover, it is preferable that the flow rate of silane gas and propane gas is set to a flow rate of 100 to 10000 times the flow rate of the hydrogen. The surface roughness Ra of the SiC epitaxial film 2 formed under these conditions is less than 1.0 nm, and a fatal defect such as a new dislocation is prevented from being induced during the formation of the SiC epitaxial film 2. Can do.

図１ｂは、ＳｉＣエピタキシャル膜２を加熱することでＳｉＣエピタキシャル膜２の表面に表面粗さＲａが１ｎｍ以上のステップバンチングを発生させてＳｉＣエピタキシャル膜２中の欠陥を修復して結晶品質を改善させる加熱工程である。この加熱条件としては、１６００〜２０００℃の範囲が好ましい。上限を２０００℃とした理由としてはＳｉＣが昇華し始める温度であるためである。また、ステップバンチング３をより効果的に発生させるためには、成膜時の圧力よりも減圧状態にすることで原子を表面拡散しやすくすることができるため、より効果的にステップバンチング３を発生することが可能である。また、成膜時の圧力よりも減圧状態にすることでより加熱温度を下げることが可能となる。また、加熱時のガス雰囲気は、成膜工程でキャリアガスとして使用する水素をそのまま流し続けて水素雰囲気中で加熱しても良いが、またアルゴンやヘリウムといった不活性ガス雰囲気中で加熱しても良い。不活性雰囲気中であれば、ＳｉＣエピタキシャル膜２がガスエッチングされて膜厚が減少してしまうことを防止することができる。   In FIG. 1b, by heating the SiC epitaxial film 2, step bunching having a surface roughness Ra of 1 nm or more is generated on the surface of the SiC epitaxial film 2 to repair defects in the SiC epitaxial film 2 and improve crystal quality. It is a heating process. As this heating condition, the range of 1600-2000 degreeC is preferable. The reason why the upper limit is set to 2000 ° C. is that SiC is a temperature at which sublimation starts. Further, in order to generate the step bunching 3 more effectively, the atoms can be easily diffused to the surface by reducing the pressure than the pressure at the time of film formation, so the step bunching 3 is generated more effectively. Is possible. In addition, the heating temperature can be further lowered by reducing the pressure to a pressure lower than the pressure at the time of film formation. In addition, the gas atmosphere during heating may be heated in a hydrogen atmosphere by continuously flowing hydrogen used as a carrier gas in the film forming process, or may be heated in an inert gas atmosphere such as argon or helium. good. If it is in an inert atmosphere, it can prevent that the SiC epitaxial film 2 is gas-etched and the film thickness decreases.

加熱工程におけて欠陥が減少するメカニズムとしては、ＳｉＣエピタキシャル膜２に多数存在する原子空孔４や格子間原子５を熱エネルギーによって移動させることで原子空孔４と格子間原子５とを再結合させたり転位に吸収させたりすることで消滅させることができる。さらに、オフ角を有するＳｉＣ単結晶基板１を使用した場合においては、最適な加熱処理を行うことによってＳｉＣエピタキシャル膜２の表面に数〜数十ｎｍ程度のステップバンチング３を形成させることが可能であり、ＳｉＣエピタキシャル膜２の表面近傍の点欠陥はおろか、ＳｉＣエピタキシャル膜２の表面近傍で発生した転位６についても修復することが可能である。つまり、ステップバンチング３の発生過程においてＳｉＣエピタキシャル膜２の表面近傍の原子が非常に盛んに表面拡散（マイグレーション）して結晶構造を再配列化していくことからエピ表面近傍の点欠陥や転位６がより効果的に消滅していくものと推測される。以上のことから、この加熱工程においては、ＳｉＣエピタキシャル膜２の表面にステップバンチング３を発生させることによりが、結晶品質を効果的に改善させる上で重要である。   As a mechanism for reducing defects in the heating process, the atomic vacancies 4 and the interstitial atoms 5 are regenerated by moving the atomic vacancies 4 and interstitial atoms 5 existing in the SiC epitaxial film 2 by thermal energy. It can be extinguished by bonding or absorbing it by dislocations. Furthermore, when the SiC single crystal substrate 1 having an off angle is used, it is possible to form a step bunching 3 of about several to several tens of nm on the surface of the SiC epitaxial film 2 by performing an optimum heat treatment. In addition, not only point defects near the surface of the SiC epitaxial film 2 but also dislocations 6 generated near the surface of the SiC epitaxial film 2 can be repaired. That is, in the process of generating the step bunching 3, atoms near the surface of the SiC epitaxial film 2 are very actively diffused (migration), and the crystal structure is rearranged. Therefore, point defects and dislocations 6 near the epi surface are generated. It is estimated that it will disappear more effectively. From the above, in this heating step, generating step bunching 3 on the surface of the SiC epitaxial film 2 is important for effectively improving the crystal quality.

また、成膜工程と加熱工程は、ＣＶＤ装置を用いて連続的に実施することが好ましい。連続的に実施することによる効果として、別途アニール装置で加熱処理を行う必要がないため生産性を向上することができる。さらには、昇温過程や降温過程といった急激な熱ストレスが加わる処理が一度で済むために単結晶基板の反りや割れなどといったリスクも軽減することができる。さらには、装置間での基板移動がないため不純物付着を防止することができる。   Further, it is preferable that the film forming process and the heating process are continuously performed using a CVD apparatus. As an effect of continuous implementation, productivity can be improved because there is no need to perform a heat treatment with a separate annealing apparatus. Furthermore, since the process of applying a rapid thermal stress such as a temperature rising process or a temperature falling process is only required once, the risk of warping or cracking of the single crystal substrate can be reduced. Furthermore, since there is no movement of the substrate between apparatuses, it is possible to prevent the adhesion of impurities.

図１ｃは、ＳｉＣエピタキシャル膜２の表面に発生させたステップバンチング３をＣＭＰ（化学的機械研磨）により除去する平坦化工程である。ＣＭＰによる研磨量は数十ｎｍ程度で良い。この工程はデバイスを製造する場合において、ＳｉＣエピタキシャル膜２のステップバンチング３がデバイス特性に悪影響を与える場合において適宜実施すればよい。具体的にはＭＯＳＦＥＴを製造する場合においては、ステップバンチング３が存在するとベース下のキャリアの移動を阻害しデバイス特性に悪影響を及ぼすことがある。平坦化処理の方法として、ＣＭＰ以外にも水素雰囲気中のガスエッチングや水素と塩素の混合ガスなどによるガスエッチング処理を用いても良い。   FIG. 1 c shows a planarization process in which the step bunching 3 generated on the surface of the SiC epitaxial film 2 is removed by CMP (chemical mechanical polishing). The polishing amount by CMP may be about several tens of nm. This process may be appropriately performed when manufacturing a device and the step bunching 3 of the SiC epitaxial film 2 adversely affects the device characteristics. Specifically, in the case of manufacturing a MOSFET, if the step bunching 3 exists, the movement of carriers under the base may be hindered to adversely affect device characteristics. As a planarization treatment method, gas etching treatment in a hydrogen atmosphere or a mixed gas of hydrogen and chlorine may be used in addition to CMP.

以下、本発明のＳｉＣエピタキシャル膜付き単結晶基板の製造法を用いたＳｉＣエピタキシャル膜の成膜方法を具体的に説明する。本実施の形態では、ＳｉＣエピタキシャル膜２の成膜工程と加熱工程とをＣＶＤ装置を用いて連続的に実施し、次いでＣＭＰによりステップバンチングの平坦化処理を行った。   Hereinafter, a method for forming an SiC epitaxial film using the method for producing a single crystal substrate with an SiC epitaxial film according to the present invention will be specifically described. In the present embodiment, the step of forming the SiC epitaxial film 2 and the heating step are continuously performed using a CVD apparatus, and then step bunching planarization is performed by CMP.

図２はＣＶＤ装置のエピタキシャル成長レシピを示したグラフである。Ｘ軸を時間とし、Ｙ軸をＣＶＤ装置のリアクタの温度および圧力で表したグラフである。また、ガス導入タイミングについてもグラフ下に示してある。使用した基板として、８度オフ（０００１）４Ｈ−ＳｉＣ単結晶基板を使用した。   FIG. 2 is a graph showing an epitaxial growth recipe of the CVD apparatus. It is a graph in which the X-axis is time and the Y-axis is the temperature and pressure of the reactor of the CVD apparatus. The gas introduction timing is also shown below the graph. As the substrate used, an 8-degree off (0001) 4H—SiC single crystal substrate was used.

成膜工程として、シラン（ＳｉＨ４）およびプロパン（Ｃ３Ｈ８）を水素（Ｈ２）と共にリアクタに導入しながら、リアクタ温度を１６５０℃、リアクタ圧力を０．８ｂａｒとし、ＳｉＣエピタキシャル膜２の成膜を１．５時間行った。また、この時のシラン、プロパン、水素の流量は、それぞれ２５ｃｃ／ｍｉｎ、２０ｃｃ／ｍｉｎ、５０Ｌ／ｍｉｎであり、成長速度は約５μｍ／ｈｒである。図４に、成膜工程直後のエピタキシャル膜表面のＡＦＭ（原子間力顕微鏡）の測定結果を示す。このＡＦＭの測定結果より、５μｍ×５μｍエリアの表面粗さＲａは約０．３ｎｍであった。 As a film forming process, while introducing silane (SiH 4 ) and propane (C 3 H 8 ) into the reactor together with hydrogen (H 2 ), the reactor temperature was set to 1650 ° C., the reactor pressure was set to 0.8 bar, and the SiC epitaxial film 2 Film formation was performed for 1.5 hours. At this time, the flow rates of silane, propane, and hydrogen are 25 cc / min, 20 cc / min, and 50 L / min, respectively, and the growth rate is about 5 μm / hr. FIG. 4 shows a measurement result of an AFM (atomic force microscope) on the surface of the epitaxial film immediately after the film forming process. From this AFM measurement result, the surface roughness Ra in the 5 μm × 5 μm area was about 0.3 nm.

次に、このＳｉＣエピタキシャル膜２にステップバンチング３を発生させる加熱工程として、シランとプロパンと水素の導入を停止し、アルゴンガスを５０Ｌ／ｍｉｎの流量でリアクタに導入しながら、リアクタ温度を１７００℃、リアクタ圧力を０．１ｂａｒとして、加熱を１時間行った。図５に、加熱工程後のエピタキシャル膜の表面のＡＦＭの測定結果を示す。５μｍ×５μｍエリアの表面粗さＲａは約４ｎｍであり、大きなステップバンチングが発生させることができている。   Next, as a heating process for generating the step bunching 3 in the SiC epitaxial film 2, the introduction of silane, propane and hydrogen is stopped, and the reactor temperature is set to 1700 ° C. while introducing argon gas into the reactor at a flow rate of 50 L / min. The reactor pressure was 0.1 bar and heating was performed for 1 hour. FIG. 5 shows the measurement results of AFM on the surface of the epitaxial film after the heating step. The surface roughness Ra of the 5 μm × 5 μm area is about 4 nm, and large step bunching can be generated.

続いて、ＣＶＤ装置からこのＳｉＣエピタキシャル膜２付き単結晶基板１を取出し、ＳｉＣエピタキシャル膜２表面のステップバンチング３をＣＭＰにより平坦化させた。この時の研磨量は約５０ｎｍとした。図５に、ＣＭＰ後のエピタキシャル膜の表面のＡＦＭの測定結果を示す。５μｍ×５μｍエリアの表面粗さＲａは約０．１ｎｍであった。また、ＣＭＰの以外の平坦化処理の方法として、図３に示すようにＣＶＤ装置での加熱工程に引き続いて、水素雰囲気中でのガスエッチングによる平坦化工程を連続的に行っても良い。   Subsequently, the single crystal substrate 1 with the SiC epitaxial film 2 was taken out from the CVD apparatus, and the step bunching 3 on the surface of the SiC epitaxial film 2 was planarized by CMP. The polishing amount at this time was about 50 nm. FIG. 5 shows the AFM measurement result of the surface of the epitaxial film after CMP. The surface roughness Ra of the 5 μm × 5 μm area was about 0.1 nm. As a planarization process other than CMP, as shown in FIG. 3, a planarization process by gas etching in a hydrogen atmosphere may be continuously performed following the heating process in the CVD apparatus.

次に、ＳｉＣエピタキシャル膜２中の結晶欠陥の減少の効果を確認するため、ＭＯＳキャパシタを作製して絶縁破壊試験を行うことした。このＭＯＳキャパシタの製造方法および構造としては、ＳｉＣエピタキシャル膜付き単結晶基板を酸素雰囲気中において約１１００℃で加熱処理を行い、ＳｉＣエピタキシャル膜を酸化させることで表面に約５０ｎｍの熱酸化膜を形成した。さらに、この熱酸化膜上にＡｌ電極を形成し、基板裏面にはＮｉ電極を形成して、ＭＯＳキャパシタを作製した。なお、作製したＭＯＳキャパシタの寸法（Ａｌ電極のサイズ）は１ｍｍ2である。 Next, in order to confirm the effect of reducing crystal defects in the SiC epitaxial film 2, a MOS capacitor was produced and a dielectric breakdown test was performed. As a manufacturing method and structure of this MOS capacitor, a single crystal substrate with an SiC epitaxial film is heated at about 1100 ° C. in an oxygen atmosphere to oxidize the SiC epitaxial film to form a thermal oxide film of about 50 nm on the surface. did. Further, an Al electrode was formed on the thermal oxide film, and a Ni electrode was formed on the back surface of the substrate to produce a MOS capacitor. The dimension of the fabricated MOS capacitor (Al electrode size) is 1 mm 2 .

絶縁破壊試験の方法として、ＭＯＳキャパシタに一定のリーク電流密度Ｊ＝１００μＡを印加し、ＭＯＳキャパシタが絶縁破壊されるまでの時間ｔを測定することにより、絶縁破壊電荷ＱｂｄをＪ×ｔの計算により求めたることとした。なお、試験点数は１２個とした。また、絶縁破壊箇所は熱酸化膜となる。   As a method of the dielectric breakdown test, a constant leakage current density J = 100 μA is applied to the MOS capacitor, and the time t until the MOS capacitor is broken down is measured, whereby the breakdown charge Qbd is calculated by J × t. I decided to ask for it. The number of test points was 12. Moreover, the dielectric breakdown part becomes a thermal oxide film.

以上の評価方法によりＭＯＳキャパシタ絶縁破壊試験を実施し得られた絶縁破壊電荷Ｑｂｄの結果のワイブルプロットを図７に示した。Ｘ軸は絶縁破壊電荷Ｑｂｄであり、Ｙ軸のＦは累積故障率である。また、比較として、従来として加熱処理を行わないＳｉＣエピタキシャル膜付きＳｉＣ基板を使用して作製したＭＯＳキャパシタと、本発明のＳｉＣエピタキシャル付きＳｉＣ単結晶基板を使用して作製したＭＯＳキャパシタの比較を行った。この図７より、本発明のＭＯＳキャパシタのＱｂｄが従来のＭＯＳキャパシタと比較して１桁程度大きいことがわかる。ＭＯＳキャパシタの熱酸化膜はエピタキシャル膜から変換されているものであるから、エピタキシャル膜の結晶欠陥は熱酸化膜中に取り込まれることとなる。よって、ＭＯＳキャパシタの絶縁破壊電荷が大きくなるということは、ＳｉＣエピタキシャル膜中の結晶欠陥が少ない低くなるというわけである。このことから、本発明のＳｉＣエピタキシャル膜２中の結晶欠陥が大きく減少していることがわかる。   FIG. 7 shows a Weibull plot of the result of the dielectric breakdown charge Qbd obtained by conducting the MOS capacitor dielectric breakdown test by the above evaluation method. The X axis is the dielectric breakdown charge Qbd, and the Y axis F is the cumulative failure rate. As a comparison, a comparison was made between a MOS capacitor manufactured using a SiC substrate with an SiC epitaxial film that was not subjected to heat treatment and a MOS capacitor manufactured using an SiC single crystal substrate with an SiC epitaxial according to the present invention. It was. FIG. 7 shows that the Qbd of the MOS capacitor of the present invention is about one digit larger than that of the conventional MOS capacitor. Since the thermal oxide film of the MOS capacitor is converted from the epitaxial film, crystal defects of the epitaxial film are taken into the thermal oxide film. Therefore, an increase in the dielectric breakdown charge of the MOS capacitor means that the number of crystal defects in the SiC epitaxial film is reduced. This shows that crystal defects in the SiC epitaxial film 2 of the present invention are greatly reduced.

本発明にかかるＳｉＣエピタキシャル膜付き単結晶基板の製造方法は、ＳｉＣエピタキシャル膜中の結晶欠陥を効果的に減少させ、結晶品質に優れたＳｉＣエピタキシャル膜付き単結晶基板を製造することができる。特に、ＳｉＣエピタキシャル膜の表面近傍の結晶欠陥の減少により効果的であることから、エピタキシャル膜表面近傍の結晶品質が重要なＭＯＳＦＥＴ、ＭＩＳＦＥＴ、ＭＥＳＦＥＴ、ショットキーダイオード等のデバイス用途として有用である。   The method for producing a single crystal substrate with an SiC epitaxial film according to the present invention can effectively reduce crystal defects in the SiC epitaxial film and produce a single crystal substrate with an SiC epitaxial film having excellent crystal quality. In particular, since it is effective by reducing crystal defects near the surface of the SiC epitaxial film, it is useful for device applications such as MOSFETs, MISFETs, MESFETs, and Schottky diodes where crystal quality near the epitaxial film surface is important.

本発明における工程フローの概略図Schematic of process flow in the present invention 本発明の実施の形態１における成膜工程と加熱工程とをＣＶＤ装置を用いて連続的に実施した時のエピタキシャル成長レシピを表した図The figure showing the epitaxial growth recipe when the film-forming process and heating process in Embodiment 1 of this invention are implemented continuously using a CVD apparatus 本発明の実施の形態１における成膜工程と加熱工程と平坦化工程とをＣＶＤ装置を用いて連続的に実施した時のエピタキシャル成長レシピを表した図The figure showing the epitaxial growth recipe when the film-forming process, heating process, and planarization process in Embodiment 1 of this invention are continuously implemented using a CVD apparatus. 本発明の実施の形態１における成膜工程直後のエピタキシャル膜表面のＡＦＭの測定結果を示す図The figure which shows the measurement result of AFM of the epitaxial film surface immediately after the film-forming process in Embodiment 1 of this invention 本発明の実施の形態１における加熱工程直後のエピタキシャル膜表面のＡＦＭの測定結果を示す図The figure which shows the measurement result of AFM of the epitaxial film surface immediately after the heating process in Embodiment 1 of this invention 本発明の実施の形態１におけるＣＭＰ後のエピタキシャル膜表面のＡＦＭの測定結果を示す図The figure which shows the measurement result of AFM of the epitaxial film surface after CMP in Embodiment 1 of this invention 本発明の実施の形態１におけるＭＯＳキャパシタを用いて実施した経時絶縁破壊試験の結果を示す図The figure which shows the result of the time-dependent dielectric breakdown test implemented using the MOS capacitor in Embodiment 1 of this invention

符号の説明Explanation of symbols

１ ＳｉＣ単結晶基板
２ ＳｉＣエピタキシャル膜
３ ステップバンチング
４ 原子空孔
５ 格子間原子
６ 転位 1 SiC single crystal substrate 2 SiC epitaxial film 3 Step bunching 4 Atomic vacancy 5 Interstitial atom 6 Dislocation

Claims (7)

オフ角を有するＳｉＣ単結晶基板が設置されている反応容器内に珪化水素ガスおよび炭化水素ガスを水素と共に導入しながら第１の温度で且つ第１の圧力で加熱することによりＳｉＣエピタキシャル膜を成膜する第１の工程と、
第２の温度で前記ＳｉＣエピタキシャル膜の表面粗さＲａが１ｎｍ以上になるまで加熱を行う第２の工程と、
を含むＳｉＣエピタキシャル膜付き単結晶基板の製造方法。 A SiC epitaxial film is formed by heating at a first temperature and a first pressure while introducing hydrogen silicide gas and hydrocarbon gas together with hydrogen into a reaction vessel in which a SiC single crystal substrate having an off-angle is installed. A first step of filming;
A second step of heating at a second temperature until the surface roughness Ra of the SiC epitaxial film becomes 1 nm or more;
Of manufacturing a single crystal substrate with a SiC epitaxial film. オフ角を有するＳｉＣ単結晶基板が設置されている反応容器内に珪化水素ガスおよび炭化水素ガスを水素と共に導入しながら第１の温度で且つ第１の圧力で加熱することによりＳｉＣエピタキシャル膜を成膜する第１の工程と、
第２の温度で且つ前記第１の圧力以下で前記ＳｉＣエピタキシャル膜の表面粗さＲａが１ｎｍ以上になるまで加熱を行う第２の工程と、
を含むＳｉＣエピタキシャル膜付き単結晶基板の製造方法。 A SiC epitaxial film is formed by heating at a first temperature and a first pressure while introducing hydrogen silicide gas and hydrocarbon gas together with hydrogen into a reaction vessel in which a SiC single crystal substrate having an off-angle is installed. A first step of filming;
A second step of heating at a second temperature and not more than the first pressure until the surface roughness Ra of the SiC epitaxial film becomes 1 nm or more;
Of manufacturing a single crystal substrate with a SiC epitaxial film. 前記オフ角を有するＳｉＣ単結晶基板は、六方晶系の結晶構造を有し、（０００１）面もしくは（０００−１）面から１〜９度傾いた面を有するＳｉＣ単結晶基板である請求項１および２に記載のＳｉＣエピタキシャル膜付き単結晶基板の製造方法。   The SiC single crystal substrate having an off angle is a SiC single crystal substrate having a hexagonal crystal structure and having a plane inclined by 1 to 9 degrees from a (0001) plane or a (000-1) plane. A method for producing a single crystal substrate with an SiC epitaxial film according to 1 and 2. 前記第１の温度は１４００〜１７００℃の範囲であり、前記第１の圧力は１０〜１０００ｍｂａｒの範囲とした、請求項１および２に記載のＳｉＣエピタキシャル膜付き単結晶基板の製造方法。 3. The method for manufacturing a single crystal substrate with an SiC epitaxial film according to claim 1, wherein the first temperature is in a range of 1400 to 1700 ° C., and the first pressure is in a range of 10 to 1000 mbar. 前記第２の温度は１６００〜２０００℃の範囲とした、請求項１および２に記載のＳｉＣエピタキシャル膜付き単結晶基板の製造方法。 3. The method for manufacturing a single crystal substrate with an SiC epitaxial film according to claim 1, wherein the second temperature is in a range of 1600 to 2000 ° C. 4. 前記第２の工程の後に、前記ＳｉＣエピタキシャル膜の表面を平均表面粗さＲａが０．５ｎｍ未満となるまで平坦化処理する第３の工程を持つ、請求項１および２に記載のＳｉＣエピタキシャル膜付き単結晶基板の製造方法。   3. The SiC epitaxial film according to claim 1, further comprising a third step of planarizing the surface of the SiC epitaxial film until an average surface roughness Ra is less than 0.5 nm after the second step. 4. For manufacturing a single crystal substrate with a substrate. 前記第３の工程は、水素を含む気体によるドライエッチングを用いて前記ＳｉＣエピタキシャル膜の表面を研磨する、請求項６に記載のＳｉＣエピタキシャル膜付き単結晶基板の製造方法。   The method of manufacturing a single crystal substrate with an SiC epitaxial film according to claim 6, wherein the third step polishes the surface of the SiC epitaxial film using dry etching with a gas containing hydrogen.
JP2007064765A 2007-03-14 2007-03-14 METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM Pending JP2008222509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007064765A JP2008222509A (en) 2007-03-14 2007-03-14 METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007064765A JP2008222509A (en) 2007-03-14 2007-03-14 METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM

Publications (1)

Publication Number Publication Date
JP2008222509A true JP2008222509A (en) 2008-09-25

Family

ID=39841551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007064765A Pending JP2008222509A (en) 2007-03-14 2007-03-14 METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM

Country Status (1)

Country Link
JP (1) JP2008222509A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4719314B2 (en) * 2009-01-30 2011-07-06 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP2013139622A (en) * 2011-12-29 2013-07-18 Tokai Carbon Korea Co Ltd Silicon carbide structure and method for producing the same
US8569106B2 (en) 2009-03-05 2013-10-29 Mitsubishi Electric Corporation Method for manufacturing silicon carbide semiconductor device
WO2013180483A1 (en) * 2012-05-30 2013-12-05 엘지이노텍 주식회사 Silicon carbide epiwafer and method for manufacturing same
WO2014157332A1 (en) * 2013-03-27 2014-10-02 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor substrate
WO2016125404A1 (en) * 2015-02-02 2016-08-11 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
KR20170099958A (en) 2015-02-18 2017-09-01 신닛테츠스미킨 카부시키카이샤 Method for producing silicon carbide single crystal ingot and silicon carbide single crystal ingot
EP2472568B1 (en) * 2009-08-28 2022-01-12 Showa Denko K.K. Silicon carbide epitaxial wafer and manufacturing method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234301A (en) * 2001-10-25 2003-08-22 Matsushita Electric Ind Co Ltd Semiconductor substrate, semiconductor element and method for manufacturing the same
JP2005277229A (en) * 2004-03-25 2005-10-06 National Institute Of Advanced Industrial & Technology Manufacturing method of silicon carbide smoothed substrate, silicon carbide smoothed substrate, silicon carbide epitaxial wafer, gallium nitride wafer, and semiconductor manufacturing device
JP2008053343A (en) * 2006-08-23 2008-03-06 Hitachi Metals Ltd Method for manufacturing silicon carbide semiconductor epitaxial substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234301A (en) * 2001-10-25 2003-08-22 Matsushita Electric Ind Co Ltd Semiconductor substrate, semiconductor element and method for manufacturing the same
JP2005277229A (en) * 2004-03-25 2005-10-06 National Institute Of Advanced Industrial & Technology Manufacturing method of silicon carbide smoothed substrate, silicon carbide smoothed substrate, silicon carbide epitaxial wafer, gallium nitride wafer, and semiconductor manufacturing device
JP2008053343A (en) * 2006-08-23 2008-03-06 Hitachi Metals Ltd Method for manufacturing silicon carbide semiconductor epitaxial substrate

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102301043A (en) * 2009-01-30 2011-12-28 新日本制铁株式会社 Epitaxial silicon carbide single crystal substrate and mehtod for producing same
JPWO2010087518A1 (en) * 2009-01-30 2012-08-02 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP4719314B2 (en) * 2009-01-30 2011-07-06 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
US8569106B2 (en) 2009-03-05 2013-10-29 Mitsubishi Electric Corporation Method for manufacturing silicon carbide semiconductor device
JP5393772B2 (en) * 2009-03-05 2014-01-22 三菱電機株式会社 Method for manufacturing silicon carbide semiconductor device
EP2472568B1 (en) * 2009-08-28 2022-01-12 Showa Denko K.K. Silicon carbide epitaxial wafer and manufacturing method therefor
JP2013139622A (en) * 2011-12-29 2013-07-18 Tokai Carbon Korea Co Ltd Silicon carbide structure and method for producing the same
CN104428872A (en) * 2012-05-30 2015-03-18 Lg伊诺特有限公司 Silicon carbide epiwafer and method for manufacturing same
WO2013180483A1 (en) * 2012-05-30 2013-12-05 엘지이노텍 주식회사 Silicon carbide epiwafer and method for manufacturing same
JP2014189442A (en) * 2013-03-27 2014-10-06 Sumitomo Electric Ind Ltd Production method of silicon carbide semiconductor substrate
US9269572B2 (en) 2013-03-27 2016-02-23 Sumitomo Electric Industries, Ltd. Method for manufacturing silicon carbide semiconductor substrate
WO2014157332A1 (en) * 2013-03-27 2014-10-02 住友電気工業株式会社 Method for manufacturing silicon carbide semiconductor substrate
WO2016125404A1 (en) * 2015-02-02 2016-08-11 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
CN106536793A (en) * 2015-02-02 2017-03-22 富士电机株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
JPWO2016125404A1 (en) * 2015-02-02 2017-04-27 富士電機株式会社 Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device
US10208400B2 (en) 2015-02-02 2019-02-19 Fuji Electric Co., Ltd. Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
DE112015002906B4 (en) 2015-02-02 2022-12-22 Fuji Electric Co., Ltd. Method of manufacturing a silicon carbide semiconductor device and silicon carbide semiconductor device
KR20170099958A (en) 2015-02-18 2017-09-01 신닛테츠스미킨 카부시키카이샤 Method for producing silicon carbide single crystal ingot and silicon carbide single crystal ingot
US10066316B2 (en) 2015-02-18 2018-09-04 Showa Denko K.K. Method for producing silicon carbide single-crystal ingot and silicon carbide single-crystal ingot

Similar Documents

Publication Publication Date Title
JP4987792B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
US9957638B2 (en) Method for manufacturing silicon carbide semiconductor device
KR101412227B1 (en) Silicon carbide epitaxial wafer and process for production thereof, silicon carbide bulk substrate for epitaxial growth purposes and process for production thereof, and heat treatment apparatus
KR101333337B1 (en) Epitaxial silicon carbide single crystal substrate and method for producing same
JP2008222509A (en) METHOD FOR PRODUCING SINGLE CRYSTAL SUBSTRATE WITH SiC EPITAXIAL FILM
KR102106722B1 (en) Method for manufacturing epitaxial silicon carbide single crystal wafer
JP4946264B2 (en) Method for manufacturing silicon carbide semiconductor epitaxial substrate
JP2008311541A (en) Manufacturing method of silicon carbide semiconductor substrate
JP2013014469A (en) Sic epitaxial substrate and method for manufacturing the same
JP7211456B2 (en) Silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
US11114295B2 (en) Epitaxial silicon carbide single crystal wafer and process for producing the same
JP2009149481A (en) Method for manufacturing semiconductor substrate
JP3557457B2 (en) Method for manufacturing SiC film and method for manufacturing SiC multilayer film structure
KR20170015497A (en) Method for producing epitaxial silicon carbide wafers
JP5786759B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP4511378B2 (en) Method for forming single crystal SiC layer using SOI substrate
JP2022020995A (en) Manufacturing method of silicon carbide epitaxial wafer
CN111799321A (en) Silicon carbide epitaxial wafer, method for producing silicon carbide epitaxial wafer, and power conversion device
JP2011023502A (en) Silicon carbide semiconductor device, method of manufacturing the same, and method of manufacturing silicon carbide epitaxial substrate
JP2018067736A (en) Silicon carbide semiconductor device and method of manufacturing the same
JP2010225734A (en) Method of manufacturing semiconductor substrate
JP2009302097A (en) Method of manufacturing single crystal sic substrate, and single crystal sic substrate
JP2010098045A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100310

RD01 Notification of change of attorney

Effective date: 20100413

Free format text: JAPANESE INTERMEDIATE CODE: A7421

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110809

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111206