JP2008220158A - Booster circuit - Google Patents

Abstract

The voltage limit of a charge transfer transistor is relaxed in a booster circuit.
When clock signals CLK1 and CLK2 are at a high level and a low level, respectively, voltages V11m, V11n, V12m, and V12n are Vdd + α · Vdd, Vdd, Vdd + α · Vdd, Vdd + 2α · Vdd, respectively. As a result, in the boost stage 12m, the on-switch transistor 103 becomes conductive, and the charge transfer transistor 101 transfers charge. On the other hand, in the boosting stage 12n, the off switch transistor 102 is turned on, and the charge transfer transistor 101 is turned off. At this time, the gate-source potential difference and the gate-drain potential difference of the charge transfer transistor 101 are “α · Vdd”.
[Selection] Figure 2

Description

  The present invention relates to a booster circuit.

  In recent years, flash memory, which is a non-volatile storage device, has been required to read / rewrite data with a single power supply voltage or a low power supply voltage. In order to perform each operation, a boosted voltage or a negative boosted voltage is required. There is a need for a boost circuit to supply.

  In US Pat. No. 5,422,586 (Patent Document 1), a boosting voltage is generated by inputting four clock signals CLK1, CLK2, CLK3, and CLK4 having different phases and performing a boosting operation. A circuit is disclosed. However, in this booster circuit, it is necessary to increase the clock margin sufficiently in order to appropriately switch the four different clocks, or the clock control is complicated, so it is difficult to increase the clock frequency. .

  US Pat. No. 4,214,174 (Patent Document 2) discloses a booster circuit that generates a boosted voltage by inputting two clock signals CLK1 and CLK2 having different phases and performing a boosting operation. ing. However, since the transistor for transferring charge is a diode connection type, there is a problem that charge transfer efficiency is lowered.

  In order to solve the above problems, IEEE_JOURNAL_OF_SOLID-STATE_CIRCUITS_VOL33_NO.4_APRIL_1998 (Non-Patent Document 1) discloses the following booster circuit.

  FIG. 36 shows the configuration of the booster circuit disclosed in Non-Patent Document 1. The booster circuit 9 generates a boosted voltage Vpump by inputting two clock signals CLK1 and CLK2 having different phases and performing a boosting operation. The booster circuit 9 includes booster cells 91, 92, 93, 94, a sub booster cell 95, and a backflow prevention circuit 96. Clock signal CLK1 is input to booster cells 91 and 93 (odd-numbered booster cells), and clock signal CLK2 is input to booster cells 92 and 94 (even-numbered booster cells). The sub booster cell 95 controls the booster cell 94 at the final stage. The backflow prevention circuit 96 prevents backflow of the boosted voltage Vpump.

  Boosting cells 91, 92, 93, 94 each include a charge transfer transistor 901, an off switch transistor 902, an on switch transistor 903, and a boosting capacitor 904. The off switch transistor 902 included in each of the boosting cells 91, 92, 93, 94 equalizes the gate potentials of the input / output terminals N91, N92, N93, N94 and the charge transfer transistor 901 to turn off the charge transfer transistor 901. Put it in a state. The on-switch transistor 903 turns on the charge transfer transistor 901. The booster capacitor 904 is pumped in synchronization with the clock signal CLK1 (or CLK2). The sub boosting capacitor 905 is pumped in synchronization with the clock signal CLK1, and turns on the charge transfer transistor 901 of the boosting cell 94 in the final stage. The diode-connected transistor 906 transmits a voltage lower than the voltage of the input / output terminal N96 by a threshold voltage to the sub boost capacitor 905. The sub input terminal N95 is connected to one end of the sub boosting capacitor 905, and is connected to the diode connection transistor 906 and the boosting cell 94 in the final stage.

  Next, the operation of the booster circuit shown in FIG. 36 will be briefly described with reference to FIG. First, at time T1, the clock signal CLK1 becomes high level, and the input / output terminals N92 and N94 and the sub input terminal N95 are boosted. As a result, in the boosting cells 91 and 93, the off switch transistor 902 is turned on and the charge transfer transistor 901 is turned off. On the other hand, when the clock signal CLK2 becomes low level and the voltages at the input / output terminals N93 and N96 are stepped down, in the boosting cells 92 and 94, the on-switch transistor 903 becomes conductive, and the charge transfer transistor 901 becomes conductive. Become. As a result, charges are transferred from the input / output terminals N92 to N93, charges are transferred from the input / output terminals N94 to N96, and the input / output terminals N93 and N96 rise.

  Next, at time T2, the clock signal CLK2 becomes high level, and the voltages of the input / output terminals N93 and N96 are boosted. As a result, in the boosting cells 92 and 94, the off switch transistor 902 is turned on and the charge transfer transistor 901 is turned off. On the other hand, when the clock signal CLK1 becomes low level and the voltages of the input / output terminals N92 and N94 and the sub input terminal N95 are stepped down, the on-switch transistor 903 becomes conductive in the boosting cells 91 and 93, and the charge transfer transistor. 901 becomes conductive. As a result, charges are transferred from the input / output terminals N91 to N92, and charges are transferred from the input / output terminals N93 to N94, increasing the voltages at the input / output terminals N92 and N94. Further, when the voltage at the input / output terminal N96 is boosted, charges are transferred to the output of the booster circuit 94 via the backflow prevention circuit 96, and the boosted voltage Vpump increases. Next, at time T3, an operation similar to that at time T1 is performed.

In this booster circuit, it is possible to ensure a long charge transfer time by simultaneously performing the boosting operation and the charge transfer operation in the boosting cells 91 to 94. In addition, control of the clock signal is easy. Furthermore, by controlling the gate potential of the charge transfer transistor 901 that performs the charge transfer operation, a decrease in charge transfer efficiency can be suppressed.
US Pat. No. 5,422,586 U.S. Pat. No. 4,214,174 IEEE_JOURNAL_OF_SOLID-STATE_CIRCUITS_VOL33_NO.4_APRIL_1998

  However, in the booster circuit disclosed in Non-Patent Document 1, when the charge transfer transistor is controlled to be conductive in each booster cell, the output voltage of the booster cell in the next stage is used. It was. For example, when the charge transfer transistor is set in a non-conductive state, the off switch transistor is in a conductive state, so that the potential difference between the gate and the drain of the charge transfer transistor is “2 · Vdd”. Therefore, it is necessary to increase the breakdown voltage of the charge transfer transistor.

  Furthermore, although the booster circuit disclosed in Non-Patent Document 1 can suppress a decrease in charge transfer efficiency in the booster cell as compared with the booster circuit of Patent Document 2, it is diode-connected in the backflow prevention circuit connected to the final stage of the booster circuit. As a result, there is a problem that the charge transfer efficiency is lowered.

  In view of the above, an object of the present invention is to provide a booster circuit capable of relaxing the withstand voltage limitation of the charge transfer transistor.

  According to one aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate in a complementary manner, and includes a plurality of cascaded connections. A plurality of boosting stages each including a boosting stage, each of the plurality of boosting stages having an input node and an output node, and boosting in response to one of the first and second clock signals; The first boosting stage, which is one of the plurality of boosting stages, operates and includes a charge transfer transistor connected between the input node and the output node, and one end connected to the output node. A boost capacitor that receives the clock signal corresponding to the first boost stage at the other end, and an output node of the boost stage corresponding to the same clock signal as the first boost stage. Either one of the input nodes of the boosting stage corresponding to the different clock signals with de and the first boost stage and a connection switching unit that connects to a gate of the charge transfer transistor.

  In the booster circuit, the potential difference between the gate and the drain and the potential difference between the gate and the source of the charge transfer transistor in the conductive state can be made smaller than before, and the withstand voltage limitation of the charge transfer transistor can be relaxed.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate in a complementary manner. A plurality of boosting stages each including a boosting stage, each of the plurality of boosting stages having an input node and an output node, and boosting in response to one of the first and second clock signals; The first boosting stage, which is one of the plurality of boosting stages, operates and includes a charge transfer transistor connected between the input node and the output node, and one end connected to the output node. A boosting capacitor that receives a clock signal corresponding to the first boosting stage at the other end, a drain connected to the gate of the charge transfer transistor, and the first boosting stage. An off switch having a source connected to the input node of the boosting stage corresponding to the same clock signal as the first clock, and a gate connected to the input node of the boosting stage corresponding to the clock signal different from the first boosting stage A transistor, a drain connected to the gate of the charge transfer transistor, a source connected to the output node of the boosting stage corresponding to a clock signal different from the first boosting stage, and the first boosting stage; And an on-switch transistor having a gate connected to the output node of the boosting stage corresponding to the same clock signal.

  In the booster circuit, in each of the charge transfer transistor, the off switch transistor, and the on switch transistor, the potential difference between the gate and the drain and the potential difference between the gate and the source can be made smaller than before, and the withstand voltage of the transistor is further limited. Can be relaxed.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate in a complementary manner. A plurality of boosting stage trains each including a boosting stage; and an analog comparison circuit, each of the plurality of boosting stages having an input node and an output node, and one of the first and second clock signals. A first boosting stage, which is one of the plurality of boosting stages, performs a boosting operation in response to one of the plurality of boosting stages, and includes a charge transfer transistor connected between the input node and the output node, and one end connected to the output node. And a boost capacitor that receives a clock signal corresponding to the first boost stage at the other end, a drain connected to the gate of the charge transfer transistor, An off-switch transistor having a source connected to the input node of the boosting stage corresponding to the same clock signal as the first boosting stage, a gate, a drain connected to the gate of the charge transfer transistor, and The analog comparison circuit includes an on-switch transistor having a source connected to an output node of the boosting stage corresponding to a clock signal different from that of the first boosting stage, and a gate. The voltage at the output node of the corresponding boost stage is compared with the voltage at the output node of the boost stage corresponding to the second clock signal, and according to the comparison result, of the output nodes of the two boost stages. Either one is connected to the off switch transistor or the on switch transistor. To connect to each of the gate of the register.

  In the booster circuit, in each of the charge transfer transistor, the off switch transistor, and the on switch transistor, the potential difference between the gate and the drain and the potential difference between the gate and the source can be made smaller than before, and the withstand voltage of the transistor is further limited. Can be relaxed. In addition, the charge / discharge charge amount at the gates of the off switch transistor and the on switch transistor can be reduced.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate in a complementary manner. A plurality of boosting stages each including a boosting stage, each of the plurality of boosting stages having an input node and an output node, and boosting in response to one of the first and second clock signals; The first boosting stage, which is one of the plurality of boosting stages, operates and includes a charge transfer transistor connected between the input node and the output node, and one end connected to the output node. A boosting capacitor that receives the clock signal corresponding to the first boosting stage at the other end, a drain connected to the gate of the charge transfer transistor, and the first boosting stage. An off-switch transistor having a source connected to the input node of the boosting stage corresponding to the same clock signal as the gate, a gate connected to the gate control node, and a drain connected to the gate of the charge transfer transistor; An on-switch transistor having a source connected to an output node of the boosting stage corresponding to a clock signal different from the first boosting stage, a gate connected to the gate control node, the input node, and the A sub-charge transfer transistor having a gate connected in series with the charge transfer transistor between the output node and a gate connected to the output node of the boost stage corresponding to a clock signal different from the first boost stage; The charge transfer transistor and the sub charge transfer transistor The connection point is connected to the gate control node.

  In the booster circuit, in each of the charge transfer transistor, the off switch transistor, and the on switch transistor, the potential difference between the gate and the drain and the potential difference between the gate and the source can be made smaller than before, and the withstand voltage of the transistor is further limited. Can be relaxed.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate complementarily. A plurality of boost stage stages that repeat the boost operation in response to a second clock signal, a plurality of backflow prevention circuits respectively corresponding to the plurality of boost circuits, and an output terminal for outputting the boost voltage, Each of the plurality of backflow prevention circuits is responsive to one of an input node connected to the boosting stage train, an output node connected to the output terminal, and the first and second clock signals. A first backflow prevention circuit, which is one of the plurality of backflow prevention circuits, includes a charge transfer transistor connected between the input node and the output node. A booster capacitor having one end connected to the intermediate node and receiving a clock signal corresponding to the first backflow prevention circuit at the other end, and a backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit And a connection switching unit for connecting one of the input nodes of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit to the gate of the charge transfer transistor.

  In the booster circuit, the potential difference between the gate and the drain and the potential difference between the gate and the source of the charge transfer transistor in the conductive state can be made smaller than before, and the withstand voltage limitation of the charge transfer transistor can be relaxed. In addition, the charge transfer efficiency in the backflow prevention circuit can be improved as compared with the prior art.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate complementarily. A plurality of boost stage stages that repeat the boost operation in response to a second clock signal, a plurality of backflow prevention circuits respectively corresponding to the plurality of boost circuits, and an output terminal for outputting the boost voltage, Each of the plurality of backflow prevention circuits is responsive to one of an input node connected to the boosting stage train, an output node connected to the output terminal, and the first and second clock signals. A first backflow prevention circuit, which is one of the plurality of backflow prevention circuits, includes a charge transfer transistor connected between the input node and the output node. A booster capacitor having one end connected to the intermediate node and receiving a clock signal corresponding to the first backflow prevention circuit at the other end, and a backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit And a connection switching unit for connecting one of the intermediate nodes of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit to the gate of the charge transfer transistor.

  In the booster circuit, the withstand voltage limit of the charge transfer transistor can be relaxed as compared with the conventional circuit. In addition, the charge transfer efficiency in the backflow prevention circuit can be improved as compared with the prior art.

  According to another aspect of the present invention, the booster circuit is a circuit that generates a boosted voltage by performing a boosting operation in response to the first and second clock signals that fluctuate complementarily. A plurality of boost stage stages that repeat the boost operation in response to a second clock signal, a plurality of backflow prevention circuits respectively corresponding to the plurality of boost circuits, and an output terminal for outputting the boost voltage, Each of the plurality of backflow prevention circuits includes an input node connected to the boost stage stage, and an intermediate node boosted in response to one of the first and second clock signals, A first backflow prevention circuit, which is one of a plurality of backflow prevention circuits, includes a charge transfer transistor connected between the input node and the intermediate node, and one end connected to the intermediate node. In addition, the boosting capacitor that receives the clock signal corresponding to the first backflow prevention circuit at the other end, the input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit, and the first backflow A connection switching unit for connecting one of the intermediate nodes of the backflow prevention circuit corresponding to a clock signal different from the prevention circuit to the gate of the charge transfer transistor, and the charge transfer between the input node and the intermediate node. A sub-charge transfer transistor connected in series with the transistor and having a gate connected to an intermediate node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit, the charge transfer transistor and the A connection point with the sub charge transfer transistor is connected to the output terminal.

  In the booster circuit, the withstand voltage limit of the charge transfer transistor can be relaxed as compared with the conventional circuit. In addition, since the gate voltage of the charge transfer transistor can be increased, the transfer efficiency and transfer speed of the charge transfer transistor can be improved.

  As described above, the withstand voltage limit of the charge transfer transistor can be relaxed in the booster circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 shows the configuration of a booster circuit according to Embodiment 1 of the present invention. The booster circuit 1 generates a boosted voltage Vpump by performing a boosting operation in response to clock signals CLK1 and CLK2, and includes first stage stages 11m and 11n, booster stages 12m, 12n, 13m, and 13n, and a backflow prevention circuit. 14m, 14n.

  Clock signals CLK1 and CLK2 transition complementarily to each other. Here, it is assumed that one of the clock signals CLK1 and CLK2 transitions from the low level (Vss) to the high level (Vdd) and then the other transitions from the high level to the low level.

  The first stage 11m and the boost stages 12m and 13m are connected in cascade to form a first boost stage row. The first stage 11n and the boost stages 12n and 13n are connected in cascade to form a second boost stage row. The backflow prevention circuit 12m is connected to the final boosting stage 13m included in the first boosting stage train, and the backflow prevention circuit 12n is connected to the final boosting stage 13n included in the second boosting stage train. . Note that the booster circuit 1 may include three or more booster stage rows.

  In the first boost stage row, the odd-numbered boost stages (first stage 11m, boost stage 13m) operate in response to the clock signal CLK1, and the even-numbered boost stage (boost stage 12m) receives the clock signal CLK2. Operates in response. On the other hand, in the second boost stage row, the odd-numbered boost stages (first stage 11n, boost stage 13n) operate in response to the clock signal CLK2, and the even-numbered boost stage (boost stage 12n) Operates in response to CLK1.

  The first stage 11m, 11n, the boost stage 12m, 12n, the boost stage 13m, 13n, and the backflow prevention circuits 14m, 14n correspond to each other, and the first stage cell 11, the boost cell 12, the boost cell 13, and the backflow prevention. The cell 14 is configured.

[Boost cell]
FIG. 2 shows the configuration of the booster cell 12 shown in FIG. Each of the boost stages 12m and 12n includes a charge transfer transistor 101, an off switch transistor 102, an on switch transistor 103, and a boost capacitor 104. Here, the charge transfer transistor 101 and the off-switch transistor 102 are P-type transistors, and the on-switch transistor 103 is an N-type transistor. Note that the configuration of the booster cell 13 is the same as the configuration of the booster cell 12, and therefore the description thereof is omitted here.

  The charge transfer transistor 101 is connected between the input node N105 and the output node N106, and transfers charge from the input node N105 to the output node N106. The off switch transistor 102 equalizes the voltage at the output node N106 and the gate voltage of the charge transfer transistor 101 to turn off the charge transfer transistor 101. The on-switch transistor 103 supplies the voltage at the input node N105 of the other boosting stage to the gate of the charge transfer transistor 101 to turn on the charge transfer transistor 101. One end of the boost capacitor 104 is connected to the output node N106, and the other end of the boost capacitor 104 is supplied with a clock signal (CLK1 or CLK2) corresponding to the boost stage including the boost capacitor 104.

[First stage cell]
FIG. 3 shows a configuration of the first stage cell 11 shown in FIG. The input nodes N105 and N105 of the first stage 11m and 11n are connected to an input terminal Tin that receives the power supply voltage VDD. In each of the initial stages 11m and 11n, the clock signal CLK1 or CLK2 is supplied to the source of the on-switch transistor 103. The other configuration is the same as that of the booster cell 12 of FIG.

[Backflow prevention cell]
FIG. 4 shows the configuration of the backflow prevention cell 14 shown in FIG. Each of the backflow prevention circuits 14m and 14n further includes a diode connection transistor 111 in addition to the charge transfer transistor 101, the off switch transistor 102, the on switch transistor 103, and the boost capacitor 104 shown in FIG. Further, one end of the boost capacitor 104 and the source of the off switch transistor 102 are connected not to the output node N106 but to the intermediate node N107. The diode-connected transistor 111 is connected between the input node N105 and the intermediate node N107, and supplies the voltage of the input node N105 to the intermediate node N107 in one direction. The boost capacitor 104 is pumped in synchronization with the clock signal CLK1 (or CLK2), so that the off switch transistor 102 and the on switch transistor 103 are turned on / off. The output nodes N106 and N106 of the backflow prevention circuits 14m and 14n are connected to an output terminal Tout for outputting the boosted voltage Vpump. The other configuration is the same as that of the booster cell 12 of FIG.

[Operation]
Next, the operation of the booster circuit shown in FIG. 1 will be described with reference to FIG. Note that each of the clock signals CLK1 and CLK2 varies between the power supply potential Vdd and the ground potential Vss, and a case where there is no current load at the output terminal Tout of the booster circuit and there is no voltage limit will be described. . In the figure, “VV1”, “VV2”, “VV3”, and “VV4” are as follows.

(VV1) = Vdd + α · Vdd
(VV2) = Vdd + 2α · Vdd
(VV3) = Vdd + 3α · Vdd
(VV4) = Vdd + 4α · Vdd−Vt
However, “α” is an effective boosted clock voltage, and α ≦ 1. “Vt” is a threshold voltage of the transistor.

  At time T1, the clock signal CLK1 transitions from a low level to a high level. As a result, the voltages V11m, V12n, V13m, and V14n increase. Accordingly, the voltages V11m to V14m and V11n to V14n are as follows.

(V11m) = (V11n) = Vdd + α · Vdd
(V12m) = (V12n) = Vdd + 2α · Vdd
(V13m) = (V13n) = Vdd + 3α · Vdd
(V14m) = (V14n) = Vdd + 4α · Vdd−Vt
In each of the first stage 11m, 11n, the boosting stage 12m, 12n, 13m, 13n, and the backflow prevention circuits 14m, 14n, the gate and the source of the on-switch transistor 103 are at the same potential. It becomes conductive.

  Further, in each of the first stage 11m, 11n and the boosting stage 12m, 12n, 13m, 13n, the potential difference between the gate and the source of the off switch transistor 102 (potential difference between the gate and the source) becomes “α · Vdd”. -The transistor 102 becomes conductive. Similarly, in each of the backflow prevention circuits 14m and 14m, the gate-source potential difference of the off switch transistor 102 becomes “α · Vdd−Vt”, and the off switch transistor 102 becomes conductive.

  In this way, the charge transfer transistor 101 is set in a non-conducting state in each of the initial stages 11m and 11n, the boosting stages 12m, 12n, 13m, and 13n, and the backflow prevention circuits 14m and 14n. Thereby, it is possible to prevent the backflow of charges in each of the first stage cell 11, the boosting cells 12, 13 and the backflow prevention cell 14 at the time of transition of the clock signals CLK1 and CLK2.

  At time T2, the clock signal CLK2 changes from high level to low level. As a result, the voltages V11n, V12m, V13n, and V14m drop. On the other hand, the voltages V11m, V12n, V13m, and V14n do not change. Accordingly, the voltages V11m to V14m and V11n to V14n are as follows.

(V11m) = Vdd + α · Vdd (V11n) = Vdd
(V12m) = Vdd + α · Vdd (V12n) = Vdd + 2α · Vdd
(V13m) = Vdd + 3α · Vdd (V13n) = Vdd + 2α · Vdd
(V14m) = Vdd + 3α · Vdd (V14n) = Vdd + 4α · Vdd−Vt
In each of the first stage 11n and the boosting stages 12m and 13n, the potential difference between the gate and the source of the off switch transistor 102 becomes “0”, and the off switch transistor 102 becomes non-conductive. Further, the potential difference between the gate and the source of the on-switch transistor 103 becomes “α · Vdd”, and the on-switch transistor 103 becomes conductive. As a result, the charge transfer transistor 101 becomes conductive.

  On the other hand, in each of the first stage 11m and the boosting stages 12n and 13m, the off switch transistor 102 is turned on and the on switch transistor 103 is turned off. As a result, the charge transfer transistor 101 is turned off.

  In the backflow prevention circuit 14m, the potential difference between the gate and the source of the off switch transistor 102 is “0”, and the off switch transistor 102 is turned off. Further, the potential difference between the gate and the source of the on-switch transistor 103 becomes “α · Vdd”, and the on-switch transistor becomes conductive. As a result, the charge transfer transistor 101 becomes conductive.

  On the other hand, in the backflow prevention circuit 14n, the off switch transistor 102 becomes conductive and the on switch transistor 103 becomes nonconductive. As a result, the charge transfer transistor 101 is turned off.

  In this way, charges are transferred in each of the first stage 11n, the boost stages 12m and 13n, and the backflow prevention circuit 14m, and the voltages V11n, V12m, V13n, and the boost voltage Vpump are increased. Further, the backflow of charges can be prevented in each of the first stage 11m, the boosting stages 12n and 13m, and the backflow prevention circuit 14n.

  At time T3, the clock signal CLK2 changes from the low level to the high level. As a result, the voltages V11n, V12m, V13n, and V14m increase. On the other hand, the voltages V11m, V12n, V13m, and V14n do not change. Accordingly, the voltages V11m to V14m and V11n to V14n are as follows.

(V11m) = (V11n) = Vdd + α · Vdd
(V12m) = (V12n) = Vdd + 2α · Vdd
(V13m) = (V13n) = Vdd + 3α · Vdd
(V14m) = (V14n) = Vdd + 4α · Vdd−Vt
In each of the first stage 11m, 11n, the boosting stage 12m, 12n, 13m, 13n, and the backflow prevention circuits 14m, 14n, processing similar to that at time T1 is executed.

  At time T4, the clock signal CLK1 changes from high level to low level. As a result, the voltages V11m, V12n, V13m, and V14n drop. On the other hand, the voltages V11n, V12m, V13n, and V14m do not change. Accordingly, the voltages V11m to V14m and V11n to V14n are as follows.

(V11m) = Vdd (V11n) = Vdd + α · Vdd
(V12m) = Vdd + 2α · Vdd (V12n) = Vdd + α · Vdd
(V13m) = Vdd + 2α · Vdd (V13n) = Vdd + 3α · Vdd
(V14m) = Vdd + 4α · Vdd−Vt (V14n) = Vdd + 3α · Vdd
In each of the first stage 11m, the boosting stages 12n and 13m, and the backflow prevention circuit 14n, the on-switch transistor 103 is turned on and the charge transfer transistor 101 is turned on. On the other hand, in each of the first stage 11n, the boosting stages 12m and 13n, and the backflow prevention circuit 14m, the off switch transistor 102 is turned on and the charge transfer transistor 101 is turned off.

  Thus, charge transfer is performed in each of the first stage 11m, the boosting stages 12n and 13m, and the backflow prevention circuit 14n, and the voltages V11m, V12n, V13m, and the boosted voltage Vpump are increased. Further, the backflow of charges can be prevented in each of the first stage 11n, the boosting stages 12m and 13n, and the backflow prevention circuit 14m.

  At times T5 and T6, operations similar to those at times T1 and T2 are executed. In this way, the boosting operation is repeated.

  According to the present embodiment, the gate-drain potential difference and the gate-source potential difference of the charge transfer transistor 101 in the conductive state can be set to “Vdd” or less, and the withstand voltage limit of the charge transfer transistor is more limited than in the past. Can be relaxed. In addition, the charge transfer efficiency in the backflow prevention cell 14 can be improved as compared with the prior art.

  Further, by using a P-type transistor as the charge transfer transistor 101, the substrate bias effect of the charge transfer transistor 101 can be reduced in a twin well process. Further, the potential difference between the gate and the substrate of the charge transfer transistor 101 can be reduced.

  Further, since the input node N105 having a voltage lower than that of the output node N106 is connected to the N-type transistor (here, the on-switch transistor 103), the potential difference between the gate and the substrate of the N-type transistor can be reduced. .

  The source of the off-switch transistor 102 corresponds to the same clock signal as that of the boosting stage including the off-switch transistor 102, and is connected to the output node N106 of the boosting stage located at the same stage or the subsequent stage of the boosting stage. It only has to be connected.

  The source of the on-switch transistor 103 corresponds to a clock signal different from that of the boosting stage including the on-switch transistor 103, and is located at the same stage or preceding stage as the boosting stage including the on-switch transistor 103. It only needs to be connected to the input node N105 of the boosting stage.

  The gates of the off switch transistor 102 and the on switch transistor 103 correspond to the same clock signal as that of the boosting stage including the transistors 102 and 103, and the boosting stage including the transistors 102 and 103. As long as it is connected to the input node N105 of the boosting stage located at the same stage or preceding stage.

(Embodiment 2)
6, FIG. 7, and FIG. 8 respectively show the configuration of the booster cell, the first stage cell, and the backflow prevention cell in the second embodiment of the present invention.

[Boost cell]
The boosting cell 22 shown in FIG. 6 includes boosting stages 22m and 22n. In each of the boosting stages 22m and 22n, the gate of the off-switch transistor 102 is connected not to the input node N105 of the boosting stage but to the output node N106 of the other boosting stage. Other configurations are the same as those of the booster cell 12 shown in FIG.

  Here, when the voltages V11m, V11n, V12m, and V12n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd”, respectively (that is, at time T2 in FIG. 5). 2), the potential difference between the gate and the source of the off switch transistor 102 is “2α · Vdd” in the boost stage 12n shown in FIG. On the other hand, in the boosting stage 22n shown in FIG. 6, the gate-source potential difference of the off switch transistor 102 is “α · Vdd”.

  Similarly, when the voltages V11m, V11n, V12m, and V12n are “Vdd”, “Vdd + α · Vdd”, “Vdd + 2α · Vdd”, and “Vdd + α · Vdd”, respectively (that is, at time T2 in FIG. 5). In the step-up stage 22m shown in FIG. 6, the potential difference between the gate and the source of the off switch transistor 102 is “α · Vdd”.

[First stage cell]
The first stage cell 21 shown in FIG. 7 includes first stage stages 21m and 21n. In each of the first stage stages 21m and 21n, the gate of the off switch transistor 102 is connected not to the input terminal Tin but to the output node N106 of the other first stage. Other configurations are the same as those of the first-stage cell 11 shown in FIG.

[Backflow prevention cell]
The backflow prevention cell 24 shown in FIG. 8 includes backflow prevention circuits 24m and 24n. In each of the backflow prevention circuits 24m and 24n, the gate of the off-switch transistor 102 is connected not to the input node N105 of the backflow prevention circuit but to the intermediate node N107 of the other backflow prevention circuit. Other configurations are the same as those of the backflow prevention cell 14 shown in FIG.

  By configuring the boosting cell, the first stage cell, and the backflow prevention cell as described above, in each of the charge transfer transistor 101, the off-switch transistor 102, and the on-switch transistor 103, the potential difference between the gate and the drain (gate and drain and And the potential difference between the gate and the source can be set to “α · Vdd” or less. Thereby, the withstand voltage limit of the transistor can be further relaxed.

  Note that the gate of the off-switch transistor 102 corresponds to a clock signal different from that of the boosting stage including the off-switch transistor 102, and is located at the same stage or a subsequent stage as the boosting stage including the off-switch transistor 102. It only has to be connected to the output node N106 of the boosting stage.

(Embodiment 3)
FIG. 9 shows the configuration of the booster cell according to the third embodiment of the present invention. The boosting cell 32 shown in FIG. 9 includes boosting stages 32m and 32n and an analog comparison circuit 301. The analog comparison circuit 301 corresponds to the boosting stages 32m and 32n, and includes transistors 301a and 301b. In each of the boosting stages 32m and 32n, the gates of the off switch transistor 102 and the on switch transistor 103 are connected to the gate control node 301c. The analog comparison circuit 301 connects the input node having the higher voltage among the input nodes N105 and N105 of the boosting stages 32m and 32n to the gate control node 301c. Other configurations are the same as those of the booster cell 12 shown in FIG.

[Operation]
Next, the operation of the booster cell 32 shown in FIG. 9 will be described with reference to FIG.

  When the voltages V11m, V11n, V12m, and V12n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd” (for example, a period from time T2 to time T3), analog comparison In the circuit 301, the transistor 301a is turned on, and the input node N105 of the boosting stage 32m is connected to the gate control node 301c. In the boost stage 32m, the on-switch transistor 103 is turned on and the charge transfer transistor 101 is turned on. On the other hand, in the boosting stage 32n, the off-switch transistor 102 is turned on and the charge transfer transistor 101 is turned off.

  Conversely, when the voltages V11m, V11n, V12m, and V12n are “Vdd”, “Vdd + α · Vdd”, “Vdd + 2α · Vdd”, and “Vdd + α · Vdd” (for example, a period from time T4 to time T5). In the analog comparison circuit 301, the transistor 301b is turned on, and the input node N105 of the boosting stage 32n is connected to the gate control node 301c. In the boost stage 32m, the off-switch transistor 102 is turned on and the charge transfer transistor 101 is turned off. On the other hand, in the boosting stage 32n, the on-switch transistor 103 is turned on and the charge transfer transistor 101 is turned on.

  When the voltages V11m and V11n are both “Vdd + α · Vdd” and the voltages V12m and V12n are both “Vdd + 2α · Vdd” (for example, a period from time T1 to T2), the analog comparison circuit 301 includes a transistor 301a. , 301b are turned off. Thereby, the voltage V301c at the gate control node 301c is maintained at “Vdd + α · Vdd”. In each of the boosting stages 32m and 32n, the off switch transistor 102 is turned on and the charge transfer transistor 101 is turned off.

  As described above, the voltage V301c at the gate control node 301c is always maintained at “Vdd + α · Vdd”. As a result, in each of the charge transfer transistor 101, the off switch transistor 102, and the on switch transistor 103, the gate-drain potential difference and the gate-source potential difference can always be set to “α · Vdd” or less. For example, when the voltages V11m, V11n, V12m, and V12n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd”, respectively, the boost stage 12n shown in FIG. The potential difference between the gate and the source of the switch transistor 102 is “2α · Vdd”, but the potential difference between the gate and the source of the off switch transistor 102 is set to “α · Vdd” in the boost stage 32n shown in FIG. Is possible. In this manner, the withstand voltage limit of the transistor can be further relaxed.

  Further, the charge / discharge charge amount at each gate of the off switch transistor 102 and the on switch transistor 103 can be reduced.

  Note that the analog comparison circuit 301 only needs to correspond to the boosting stage corresponding to the clock signal CLK1 and the boosting stage corresponding to the clock signal CLK2 and located at the same stage as the boosting stage.

(Modification of Embodiment 3)
Further, as shown in FIG. 11, the analog comparison circuit 301 compares the voltage at the output node N106 of the boosting stage 32m with the voltage at the output node N106 of the boosting stage 32n, and the boosting stages 32m and 32n according to the comparison result. You may comprise so that any one of each output node N106 and N106 may be selected. In the boosting cell 32a shown in FIG. 11, the analog comparison circuit 301 connects the output node having the lower voltage of the output nodes N106 and N106 of the boosting stages 32m and 32n to the gate control node 301c.

  Even in such a configuration, in each of the charge transfer transistor 101, the off switch transistor 102, and the on switch transistor 103, the potential difference between the gate and the drain and the potential difference between the gate and the source are always set to “α · Vdd” or less. can do.

(Embodiment 4)
FIG. 12 shows the configuration of a booster cell according to Embodiment 4 of the present invention. In the boosting cell 42 shown in FIG. 12, the boosting stages 42m and 42n have sub-charges in addition to the charge transfer transistor 101, off-switch transistor 102, on-switch transistor 103, and boosting capacitor 104 shown in FIG. A transfer transistor 401 is included. The sub charge transfer transistor 401 is a transistor having the same polarity as the charge transfer transistor 101 and is connected in series between the input node N105 and the output node N106 together with the charge transfer transistor 101. A connection point between the charge transfer transistor 101 and the sub charge transfer transistor 401 is connected to the gate control node 402. In each of the boosting stages 42 m and 42 n, the gates of the off switch transistor 102 and the on switch transistor 103 are connected to the gate control node 402.

  In each of the boosting stages 42m and 42n, the well of the charge transfer transistor 101 and the well of the sub charge transfer transistor 401 are connected to reduce the area.

[Operation]
Next, the operation of the booster cell 42 shown in FIG. 12 will be described.

  When the voltages V11m, V11n, V12m, and V12n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd”, the sub-charge transfer transistor 401 becomes conductive in the boosting stage 42m. On the other hand, in the boosting stage 42n, the sub charge transfer transistor 401 is turned off. As a result, the voltage at the gate control node 402 becomes “Vdd + α · Vdd”. In the boost stage 32m, the on-switch transistor 103 is turned on and the charge transfer transistor 101 is turned on. On the other hand, in the boosting stage 32n, the off-switch transistor 102 is turned on and the charge transfer transistor 101 is turned off.

  Conversely, when the voltages V11m, V11n, V12m, and V12n are “Vdd”, “Vdd + α · Vdd”, “Vdd + 2α · Vdd”, and “Vdd + α · Vdd”, respectively, the sub-charge transfer transistor 401 is not in the boost stage 42m. On the other hand, the sub charge transfer transistor 401 becomes conductive in the boosting stage 42n. As a result, the voltage at the gate control node 402 becomes “Vdd + α · Vdd”. In the boost stage 32m, the off-switch transistor 102 is turned on and the charge transfer transistor 101 is turned off. On the other hand, in the boosting stage 32n, the on-switch transistor 103 is turned on and the charge transfer transistor 101 is turned on.

  Further, when the voltages V11m and V11n are both “Vdd + α · Vdd” and the voltages V12m and V12n are both “Vdd + 2α · Vdd”, the sub-charge transfer transistor 401 is brought into a non-conductive state in both the boosting stages 42m and 42n. Become. As a result, the voltage at the gate control node 402 is maintained at “Vdd + α · Vdd”. In each of the boosting stages 32m and 32n, the off switch transistor 102 is turned on and the charge transfer transistor 101 is turned off.

  As described above, the voltage at the gate control node 402 is always maintained at “Vdd + α · Vdd”. Thereby, in each of the charge transfer transistor 101, the off-switch transistor 102, and the on-switch transistor 103, the gate-drain potential difference and the gate-source potential difference can always be set to “α · Vdd” or less, The withstand voltage limit of the transistor can be further relaxed.

  Note that the gate of the sub charge transfer transistor 401 corresponds to a clock signal different from that of the boost stage including the sub charge transfer transistor 401 and is located at the same stage or preceding stage as the boost stage including the sub charge transfer transistor 401. As long as it is connected to the input node N105.

(Modification of Embodiment 4)
Further, like the boosting cell 42a shown in FIG. 13, the sub charge transfer transistor 401 shown in FIG. 12 and the analog comparison circuit 301 shown in FIG. 9 may be used in combination. With this configuration, in each of the charge transfer transistor 101, the off-switch transistor 102, the on-switch transistor 103, and the sub charge transfer transistor 401, the gate-drain potential difference and the gate-source potential difference are set to “α · Vdd In addition to being able to be set below, the charge / discharge charge amount in the diffusion capacitors of the charge transfer transistor 101 and the sub charge transfer transistor 401 can be reduced.

(Embodiment 5)
14, FIG. 15, and FIG. 16 show the configurations of the booster cell, the first stage cell, and the backflow prevention cell in the fifth embodiment of the present invention, respectively.

[Boost cell]
Boosting cells 52 and 53 shown in FIG. 14 include boosting stages 52m and 52n and boosting stages 53m and 53n, respectively. Boost stages 52m and 52n, boost stages 53m and 53n each include a charge transfer transistor 501, an off switch transistor 502, an on switch transistor 503, and a boost capacitor 104. Here, the charge transfer transistor 501 and the off-switch transistor 502 are N-type transistors, and the on-switch transistor 503 is a P-type transistor.

  The charge transfer transistor 501 is connected between the input node N105 and the output node N106, and transfers charge from the input node N105 to the output node N106. The off switch transistor 502 equalizes the voltage at the input node N105 and the gate voltage of the charge transfer transistor 501 to turn off the charge transfer transistor 501. The on-switch transistor 503 supplies the voltage at the output node N106 of the other boosting stage to the gate of the charge transfer transistor 501 to turn on the charge transfer transistor 501.

[First stage cell]
The first stage cell 51 shown in FIG. 15 includes first stage stages 51m and 51n. In the first stage 51m, 51n, the input node N105 and the gate of the off switch transistor 502 are connected to the input terminal Tin, and the clock signal CLK1 or CLK2 is supplied to the source of the off switch transistor 502. Other configurations are the same as those of the booster cell 52 shown in FIG.

[Backflow prevention cell]
The backflow prevention cell 54 shown in FIG. 16 includes backflow prevention circuits 54m and 54n. The backflow prevention circuits 54m and 54n further include a diode connection transistor 511 in addition to the charge transfer transistor 501, the off switch transistor 502, the on switch transistor 503, and the boost capacitor 104 shown in FIG. Further, one end of the boost capacitor 104 and the source of the on-switch transistor 503 are connected not to the output node N106 but to the intermediate node N107. The diode-connected transistor 511 is connected between the input node N105 and the intermediate node N107, and supplies the voltage of the input node N105 to the intermediate node N107 and the gate of the on-switch transistor 103 in one direction. The boost capacitor 104 is pumped in synchronization with the clock signal CLK1 (or CLK2), so that the off switch transistor 502 and the on switch transistor 503 are turned on / off. The output nodes N106 and N106 of the backflow prevention circuits 54m and 54n are connected to the output terminal Tout. Other configurations are the same as those of the booster cell 52 shown in FIG.

[Operation]
Next, the operation of the booster circuit according to the fifth embodiment will be described with reference to FIG. Here, it is assumed that one of the clock signals CLK1 and CLK2 transitions from the high level (Vdd) to the low level (Vss) and then the other transitions from the low level to the high level.

  At time T1, the clock signal CLK2 changes from high level to low level. As a result, the voltages V51n, V52m, V53n, and V54m drop. Accordingly, the voltages 51m to V54m and V51n to V54n are as follows.

(V51m) = (V51n) = Vdd
(V52m) = (V52n) = Vdd + α · Vdd
(V53m) = (V53n) = Vdd + 2α · Vdd
(V54m) = (V54n) = Vdd + 3α · Vdd
In each of the first stage 51m, 51n, the boosting stage 52m, 52n, 53m, 53n, and the backflow prevention circuits 54m, 54n, the gate and the source of the off switch transistor 502 are at the same potential. It becomes conductive. Further, since the gate and the source of the on-switch transistor 503 are at the same potential, the on-switch transistor 503 is also turned off. Thereby, it is possible to prevent the backflow of charges in each of the first stage cell 51, the boosting cells 52 and 53, and the backflow prevention cell 54 at the time of transition of the clock signals CLK1 and CLK2.

  At time T2, the clock signal CLK1 changes from high level to low level. As a result, the voltages V51m, V52n, V53m, and V54n increase. On the other hand, the voltages V51n, V52m, V53n, and V54m do not change. Accordingly, the voltages 51m to V54m and V51n to V54n are as follows.

(V51m) = Vdd + α · Vdd (V51n) = Vdd
(V52m) = Vdd + α · Vdd (V52n) = Vdd + 2α · Vdd
(V53m) = Vdd + 3α · Vdd (V53n) = Vdd + 2α · Vdd
(V54m) = Vdd + 3α · Vdd (V54n) = Vdd + 4α · Vdd−Vt
In the first stage 51m, since the potential difference between the gate and the source of the off switch transistor 502 is “Vdd”, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off. On the other hand, in the first stage 51n, since the potential difference between the gate and the source of the on-switch transistor 503 becomes “α · Vdd”, the on-switch transistor 503 becomes conductive and the charge transfer transistor 501 becomes conductive.

  Further, in each of the boosting stages 52n and 53m, the potential difference between the gate and the source of the off switch transistor 502 becomes “α · Vdd”, so that the off switch transistor 502 becomes conductive and the charge transfer transistor 501 becomes nonconductive. become. On the other hand, in each of the boosting stages 52m and 53n, since the gate-source potential difference of the on-switch transistor 503 is “α · Vdd”, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on. Become.

  In the backflow prevention circuit 54n, since the potential difference between the gate and the source of the off switch transistor 502 is “α · Vdd”, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off. On the other hand, in the backflow prevention circuit 54m, since the gate-source potential difference of the on-switch transistor 503 is “α · Vdd−Vt”, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on. .

  In this way, charges are transferred in each of the first stage 51n, the boost stages 52m and 53n, and the backflow prevention circuit 54m, and the voltages V51n, V52m and V53n, and the boost voltage Vpump are increased. In addition, the backflow of charges can be prevented in each of the first stage 51m, the boosting stages 52n and 53n, and the backflow prevention circuit 54n.

  At time T3, the clock signal CLK1 changes from high level to low level. As a result, the voltages V51m, V52n, V53m, and V54n drop. On the other hand, the voltages V51n, V52m, V53n, and V54m do not change. Accordingly, the voltages 51m to V54m and V51n to V54n are as follows.

(V51m) = (V51n) = Vdd
(V52m) = (V52n) = Vdd + α · Vdd
(V53m) = (V53n) = Vdd + 2α · Vdd
(V54m) = (V54n) = Vdd + 3α · Vdd
In each of the initial stages 51m and 51n, the boosting stages 52m, 52n, 53m and 53n, and the backflow prevention circuits 54m and 54n, processing similar to that at time T1 is executed.

  At time T4, the clock signal CLK2 changes from the low level to the high level. As a result, the voltages V51n, V52m, V53n, and V54m increase. On the other hand, the voltages V51m, V52n, V53m, and V54n do not change. Thereby, the voltages V51m to V54m and V51n to V54n are as follows.

(V51m) = Vdd (V51n) = Vdd + α · Vdd
(V52m) = Vdd + 2α · Vdd (V52n) = Vdd + α · Vdd
(V53m) = Vdd + 2α · Vdd (V53n) = Vdd + 3α · Vdd
(V54m) = Vdd + 4α · Vdd−Vt (V54n) = Vdd + 3α · Vdd
In the first stage 51n, the boosting stages 52m and 53n, and the backflow prevention circuit 54m, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off. On the other hand, in the first stage 51m, the boosting stages 52n and 53m, and the backflow prevention circuit 54n, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on.

  In this way, charges are transferred in each of the first stage 51m, the boosting stages 52n and 53m, and the backflow prevention circuit 54n, and the voltages V51m, V52n and V53m, and the boosted voltage Vpump are increased.

  At times T5 and T6, operations similar to those at times T1 and T2 are executed. In this way, the boosting operation is repeated.

  As described above, in each of the charge transfer transistor 501, the off switch transistor 502, and the on switch transistor 503, the gate-source voltage and the gate-drain potential can be set to “α · Vdd” or less. Thereby, the withstand voltage limit of the transistor can be relaxed as compared with the conventional case. In addition, the charge transfer efficiency in the backflow prevention cell 54 can be improved as compared with the prior art.

  The source of the off-switch transistor 502 corresponds to the same clock signal as that of the boosting stage including the off-switch transistor 502 and is located at the same stage or preceding stage as the boosting stage including the off-switch transistor 502. It only needs to be connected to the input node N105 of the boosting stage.

  The source of the on-switch transistor 503 corresponds to a clock signal different from that of the boosting stage including the on-switch transistor 503, and is connected to the output node N106 of the boosting stage located at the same stage or the subsequent stage of the boosting stage. It only has to be connected.

  Further, the gate of the off-switch transistor 502 corresponds to a clock signal different from that of the boosting stage including the off-switch transistor 502 and is located in the same stage or preceding stage as the boosting stage including the off-switch transistor 502. It only needs to be connected to the input node N105 of the boosting stage.

  Further, the gate of the on-switch transistor 503 corresponds to the same clock signal as that of the boosting stage including the on-switch transistor 503 and is located in the same stage or the subsequent stage of the boosting stage including the on-switch transistor 503. It only has to be connected to the output node N106 of the boosting stage.

(Modification of Embodiment 5)
As shown in FIG. 18, a sub charge transfer transistor 504 may be connected between the charge transfer transistor 501 and the output node N106. In the booster cell 52a shown in FIG. 18, the transistors 501, 502, and 503 can be driven by a voltage that is equal to or lower than the maximum voltage value of the clock signals CLK1 and CLK2, so that the withstand voltage limitation of the transistors can be further relaxed.

(Embodiment 6)
FIG. 19 shows the configuration of a booster cell according to the sixth embodiment of the present invention. The boosting cell 62 shown in FIG. 19 includes boosting stages 62m and 62n and an analog comparison circuit 601. The analog comparison circuit 601 corresponds to the boosting stages 62m and 62n, and includes transistors 601a and 601b. In each of the boosting stages 62m and 62n, the gates of the off switch transistor 502 and the on switch transistor 503 are connected to the gate control node 601c. The analog comparison circuit 601 connects the output node having the lower voltage of the output nodes N106 and N106 of the boosting stages 62m and 62n to the gate control node 601c. Other configurations are the same as those of the booster cell 52 shown in FIG.

[Operation]
Next, the operation of the booster cell 62 shown in FIG. 19 will be described with reference to FIG.

  When the voltages V51m, V51n, V52m, and V52n are “Vdd”, “Vdd + α · Vdd”, “Vdd + 2α · Vdd”, and “Vdd + α · Vdd” (for example, the period from time T2 to time T3), analog comparison In the circuit 601, the transistor 601b is turned on, and the output node N106 of the boosting stage 62n is connected to the gate control node 601c. In the boost stage 62m, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off. On the other hand, in the boosting stage 62n, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on.

  Conversely, when the voltages V51m, V51n, V52m, and V52n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd” (for example, a period from time T4 to time T5). In the analog comparison circuit 601, the transistor 601a is turned on, and the output node N106 of the boosting stage 62m is connected to the gate control node 601c. In the boosting stage 62m, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on. On the other hand, in the boosting stage 62n, the off switch transistor 502 is turned on and the charge transfer transistor 101 is turned off.

  When the voltages V51m and V51n are both “Vdd” and the voltages V52m and V52n are both “Vdd + α · Vdd” (for example, a period from time T1 to T2), the analog comparison circuit 601 includes transistors 601a and 601b. Both of these become non-conductive. As a result, the voltage V601c at the gate control node 601c is maintained at “Vdd + α · Vdd”. In each of the boosting stages 62m and 62n, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off.

  As described above, the voltage V601c at the gate control node 601c is always maintained at “Vdd + α · Vdd”. As a result, in each of the charge transfer transistor 501, the off switch transistor 502, and the on switch transistor 503, the gate-drain potential difference and the gate-source potential difference can always be set to "α · Vdd" or less. Thereby, the withstand voltage limit of the transistor can be further relaxed.

  Further, the charge / discharge charge amount at the gate of each of the off switch transistor 502 and the on switch transistor 503 can be reduced.

  Note that the analog comparison circuit 601 only needs to correspond to the boosting stage corresponding to the clock signal CLK1 and the boosting stage corresponding to the clock signal CLK2 and located at the same stage as the boosting stage.

(Modification of Embodiment 6)
Further, as shown in FIG. 21, the analog comparison circuit 601 compares the voltage at the input node N105 of the boosting stage 62m with the voltage at the input node N105 of the boosting stage 62n, and the boosting stages 62m and 62n according to the comparison result. You may comprise so that any one of each input node N105 and N105 may be selected. In the boosting cell 62a shown in FIG. 21, the analog comparison circuit 601 connects the input node having the higher voltage of the input nodes N105 and N105 of the boosting stages 32m and 32n to the gate control node 601c.

  Even in such a configuration, in each of the charge transfer transistor 501, the off switch transistor 502, and the on switch transistor 503, the gate-drain potential difference and the gate-source potential difference are always set to "α · Vdd" or less. can do.

(Embodiment 7)
FIG. 22 shows a configuration of the booster cell according to the seventh embodiment of the present invention. In the boosting cell 72 shown in FIG. 22, the boosting stages 72m and 72n include sub-charges in addition to the charge transfer transistor 501, the off-switch transistor 502, the on-switch transistor 503, and the boosting capacitor 104 shown in FIG. A transfer transistor 701 is included. The sub charge transfer transistor 701 is a transistor having the same polarity as the charge transfer transistor 501 and is connected in series between the input node N105 and the output node N106 together with the charge transfer transistor 501. A connection point between the charge transfer transistor 501 and the sub charge transfer transistor 701 is connected to the gate control node 702. In each of the boost stages 72m and 72n, the gates of the off switch transistor 502 and the on switch transistor 503 are connected to the gate control node 702.

  In each of the boosting stages 72m and 72n, the well of the charge transfer transistor 501 and the well of the sub charge transfer transistor 701 are connected to reduce the area.

[Operation]
Next, the operation of the booster cell 42 shown in FIG. 22 will be described.

  When the voltages V51m, V51n, V52m, and V52n are “Vdd + α · Vdd”, “Vdd”, “Vdd + α · Vdd”, and “Vdd + 2α · Vdd”, the sub-charge transfer transistor 701 becomes conductive in the boosting stage 72m. On the other hand, in the boosting stage 42n, the sub charge transfer transistor 701 is turned off. As a result, the voltage at the gate control node 702 becomes “Vdd + α · Vdd”. In the boosting stage 72m, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on. On the other hand, in the boosting stage 72n, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off.

  Conversely, when the voltages V51m, V51n, V52m, and V52n are “Vdd”, “Vdd + α · Vdd”, “Vdd + 2α · Vdd”, and “Vdd + α · Vdd”, respectively, the sub-charge transfer transistor 701 is not in the boost stage 72m. On the other hand, the sub charge transfer transistor 701 becomes conductive in the boosting stage 72n. As a result, the voltage at the gate control node 702 becomes “Vdd + α · Vdd”. In the boost stage 72m, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off. On the other hand, in the boosting stage 72n, the on-switch transistor 503 is turned on and the charge transfer transistor 501 is turned on.

  Further, when the voltages V51m and V51n are both “Vdd + α · Vdd” and the voltages V52m and V52n are both “Vdd + 2α · Vdd”, the sub charge transfer transistor 701 is brought into a non-conductive state in both the boosting stages 72m and 72n. Become. As a result, the voltage at the gate control node 702 is maintained at “Vdd + α · Vdd”. In each of the boosting stages 72m and 72n, the off switch transistor 502 is turned on and the charge transfer transistor 501 is turned off.

  As described above, the voltage at the gate control node 702 is always maintained at “Vdd + α · Vdd”. Thereby, in each of the charge transfer transistor 501, the off switch transistor 502, and the on switch transistor 503, the potential difference between the gate and the drain and the potential difference between the gate and the source can always be set to “α · Vdd” or less. The withstand voltage limit of the transistor can be further relaxed.

  Note that the gate of the sub charge transfer transistor 701 corresponds to a clock signal different from that of the boost stage including the sub charge transfer transistor 401, and is located in the same stage or a subsequent stage as the boost stage including the sub charge transfer transistor 701. As long as it is connected to the output node N106.

(Modification of Embodiment 7)
23, the sub charge transfer transistor 701 shown in FIG. 22 and the analog comparison circuit 601 shown in FIG. 19 may be used in combination, like the booster cell 72a shown in FIG. With this configuration, in each of the charge transfer transistor 501, the off switch transistor 502, the on switch transistor 503, and the sub charge transfer transistor 701, the gate-drain potential difference and the gate-source potential difference are set to “α · Vdd”. In addition to being able to be set below, the charge / discharge charge amount in the diffusion capacitance of each of the charge transfer transistor 501 and the sub charge transfer transistor 701 can be reduced.

(Modification of backflow prevention cell)
Instead of the backflow prevention cell in each of the above embodiments, the backflow prevention cells 54a to 54g shown in FIGS. 24 to 30 may be used for the booster circuit.

[Modification 1 of Backflow Prevention Cell]
The backflow prevention cell 54a shown in FIG. 24 includes the backflow prevention circuits 54m and 54n shown in FIG. In each of the backflow prevention circuits 54m and 54n, the gates of the off switch transistor 502 and the on switch transistor 503 are connected to the gate control node 521. The gate control node 521 is connected to the output terminal Tout. The other configuration is the same as that of the backflow prevention cell 54 shown in FIG.

  With this configuration, in each of the charge transfer transistor 501, the off-switch transistor 502, and the on-switch transistor 503, the gate-source voltage and the gate-drain potential are always set to “α · Vdd” or less. can do. Further, the charge / discharge charge amount at the gate of each of the off switch transistor 502 and the on switch transistor 503 can be reduced.

[Modification 2 of backflow prevention cell]
The backflow prevention cell 54b shown in FIG. 25 includes the backflow prevention circuits 54m and 54n shown in FIG. 24 and the analog comparison circuit 601 shown in FIG. In each of the backflow prevention circuits 54m and 54n, the gates of the off switch transistor 502 and the on switch transistor 503 are connected to the gate control node 601c. Other configurations are the same as those of the backflow prevention cell 54a shown in FIG.

  Even in such a configuration, the same effect as the backflow prevention cell 54a shown in FIG. 24 can be obtained.

[Modification 3 of backflow prevention cell]
In the backflow prevention cell 54c shown in FIG. 26, each of the backflow prevention circuits 54m and 54n includes the charge transfer transistor 501, the off switch transistor 502, the on switch transistor 503, the boost capacitor 104, and the diode connection transistor shown in FIG. In addition to 511, the sub charge transfer transistor 701 shown in FIG. A connection point between the charge transfer transistor 501 and the sub charge transfer transistor 701 is connected to the gate control node 521. The gates of the off switch transistor 502 and the on switch transistor 503 are also connected to the gate control node 521. The diode connection transistor 511 is connected between a connection point between the charge transfer transistor 501 and the sub charge transfer transistor 701 and the intermediate node N107.

  With this configuration, the voltage between the terminals of the charge transfer transistor 501 can be set to “α · Vdd” or less.

[Modification 4 of Backflow Prevention Cell]
In the backflow prevention cell 54d shown in FIG. 27, not the output node N106 but the gate control node 521 is connected to the output terminal Tout. Output node N106 is connected to intermediate node N107. Other configurations are the same as those of the backflow prevention cell 54c shown in FIG.

  With this configuration, the voltage between the terminals of the charge transfer transistor 501 can be set to “α · Vdd” or less. Further, by connecting the sub charge transfer transistor 701 between the intermediate node N107 and the output terminal Tout, the boosting operation can be performed after setting the intermediate node N107 to the input node N105 at the same potential. Therefore, since the gate voltage of the charge transfer transistor 501 can be increased (specifically, by the threshold voltage Vt), the transfer efficiency and transfer speed of the charge transfer transistor 501 can be improved.

[Modification 5 of Backflow Prevention Cell]
In the backflow prevention cell 54e shown in FIG. 28, the diode-connected transistor 511 is connected between the power supply node and the intermediate node N107. Other configurations are the same as those of the backflow prevention cell 54d shown in FIG.

  With this configuration, the influence of the parasitic capacitance of the diode-connected transistor 511 can be removed, and the boosting efficiency can be improved.

[Modification 6 of Backflow Prevention Cell]
In the backflow prevention cell 54f shown in FIG. 29, the gates of the off switch transistor 502 and the on switch transistor 503 are connected to the output node N106. A connection point between the charge transfer transistor 501 and the sub charge transfer transistor 701 is connected to the gate control node 702, and the gate control node 702 is connected to the output terminal Tout. Other configurations are the same as those of the backflow prevention cell 54e shown in FIG.

  Even in such a configuration, the influence of the parasitic capacitance of the diode-connected transistor 511 can be removed, and the boosting efficiency can be improved.

[Modification 7 of Backflow Prevention Cell]
In the backflow prevention cell 54g shown in FIG. 30, the gate of the off-switch transistor 502 included in each of the backflow prevention circuits 54m and 54n is connected to the input node N105 of the other backflow prevention circuit. Other configurations are the same as those of the backflow prevention cell 54f shown in FIG.

  Even in such a configuration, the influence of the parasitic capacitance of the diode-connected transistor 511 can be removed, and the boosting efficiency can be improved.

(Negative voltage booster circuit)
In the above embodiments, the booster circuit receives the power supply voltage VDD and generates the positive boosted voltage Vpump. However, as shown in FIG. 31, the booster circuit receives the ground voltage and receives the negative boosted voltage. Vnpump may be generated. For example, in order to generate the negative boosted voltage Vnpump in the booster circuit 1 according to the first embodiment, the polarity of the transistor may be reversed in each of the first stage cell 11, the booster cells 12 and 13, and the backflow prevention cell 14. Specifically, as shown in FIGS. 32, 33, and 34, the charge transfer transistor 101 and the off-switch transistor 102 are changed from P-type to N-type, and the on-switch transistor 103 is changed from N-type to P-type. Just do it. With this configuration, the voltages V11m to V14m and V11n to V14n change as shown in FIG. 35 in response to the clock signals CLK1 and CLK2.

  In particular, when the negative voltage booster circuit is configured using the booster cells 12, 22, 32, 32a, 42, and 42a, the charge transfer transistor 101 can be configured by an N-type transistor. The potential difference between the substrates can be reduced, and the withstand voltage limitation of the charge transfer transistor 101 can be further relaxed.

  In the booster circuits in the fifth, sixth, and seventh embodiments, a negative boosted voltage can be generated by inverting the polarity of the transistor in each of the first stage cell, the booster cell, and the backflow prevention cell.

(Other embodiments)
In each of the above embodiments, each of the initial stage, the boosting stage, and the backflow prevention circuit includes a diode element (or a diode-connected transistor) connected in parallel with the charge transfer transistor between the input node N105 and the output node N106. It may be. Such a diode element transfers charges in one direction from the input node N105 to the output node N106.

  In each of the above embodiments, each of the initial stage, the boosting stage, and the backflow prevention circuit has a diode element (or diode) having one end connected to the power supply node and the other end connected to the source of the charge transfer transistor. Connection transistor) may be included. Such a diode element transfers charges in one direction from the power supply node to the source of the charge transfer transistor.

  Further, the transition timings of the clock signals CLK1 and CLK2 may be shifted or may be simultaneous.

  Note that the booster circuit may be configured using the same type of booster cell, or the booster circuit may be configured using two or more types of booster cells. For example, the first-stage cell 11 in FIG. 3, the booster cell 22 in FIG. 6, the booster cell 32 in FIG. 9, the booster cell 42 in FIG. 12, and the backflow prevention cell 24 in FIG. Cell), second-stage boost cell, third-stage boost cell, fourth-stage boost cell, and backflow prevention cell may be configured.

  The booster circuit according to the present invention includes a power supply circuit used for a nonvolatile semiconductor memory device, a volatile semiconductor device (DRAM, etc.), a liquid crystal device, a portable device, etc., and a power supply used for improving analog circuit characteristics in a CMOS process. It is useful as a generator circuit.

1 is a block diagram showing a configuration of a booster circuit according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of a booster cell shown in FIG. 1. The circuit diagram which shows the structure of the first stage cell shown in FIG. The circuit diagram which shows the structure of the backflow prevention cell shown in FIG. FIG. 2 is a signal waveform diagram for explaining the operation of the booster circuit shown in FIG. 1. The circuit diagram which shows the structure of the pressure | voltage rise cell in Embodiment 2 of this invention. The circuit diagram which shows the structure of the first stage cell in Embodiment 2 of this invention. The circuit diagram which shows the structure of the backflow prevention cell in Embodiment 2 of this invention. The circuit diagram which shows the structure of the pressure | voltage rise cell in Embodiment 3 of this invention. FIG. 10 is a signal waveform diagram for explaining the operation of the booster cell shown in FIG. 9. FIG. 10 is a circuit diagram showing a modification of the booster cell shown in FIG. 9. The circuit diagram which shows the structure of the pressure | voltage rise cell by Embodiment 4 of this invention. FIG. 13 is a circuit diagram showing a modification of the booster cell shown in FIG. 12. The circuit diagram which shows the structure of the pressure | voltage rise cell in Embodiment 5 of this invention. The circuit diagram which shows the structure of the first stage cell in Embodiment 5 of this invention. The circuit diagram which shows the structure of the backflow prevention cell in Embodiment 5 of this invention. FIG. 10 is a signal waveform diagram for explaining the operation of the booster circuit according to the fifth embodiment of the present invention. FIG. 15 is a circuit diagram showing a modification of the booster cell shown in FIG. 14. The circuit diagram which shows the structure of the pressure | voltage rise cell in Embodiment 6 of this invention. FIG. 20 is a signal waveform diagram for explaining the operation of the booster cell shown in FIG. 19. FIG. 20 is a circuit diagram showing a modification of the booster cell shown in FIG. 19. The circuit diagram which shows the structure of the pressure | voltage rise cell in Embodiment 7 of this invention. FIG. 23 is a circuit diagram showing a modification of the booster cell shown in FIG. 22. The circuit diagram which shows the modification 1 of a backflow prevention cell. The circuit diagram which shows the modification 2 of a backflow prevention cell. The circuit diagram which shows the modification 3 of a backflow prevention cell. The circuit diagram which shows the modification 4 of a backflow prevention cell. The circuit diagram which shows the modification 5 of a backflow prevention cell. The circuit diagram which shows the modification 6 of a backflow prevention cell. The circuit diagram which shows the modification 7 of a backflow prevention cell. FIG. 3 is a block diagram showing a configuration of a booster circuit that generates a negative boosted voltage. FIG. 32 is a circuit diagram showing a configuration of a booster cell shown in FIG. 31. FIG. 32 is a circuit diagram showing a configuration of a first stage cell shown in FIG. 31. FIG. 32 is a circuit diagram showing a configuration of the backflow prevention cell shown in FIG. 31. FIG. 32 is a signal waveform diagram for explaining the operation of the booster circuit shown in FIG. 31. The circuit diagram which shows the structure of the conventional booster circuit. FIG. 37 is a signal waveform diagram for explaining the operation of the booster circuit shown in FIG. 36.

Explanation of symbols

1 Booster Circuits 11, 21, 51, First Stage Cells 12, 13, 22, 32, 32a, 42, 42a, 52, 52a, 53, 62, 62a, 72, 72a Booster Cells 14, 24, 54, 54a, 54b, 54c, 54d, 54e, 54f, 54g Backflow prevention cells 11m, 11n, first stage 12m, 12n, 13m, 13n, boost stage 14m, 14n backflow prevention circuit 101, 501 Charge transfer transistor 102, 502 Off switch transistor 103, 503 On-switch transistor 104 Boost capacitor N105 Input node N106 Output node 111 Diode-connected transistor N107 Intermediate nodes 301, 601 Analog comparison circuits 301a, 301b, 601a, 601b Transistors 301c, 601c Gate control node 401, 01 sub charge transfer transistors 402,702 gate control node

Claims (21)

A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boosting stage trains each including a plurality of boosting stages connected in cascade;
Each of the plurality of boosting stages has an input node and an output node, and performs a boosting operation in response to one of the first and second clock signals,
A first boosting stage, which is one of the plurality of boosting stages,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the output node and receiving a clock signal corresponding to the first boost stage at the other end;
Either the output node of the boosting stage corresponding to the same clock signal as the first boosting stage or the input node of the boosting stage corresponding to a clock signal different from the first boosting stage is connected to the charge transfer transistor. A booster circuit comprising: a connection switching unit connected to the gate. In claim 1,
The connection switching unit is
The absolute value of the voltage at the input node of the boosting stage corresponding to the same clock signal as that of the first boosting stage is based on the absolute value of the voltage at the input node of the boosting stage corresponding to the clock signal different from that of the first boosting stage. Is greater than or equal to, the output node of the boosting stage corresponding to the same clock signal as the first boosting stage is connected to the gate of the charge transfer transistor,
The absolute value of the voltage at the input node of the boosting stage corresponding to the same clock signal as that of the first boosting stage is based on the absolute value of the voltage at the input node of the boosting stage corresponding to the clock signal different from that of the first boosting stage. If the voltage is smaller than the first boosting stage, a boosting stage input node corresponding to a clock signal different from that of the first boosting stage is connected to the gate of the charge transfer transistor. In claim 2,
The connection switching unit is
The drain connected to the gate of the charge transfer transistor, the source connected to the output node of the boosting stage corresponding to the same clock signal as the first boosting stage, and the same clock signal as the first boosting stage An off-switch transistor having a gate connected to the input node of the boost stage corresponding to
The drain connected to the gate of the charge transfer transistor, the source connected to the input node of the boosting stage corresponding to a clock signal different from the first boosting stage, and the same clock signal as the first boosting stage And an on-switch transistor having a gate connected to the input node of the boosting stage corresponding to. In claim 2,
The connection switching unit is
A drain connected to the gate of the charge transfer transistor, a source connected to an output node of the boosting stage corresponding to the same clock signal as the first boosting stage, and a clock signal different from the first boosting stage An off-switch transistor having a gate connected to the output node of the boost stage corresponding to
The drain connected to the gate of the charge transfer transistor, the source connected to the input node of the boosting stage corresponding to a clock signal different from the first boosting stage, and the same clock signal as the first boosting stage And an on-switch transistor having a gate connected to the input node of the boosting stage corresponding to. In claim 2,
The voltage at the input node of the boosting stage corresponding to the first clock signal is compared with the voltage at the input node of the boosting stage corresponding to the second clock signal, and the two boosting stages are compared according to the comparison result. An analog comparison circuit for selecting any one of the input nodes;
The connection switching unit is
The drain connected to the gate of the charge transfer transistor, the source connected to the output node of the boosting stage corresponding to the same clock signal as the first boosting stage, and the input node selected by the analog comparison circuit An off-switch transistor having a gate connected thereto;
A drain connected to the gate of the charge transfer transistor, a source connected to an input node of a boosting stage corresponding to a clock signal different from the first boosting stage, and an input node selected by the analog comparison circuit And an on-switch transistor having a gate connected thereto. In claim 2,
The first boost stage includes
Sub-charge transfer having a gate connected in series with the charge transfer transistor between the input node and the output node and connected to the input node of the boost stage corresponding to a clock signal different from the first boost stage Further including a transistor;
The connection switching unit is
A drain connected to the gate of the charge transfer transistor; a source connected to an output node of the boosting stage corresponding to the same clock signal as the first boosting stage; and a gate connected to a gate control node. An off-switch transistor,
A drain connected to the gate of the charge transfer transistor, a source connected to an input node of the boosting stage corresponding to a clock signal different from the first boosting stage, and a gate connected to the gate control node An on-switch transistor having,
A boosting circuit, wherein a connection point between the charge transfer transistor and the sub charge transfer transistor is connected to the gate control node. In any one of Claims 3-6,
The boosted voltage is a negative voltage,
The charge transfer transistor and the off-switch transistor are P-type transistors, and the on-switch transistor is an N-type transistor. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boosting stage trains each including a plurality of boosting stages connected in cascade;
Each of the plurality of boosting stages has an input node and an output node, and performs a boosting operation in response to one of the first and second clock signals,
A first boosting stage, which is one of the plurality of boosting stages,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the output node and receiving a clock signal corresponding to the first boost stage at the other end;
A drain connected to the gate of the charge transfer transistor, a source connected to the input node of the boosting stage corresponding to the same clock signal as the first boosting stage, and a clock signal different from the first boosting stage An off-switch transistor having a gate connected to the input node of the boost stage corresponding to
The drain connected to the gate of the charge transfer transistor, the source connected to the output node of the boosting stage corresponding to a clock signal different from the first boosting stage, and the same clock signal as the first boosting stage And an on-switch transistor having a gate connected to the output node of the boosting stage corresponding to. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boost stage stages each including a plurality of cascaded boost stages;
With analog comparison circuit,
Each of the plurality of boosting stages has an input node and an output node, and performs a boosting operation in response to one of the first and second clock signals,
A first boosting stage, which is one of the plurality of boosting stages,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the output node and receiving a clock signal corresponding to the first boost stage at the other end;
An off-switch transistor having a drain connected to the gate of the charge transfer transistor, a source connected to an input node of the boosting stage corresponding to the same clock signal as the first boosting stage, and a gate;
An on-switch transistor having a drain connected to the gate of the charge transfer transistor, a source connected to an output node of the boosting stage corresponding to a clock signal different from the first boosting stage, and a gate ,
The analog comparison circuit compares the voltage at the output node of the boosting stage corresponding to the first clock signal with the voltage at the output node of the boosting stage corresponding to the second clock signal, and according to the comparison result One of the output nodes of the two boosting stages is connected to the respective gates of the off-switch transistor and the on-switch transistor. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boosting stage trains each including a plurality of boosting stages connected in cascade;
Each of the plurality of boosting stages has an input node and an output node, and performs a boosting operation in response to one of the first and second clock signals,
A first boosting stage, which is one of the plurality of boosting stages,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the output node and receiving a clock signal corresponding to the first boost stage at the other end;
A drain connected to the gate of the charge transfer transistor; a source connected to an input node of the boosting stage corresponding to the same clock signal as the first boosting stage; and a gate connected to a gate control node. An off-switch transistor,
A drain connected to the gate of the charge transfer transistor, a source connected to the output node of the boosting stage corresponding to a clock signal different from the first boosting stage, and a gate connected to the gate control node An on-switch transistor having,
Sub-charge transfer having a gate connected in series with the charge transfer transistor between the input node and the output node and connected to an output node of a boosting stage corresponding to a clock signal different from the first boosting stage Including a transistor,
A boosting circuit, wherein a connection point between the charge transfer transistor and the sub charge transfer transistor is connected to the gate control node. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boost stage stages each repeating a boost operation in response to the first and second clock signals;
A plurality of backflow prevention circuits respectively corresponding to the plurality of booster circuits;
An output terminal for outputting the boosted voltage,
Each of the plurality of backflow prevention circuits is responsive to one of an input node connected to the boosting stage train, an output node connected to the output terminal, and the first and second clock signals. An intermediate node to be boosted,
A first backflow prevention circuit, which is one of the plurality of backflow prevention circuits,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the intermediate node and receiving a clock signal corresponding to the first backflow prevention circuit at the other end;
Either the intermediate node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit or the input node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit And a connection switching unit connected to the gate of the charge transfer transistor. In claim 11,
The connection switching unit is
Voltage at the input node of the backflow prevention circuit corresponding to a clock signal whose absolute value at the input node of the backflow prevention circuit corresponding to the same clock signal as that of the first backflow prevention circuit is different from that of the first backflow prevention circuit The intermediate node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit is connected to the gate of the charge transfer transistor.
Voltage at the input node of the backflow prevention circuit corresponding to a clock signal whose absolute value at the input node of the backflow prevention circuit corresponding to the same clock signal as that of the first backflow prevention circuit is different from that of the first backflow prevention circuit When the absolute value is smaller than the absolute value, the booster circuit is characterized in that the input node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit is connected to the gate of the charge transfer transistor. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boost stage stages each repeating a boost operation in response to the first and second clock signals;
A plurality of backflow prevention circuits respectively corresponding to the plurality of booster circuits;
An output terminal for outputting the boosted voltage,
Each of the plurality of backflow prevention circuits is responsive to one of an input node connected to the boosting stage train, an output node connected to the output terminal, and the first and second clock signals. An intermediate node to be boosted,
A first backflow prevention circuit, which is one of the plurality of backflow prevention circuits,
A charge transfer transistor connected between the input node and the output node;
A boost capacitor having one end connected to the intermediate node and receiving a clock signal corresponding to the first backflow prevention circuit at the other end;
Either an input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit or an intermediate node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit And a connection switching unit connected to the gate of the charge transfer transistor. In claim 13,
The connection switching unit is
The drain connected to the gate of the charge transfer transistor, the source connected to the input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit, and the first backflow prevention circuit An off-switch transistor having a gate connected to the input node of the backflow prevention circuit corresponding to the different clock signals;
The drain connected to the gate of the charge transfer transistor, the source connected to the intermediate node of the backflow prevention circuit corresponding to the clock signal different from the first backflow prevention circuit, and the same as the first backflow prevention circuit And an on-switch transistor having a gate connected to an intermediate node of the backflow prevention circuit corresponding to the clock signal. In claim 13,
The connection switching unit is
A drain connected to the gate of the charge transfer transistor, a source connected to the input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit, and a gate connected to the output terminal An off-switch transistor having:
A drain connected to the gate of the charge transfer transistor, a source connected to an intermediate node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit, and a gate connected to the output terminal And an on-switch transistor. In claim 13,
The voltage at the intermediate node of the backflow prevention circuit corresponding to the first clock signal is compared with the voltage at the intermediate node of the backflow prevention circuit corresponding to the second clock signal, and the two are determined according to the comparison result. An analog comparison circuit that selects any one of the intermediate nodes of the backflow prevention circuit;
The connection switching unit is
The drain connected to the gate of the charge transfer transistor, the source connected to the input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit, and the intermediate selected by the analog comparison circuit An off-switch transistor having a gate connected to the node;
A drain connected to the gate of the charge transfer transistor, a source connected to an intermediate node of a backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit, and an intermediate selected by the analog comparison circuit And an on-switch transistor having a gate connected to the node. In claim 13,
The first backflow prevention circuit includes:
A sub-gate having a gate connected in series with the charge transfer transistor between the input node and the output node and connected to an intermediate node of a backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit. Further comprising a charge transfer transistor;
The connection switching unit is
A drain connected to the gate of the charge transfer transistor; a source connected to an input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit; a gate connected to a gate control node; An off-switch transistor having:
A drain connected to the gate of the charge transfer transistor, a source connected to an intermediate node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit, and a gate connected to the gate control node An on-switch transistor having
A boosting circuit, wherein a connection point between the charge transfer transistor and the sub charge transfer transistor is connected to the gate control node. A circuit that generates a boosted voltage by performing a boosting operation in response to first and second clock signals that fluctuate complementarily;
A plurality of boost stage stages each repeating a boost operation in response to the first and second clock signals;
A plurality of backflow prevention circuits respectively corresponding to the plurality of booster circuits;
An output terminal for outputting the boosted voltage,
Each of the plurality of backflow prevention circuits has an input node connected to the boost stage stage, and an intermediate node boosted in response to one of the first and second clock signals,
A first backflow prevention circuit, which is one of the plurality of backflow prevention circuits,
A charge transfer transistor connected between the input node and the intermediate node;
A boost capacitor having one end connected to the intermediate node and receiving a clock signal corresponding to the first backflow prevention circuit at the other end;
Either an input node of the backflow prevention circuit corresponding to the same clock signal as the first backflow prevention circuit or an intermediate node of the backflow prevention circuit corresponding to a clock signal different from the first backflow prevention circuit A connection switching unit connected to the gate of the charge transfer transistor;
A gate connected in series with the charge transfer transistor between the input node and the intermediate node and connected to the intermediate node of the backflow prevention circuit corresponding to a different clock signal from the first backflow prevention circuit A sub-charge transfer transistor,
A booster circuit, wherein a connection point between the charge transfer transistor and the sub charge transfer transistor is connected to the output terminal. In any one of Claims 13-18,
The first backflow prevention circuit includes:
The booster circuit further comprising a diode-connected transistor connected between the input node and the intermediate node. In any one of Claims 13-18,
The first backflow prevention circuit includes:
A booster circuit further comprising a diode-connected transistor connected between a voltage node receiving a power supply voltage or a ground voltage and the intermediate node. In claim 18,
The first backflow prevention circuit includes:
The booster circuit further comprising a diode connection transistor connected between a connection point between the charge transfer transistor and the sub charge transfer transistor and the intermediate node.

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