JP2008219056A - Semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device with a high nondefective product rate by assuring the KGD (Known-Good-Die) of each semiconductor chip easily when composing a packaged semiconductor device by incorporating a plurality of semiconductor chips, and to utilize the position, pitch, signal array of the terminal of each semiconductor chip, and the like as they are without any restrictions. <P>SOLUTION: A projection provided on a semiconductor chip mount sealing subsubstrate 100 is bonded onto a package substrate 10. Semiconductor bare chips 31, 32 are arranged in the space formed between the semiconductor chip mount sealing subsubstrate 100 and the package substrate 10, for wiring. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a package structure of a semiconductor device.

In an electronic device using a semiconductor device such as a terminal device (mobile phone) of a mobile communication system, it is always important how to increase the integration of the semiconductor device in order to reduce the size and weight. Up to now, when miniaturization of semiconductor circuits has been progressing smoothly, as many circuits as possible are made into one chip, and the advantages of reducing the mounting area, increasing the speed, and reducing the power consumption have been utilized. However, problems such as a rapid increase in manufacturing cost and a prolonged design and development period due to miniaturization of semiconductor circuits have become apparent.

Therefore, SIP (System in 3D) for mounting a plurality of semiconductor chips in three dimensions.
Package) technology is drawing attention. For example, as shown in FIG. 13, a semiconductor bare chip 30 is mounted on a package substrate 10, and another semiconductor bare chip 31 is mounted on the semiconductor bare chip 30, and these semiconductor bare chips 30, 31 and the package substrate 10 are A wire 60 is used for wire bonding (see Non-Patent Document 1).
Nikkei Electronics 2002, 2-11 no. 815 p108 "Part 1: If the chip is not good, there is a package"

As described above, the non-defective product rate of the SIP in which a plurality of semiconductor chips are contained in one package is a synergistic value of the good product rate of each semiconductor chip. The non-defective product rate is reduced to almost 50% (= 0.8 × 0.8 × 0.8). In particular, since the yield rate of low-priced chips such as DRAM is lower than the yield rate of logic semiconductor chips such as expensive CPUs, expensive semiconductor chips are wasted due to defects in low-priced semiconductor chips. There was a problem of end. Therefore, it is strongly desired that the semiconductor chip to be mounted on the SIP is a semiconductor chip (inspected good chip, KGD: Known-Good-Die) that has been verified in advance to be a good product.

Next, a method for acquiring KGD will be described. First, a predetermined probe inspection is performed on each semiconductor chip in the state of the semiconductor wafer. The semiconductor wafer is diced (cut) and separated into semiconductor chip pieces. Based on the result of the probe inspection, the semiconductor chips are selected, and only a good semiconductor chip is subjected to a screening inspection such as burn-in inspection (hereinafter referred to as BT). At this time, only good semiconductor chips are accommodated in a chip tray or carrier socket for BT, BT in a chip state is performed using a dedicated jig for KGD and a dedicated device, and after further sorting, a chip tray for BT Alternatively, the semiconductor chip is taken out from the carrier socket, and the non-defective semiconductor chip is transferred to a shipping tray for packing and shipping. Since the semiconductor chip piece (bare chip) is formed very thin, it is easy to break, and a very delicate operation is required for the operation of the socket, probe, and tester used in the sorting test.

In order to solve this problem, for example, there is a method as disclosed in JP-A-2002-40095.

In a semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095, an electrode formed on the surface of a first resin-sealed package formed by resin-sealing a semiconductor chip is connected to the electrode of the semiconductor chip and mounted. And a test area for connecting a test device. An example in which the semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095 is applied to SIP is shown in FIG. 14 and will be described below with reference to this.

As shown in FIG. 14, when the semiconductor package 20 is mounted on the package substrate 10, the semiconductor package 21 and the semiconductor package 22 are mounted on a lead frame connected to an electrode on the package substrate 10 and sealed. The resin 80 is sealed with resin. At this time, the semiconductor package 21 and the semiconductor package 22 incorporate the semiconductor bare chip 30 and the semiconductor bare chip 31, respectively, and are sealed with a sealing resin 81, respectively. However, when the semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095 is applied to SIP, the electrode 40 of the semiconductor package 21 is connected to the electrode 41 of the semiconductor package 22 on which the semiconductor package 21 is mounted by the wire 60. Has been. Further, the electrode 41 of the semiconductor package 22 and the lead frame are connected by a wire 61. As described above, the resin-sealed package (semiconductor package 21 and semiconductor package 22) disclosed in Japanese Patent Laid-Open No. 2002-40095 is easier to handle because it is resin-sealed than the conventional bare chip. There is an effect that the fineness required for the operation of the socket, probe, and tester used in the screening test is reduced.

Further, Japanese Patent Application Laid-Open No. 2002-40095 has a configuration in which the electrodes that are damaged in the sorting test at the time of mounting are not used by dividing the electrodes into a test region and a mounting region. The test electrode and the mounting electrode have the following requirements.

First, for the test electrodes, the electrode pitch is set to about 0.8 mm in a BGA type package, for example. If this level of electrode pitch can be realized, the fineness required for the operation of the socket, probe, and tester used in the sorting test will be sufficient to measure the CSP. On the other hand, the usefulness of the mounting electrode is demonstrated by making the electrode pitch equal to the electrode pitch of a normal bare chip. This pitch is about 130 μm, for example. If this level of electrode pitch can be realized, the assembly apparatus or the like can be used without any particular changes.

In order to enable wiring with a narrow pitch for mounting as described above, a method using an interposer using a glass substrate is disclosed in Japanese Patent Application Laid-Open No. 2003-249606. However, there is a limit to simply providing wiring with a narrow pitch in order to give freedom to both the test electrode arrangement and the mounting electrode arrangement, and there is a problem that any test electrode arrangement and mounting electrode arrangement cannot be realized. there were.

On the other hand, Japanese Patent Application Laid-Open No. 2001-196529 provides a wiring method capable of connecting a pad electrode of a semiconductor chip to an arbitrary electrical connection portion. A wiring technique disclosed in Japanese Patent Laid-Open No. 2001-196529 is shown in FIG. In FIG. 15, the pad electrode disposed in the vicinity of the edge extending in the arrow YY ′ direction of the semiconductor bare chip 30 and the pad electrode disposed in the vicinity of the edge extending in the arrow XX ′ direction in the package substrate 10 They are connected via the internal wiring of the bare chip 31.

As described above, SIP is realized, but in order to realize a chip-on-chip in which a plurality of chips are three-dimensionally stacked, it is necessary to provide a gap in the stacked chips. This gap functions to radiate heat from the semiconductor element and to protect the semiconductor element during mounting. In addition, this gap prevents the bonding pads of the lower chip from being separated and making wire bonding impossible if the chips to be stacked are the same or nearly the same size and the chips are stacked directly. To do. The means for providing a gap between the stacked chips is called a spacer.

The present invention relates to a package structure of a semiconductor device including a substrate-like or frame-like base material on which a plurality of semiconductor chips are mounted, and a plurality of semiconductor chips mounted on the base material, and the terminals of the semiconductor chips to be mounted are An internal electrode to be connected; a mounting electrode to be connected to another component during mounting; a test electrode to which a terminal of a test apparatus is connected during testing; and the internal electrode, the mounting electrode, and the test electrode A semiconductor chip mounting sub-board in which a semiconductor chip is mounted on a sub-board on which a multilayer wiring to be electrically connected is formed, and the semiconductor chip mounting sub-board is mounted on the base material together with other semiconductor chips, A semiconductor chip mount sub-board and another semiconductor chip are sealed with a resin together with the base material.

Further, according to the present invention, the semiconductor chip mount sub-board is formed by resin-sealing one or more semiconductor chips mounted on the semiconductor chip mount sub-board together with the semiconductor chip mount sub-board, separately from the resin sealing with respect to the base material. It is characterized by being stopped.

According to the present invention, in the semiconductor chip mount sub-substrate formed by resin-sealing one or more semiconductor chips mounted on the semiconductor chip mount sub-substrate together with the semiconductor chip mount sub-substrate, a protrusion is formed on the resin-encapsulated portion. It is characterized by providing.

The present invention is characterized in that a protrusion is provided on the semiconductor chip mount sub-board.

Further, the present invention is characterized in that the mounting pitch of the mounting electrodes and the testing electrode are different from each other in the semiconductor chip mount sub-board.

In addition, the present invention is characterized by comprising a sub-substrate on which a plurality of electrodes and a multilayer wiring for electrically connecting the electrodes are formed separately from the semiconductor chip mount sub-substrate.

According to the present invention, the semiconductor chip mount sub-board comprises an internal electrode, a mounting electrode, and a test electrode. When testing the semiconductor chip mount sub-board, by using the test electrode, Tests can be performed with the conventional socket method, and the test cost can be reduced, and when mounting the semiconductor chip mount sub-board, the conventional mounting apparatus can be used by using the mounting electrodes, and the mounting cost can be reduced. . Furthermore, by realizing the interconnection between the internal electrode, the mounting electrode, and the test electrode with a multilayer wiring, the arrangement of the internal electrode, the arrangement of the test electrode, and the arrangement of the mounting electrode Each can be set arbitrarily, and for the semiconductor chips having various pad arrangements, the arrangement of the test electrodes suitable for the test method and the arrangement of the mounting electrodes suitable for the mounting conditions can be selected.

Further, according to the present invention, the resin sealing of the semiconductor chip mount sub-substrate and the resin sealing of the semiconductor chip mount sub-substrate after the resin sealing, the other semiconductor chip, and the base material are separately performed. The handling of the semiconductor chip mounted sub-board after the resin sealing is further simplified, the fineness required for the test apparatus can be reduced, and the test cost can be reduced.

In addition, according to the present invention, by providing a protrusion on the resin-sealed portion of the semiconductor chip mount sub-board, the protrusion can be used as a spacer, so that the spacer insertion step can be omitted.

Further, according to the present invention, by providing a protrusion on the semiconductor chip mount sub-board, the protrusion can be used as a spacer, so that the spacer insertion step can be omitted.

According to the invention, the test electrode suitable for the test method is set by setting the arrangement pitch of the mounting electrodes and the arrangement pitch of the test electrodes of the semiconductor chip mount sub-board different from each other. And an arrangement pitch of mounting electrodes suitable for the mounting conditions can be selected.

In addition, according to the present invention, in addition to the semiconductor chip mount sub-board, a sub-board on which a plurality of electrodes and a multi-layer wiring for electrically connecting the electrodes are provided can be connected by wires. Beyond the range, electrical connection between the semiconductor chip and the substrate can be realized.

FIG. 1 shows a structure of a semiconductor chip mount sealing sub-substrate 100 according to the present invention. FIG. 2 is a cross-sectional view of FIG. The semiconductor bare chip 30 is mounted on the interposer 70, the spacer 90 is laminated below it, and the semiconductor bare chip 31 is laminated below it. A semiconductor chip mount sub-substrate 100 is obtained by sealing the semiconductor chip mount sub-substrate 50 with a resin.

FIG. 3 is a top view of the interposer 70 shown in FIG. 2, in which the test electrode 110 and the mounting electrode 120 are provided on the surface thereof. The test electrodes 110 are arranged in a 14 × 14 array, for example, and have a pitch of 0.8 mm. This is the same level as the electrode pitch of the CSP chip. Therefore, the measurement for these test electrodes can be performed by a conventional socket method. For example, 96 mounting electrodes 120 are arranged on each side and have a pitch of 130 μm. This is the same level as the electrode pitch of the bare chip. Accordingly, the wiring from the mounting electrode 120 to the lead frame can be performed using a conventional apparatus.

FIG. 4 is a bottom view of the interposer 70 shown in FIG. Wiring is performed from the semiconductor bare chip 30 provided on the interposer 70 to the internal electrode 130. For example, 36 internal electrodes 130 are provided on one side and have a pitch of 160 μm.

Interconnection between the internal electrode 130, the test electrode 110, and the mounting electrode 120 is realized by the internal wiring of the interposer 70. FIG. 5 shows a first layer connection pattern for interconnecting the internal electrode 130 and the test electrode 110. FIG. 6 shows a second layer connection pattern for interconnecting the test electrode 110 and the mounting electrode 120. By using two layers, the internal electrode group, the test electrode group, and the mounting electrode group are connected to each other without increasing the area of the substrate. As described above, by arranging the wiring in the interposer in multiple layers, any test electrode arrangement and mounting electrode arrangement can be realized.

FIG. 7 shows an application of the idea of Japanese Patent Application Laid-Open No. 2001-196529 that arbitrary electrodes can be connected by forming a multi-layer wiring in the interposer. The semiconductor bare chip 30 in FIG. 7 corresponds to the semiconductor bare chip 30 in FIG. 15, and the interposer 70 in FIG. 7 plays the role of the semiconductor bare chip 31 in FIG. 15. That is, the internal wiring of the interposer 70 can be electrically connected to the package substrate 10 beyond the range that can be connected from the semiconductor bare chip 30 with a wire.

FIG. 8 shows an example in which the semiconductor chip mount sealing sub-substrate 100 and the semiconductor bare chip 34 are made into SIP. In this case, since the semiconductor chip mount sealing sub-board 100 is almost the same size as the semiconductor bare chip 34, the spacer 90 is placed between the semiconductor chip mount sealing sub-board 100 and the semiconductor bare chip 34 so that the bonding pad portion of the lower chip is not covered. Inserted in between.

Although the spacer 90 is used in FIG. 8, the semiconductor chip mount sealing sub-substrate 100 may be provided with a protrusion serving as a spacer. FIG. 9 shows a semiconductor chip mount sealing sub-substrate 100 having protrusions. This protrusion can be realized by making the mold mold into a desired shape. This protrusion is bonded onto the semiconductor bare chip 32 to secure a wiring space from the semiconductor bare chip 32 and a wiring space from the semiconductor bare chip 31.

FIG. 10 shows another embodiment in which a protrusion is provided on the semiconductor chip mount sealing sub-substrate 100 as in FIG. In FIG. 9, the protrusion provided on the semiconductor chip mount sealing sub-substrate is bonded onto the semiconductor bare chip 32, but in FIG. 10, the protrusion provided on the semiconductor chip mount sealing sub-substrate 100 is bonded onto the package substrate 10. is doing. Semiconductor bare chips 31 and 32 are arranged in a space formed between the semiconductor chip mount sealing sub-substrate 100 and the package substrate 10 to enable wiring.

In FIG. 11, the semiconductor chip mount sub-board 50 is stacked on the package board 10 via the spacer 90. The semiconductor bare chip 34 is mounted in advance on the semiconductor chip mount sub-board 50. In addition to the semiconductor chip mount sub-substrate 50, the semiconductor bare chip 32 and the semiconductor bare chip 33 are stacked and arranged, and then resin sealing is performed collectively.

Although the semiconductor chip mount sub-board 50 of FIG. 11 is laminated via the spacer 90, the interposer 70 may be provided with a protrusion, which may serve as a spacer. FIG. 12 shows a structure in which the interposer 70 is provided with protrusions. Even in this case, sealing can be performed in a lump.

1 is an external view of a semiconductor chip mount sealing sub-board according to the present invention. Sectional drawing of the semiconductor chip mound sealing sub-board | substrate of FIG. FIG. 3 is a top view of the interposer 70 shown in FIG. 2. The bottom view of the interposer 70 shown in FIG. A connection pattern of the first layer in the interposer 70 that interconnects the internal electrode 130 and the test electrode 110. A connection pattern of the second layer in the interposer 70 that interconnects the test electrode 110 and the mounting electrode 120. The example which enables the electrical connection to the package board | substrate 10 exceeding the range which can be connected with a wire from the semiconductor bare chip 30 by the internal wiring of the interposer 70 based on this invention. The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chip 34 based on this invention. The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chips 31 and 32 which comprised the protrusion based on this invention. The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chips 31 and 32 which comprised the protrusion based on this invention. An example in which the semiconductor chip mount sub-substrate 50 according to the present invention is stacked on the package substrate 10 via the spacer 90 and is encapsulated together with the semiconductor bare chips 32 and 33 with resin. An example in which a semiconductor chip mount sub-board 50 having an interposer 70 having protrusions is stacked on a package board 10 and sealed together with semiconductor bare chips 32 and 33 according to the present invention. Example of conventional SIP. Example of conventional SIP. Example of conventional SIP.

Explanation of symbols

10-package substrate 20-semiconductor package 21-semiconductor package 22-semiconductor package 30-semiconductor bare chip 31-semiconductor bare chip 32-semiconductor bare chip 33-semiconductor bare chip 34-semiconductor bare chip 40-electrode 41-electrode 50-semiconductor chip mount sub-substrate 60 -Wire 61-Wire 70-Interposer 80-Sealing resin 81-Sealing resin 90-Spacer 100-Semiconductor chip mount sealing sub-board 110-Test electrode 120-Mounting electrode 130-Internal electrode

Claims (12)

A package substrate (10);
A first semiconductor chip (32) mounted on the surface of the package substrate (10);
An interposer (70) having an upper surface and a lower surface arranged in parallel with the package substrate (10);
In a semiconductor package comprising a second semiconductor chip (34) mounted on the lower surface of the interposer (70) and arranged to face the first semiconductor chip,
a) On the lower surface of the interposer (70), a plurality of first electrodes (130) for electrical connection with the second semiconductor chip (34) are formed,
b) On the upper surface of the interposer (70), a plurality of second electrodes (110) arranged in a matrix at a pitch larger than the electrode pitch of the second semiconductor chip (34), and the interposer A plurality of third electrodes (120) arranged in a row at a smaller pitch than the plurality of second electrodes (110) along one side of the poser (70);
c) The package substrate (10) and the plurality of third electrodes (120) of the interposer (70) are electrically connected,
d) the plurality of first electrodes (130), the plurality of second electrodes (110), and the plurality of third electrodes (120) are electrically interconnected;
A semiconductor package characterized by that. The semiconductor package according to claim 1,
The semiconductor package, wherein the second electrode has a circular shape and the third electrode has a rectangular shape. The semiconductor package according to claim 1,
A semiconductor package, wherein electrical connection between the package substrate (10) and the plurality of third electrodes (120) of the interposer (70) is made by wiring. The semiconductor package according to claim 1,
A semiconductor package, wherein the second semiconductor chip (34) and the plurality of first electrodes (130) are electrically connected by wiring. The semiconductor package according to claim 1,
The interposer (70) has a plurality of fourth electrodes arranged substantially in a matrix corresponding to the plurality of second electrodes (110) on the back surface of the portion corresponding to the plurality of second electrodes (110). Electrode (110) is formed,
The semiconductor package, wherein the plurality of fourth electrodes and the plurality of first electrodes are electrically connected by a first connection pattern formed on a lower surface of the interposer (70). . The semiconductor package according to claim 1,
A second connection pattern for electrically connecting the plurality of second electrodes (110) and the plurality of third electrodes (120) is formed on the upper surface of the interposer (70). A semiconductor package characterized by A package substrate (10);
A first semiconductor chip (34) mounted on the surface of the package substrate (10) and having a bonding pad portion;
A first wire for electrically connecting the bonding pad portion of the first semiconductor chip (34) and the package substrate (10);
A spacer (90) disposed on a surface of the first semiconductor chip (34) so that the bonding pad portion of the first semiconductor chip (34) is not covered;
The semiconductor chip mount sealing sub-substrate (100) mounted on the spacer (90) and larger than the spacer (90),
The semiconductor chip mount sealing sub-substrate (100) includes:
a) a second semiconductor chip (30) and b) having an upper surface and a lower surface, on which the second semiconductor chip (30) is mounted and electrically connected to the second semiconductor chip (30). A plurality of first electrodes (130) connected to each other are formed, and a plurality of first electrodes arranged in a matrix at a pitch larger than the electrode pitch of the second semiconductor chip (30) are formed on the upper surface. An interposer in which two electrodes (110) and a plurality of third electrodes (120) arranged in a line at a smaller pitch than the plurality of second electrodes (110) along one side are formed. 70)
c) a first resin that seals the lower surface of the interposer (70) and the second semiconductor chip (30);
The semiconductor chip mount sealing sub-substrate (100) is disposed such that the lower surface of the interposer (70) faces the spacer (90),
The semiconductor package, wherein the third electrode (120) and the package substrate (10) are electrically connected by a second wire. 8. The semiconductor package according to claim 7, further comprising a surface of the package substrate (10), the first semiconductor chip (34), the first wire, the spacer (90), and the semiconductor chip mount. A semiconductor package comprising: a second resin that is sealed separately from the first resin and seals the sealing sub-substrate (100) and the second wire. The semiconductor package according to claim 7,
The semiconductor package, wherein the second electrode (110) has a circular shape and the third electrode (130) has a rectangular shape. The semiconductor package according to claim 7,
A semiconductor package, wherein the second semiconductor chip (30) and the plurality of first electrodes (130) are electrically connected by wiring. The semiconductor package according to claim 7,
The interposer (70) has a plurality of rows arranged substantially in a matrix corresponding to the plurality of second electrodes (110) on a lower surface of a portion corresponding to the plurality of second electrodes (110). A fourth electrode (110) is formed;
The semiconductor package, wherein the plurality of fourth electrodes and the plurality of first electrodes are electrically connected by a first connection pattern formed on a lower surface of the interposer (70). . The semiconductor package according to claim 7,
A second connection pattern for electrically connecting the plurality of second electrodes (110) and the plurality of third electrodes (130) is formed on an upper surface of the interposer (70). A semiconductor package characterized by