JP2008218836A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which includes a full silicide gate electrode and easily produces a CMOS device improved in electric characteristics. <P>SOLUTION: The method includes steps of: forming a first polysilicon gate electrode on a high dielectric constant gate insulating film on a first conductive-type region in a semiconductor substrate and a second polysilicon gate electrode on the high dielectric constant gate insulating film on a second conductive-type region; injecting an element of a silicification reaction suppression metal suppressing silicification reaction not into the second polysilicon gate electrode but into the first polysilicon gate electrode; forming, at least on the first and second polysilicon gate electrodes, a film of a metal to be silicified after the injection of the element of the silicification reaction suppression metal; and silicifying the first and second pilysilicon gate electrodes by applying thermal treatment to the semiconductor substrate with the film of the metal formed thereon, as full silicide electrodes, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a CMOS type semiconductor device having a full silicide gate electrode.

  Conventionally, in a complementary metal oxide semiconductor (CMOS) device, a silicon oxynitride film is widely used as a gate insulating film, and p-type and n-type polysilicon are widely used as a material for a gate electrode. When polysilicon is used as the material of the gate electrode, the optimum threshold value control for each transistor is made possible by adjusting the implantation type, implantation amount, etc. of impurities. However, when polysilicon is used as the material for the gate electrode, there is a problem that the polysilicon itself is depleted when an electric field is applied, and the effective electrical gate insulating film thickness increases.

  Further, in order to improve device performance, a high dielectric constant (high-k) gate insulating film made of a high dielectric constant (high-k) material typified by HfSiON is used as a gate insulating film instead of a silicon acid (nitride) film. The practical application of is being studied. However, when a high-k material and a polysilicon electrode are used in combination, a threshold voltage rises significantly during transistor operation particularly in a p-type MISFET (Metal Insulator Semiconductor field effect transistor) (see, for example, Reference 1) The problem that device performance deteriorates occurs.

  In order to solve such drawbacks of the polysilicon gate electrode, a structure using a metal silicide for the gate electrode (Fully Silicided (FUSI) gate structure) has been studied (for example, see Document 2). In the full silicide gate structure, a silicide film such as Ni is formed on polysilicon and subjected to heat treatment to form a silicide film, and the silicide film is used as a gate electrode. Thereby, since the depletion phenomenon of the gate electrode as described above can be suppressed, an increase in the effective electrical gate insulating film thickness can be eliminated.

  Further, when a high-k gate insulating film is used as the gate insulating film, the effective work function can be controlled by the material for forming the full silicide gate electrode, the phase composition, the crystal structure, the film thickness, and the like. (See, for example, Reference 3), and a desired threshold voltage can be obtained in each of the p-type and n-type transistors.

C. Hobbs et al., “Fermi Level Pinning at the PolySi / Metal Oxide Interface“ VLSI Symp.Tech.Dig., 2003 p9 J. Kedzierski et al., “Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)“ IEDM Tech. Dig., (2002) p247 K. Takahashi et al., “Dual Workfunction Ni-Silicide / HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices” IEDM Tech. Dig., (2004) p91

  By the way, as described above, when a high dielectric constant (high-k) gate insulating film and a full silicide (FUSI) gate structure are used, it is necessary to change the composition of the full silicide film used for the gate electrode between the pMISFET and the nMISFET. There is. Therefore, conventionally, in order to form a FUSI gate having a desired composition for each of the p-type and n-type, the polysilicon film to be silicidated is partially etched back, or the silicided metal is partially redeposited. By changing the film thickness ratio between the p-type region and the n-type region by such a method, silicidation reaction is performed to form silicide films having different compositions.

  For this reason, when the polysilicon film to be silicidized is partially etched back, problems such as complicated processes and deterioration of the transistor shape due to the etch back process occur. Further, when the metal silicide is partially redeposited, it is necessary to partially form a film that protects a region that is not redeposited, and there is a concern that the process may be complicated and the apparatus may be contaminated with impurities.

  The present invention has been made in view of the above, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can easily manufacture a CMOS device having a full silicide gate electrode and excellent electrical characteristics. To do.

  According to one embodiment of the present invention, in a method of manufacturing a semiconductor device having a CMOS transistor using a metal silicide film for a gate electrode and a high dielectric constant material for a gate insulating film, a polysilicon layer reacted with nickel (Ni) By previously injecting an element that exhibits a silicidation reaction suppressing effect, a gate electrode made of a different NiSix phase can be formed on each of the p-type and n-type MISFETs by a simple process compared to the prior art. A method for manufacturing a formed semiconductor device is provided.

  According to an embodiment of the present invention, in a method of manufacturing a semiconductor device having a CMOS transistor using a metal silicide film for a gate electrode and a high dielectric constant material for a gate insulating film, the threshold values of pMISFET and nMISFET are different from each other. It is possible to provide a method for manufacturing a semiconductor device that can easily form a transistor having an optimum threshold value for each, and can easily manufacture a semiconductor device having excellent electrical characteristics and reliability. There is an effect.

  Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) according to a first embodiment of the present invention, and is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) manufactured by applying the present invention. . First, the structure of the semiconductor device will be described. A semiconductor device 10 according to the present embodiment is a semiconductor device (CMOS device) having a CMOS transistor, and an element isolation film 102 for isolating each transistor element and a MIS FET on the surface layer of a silicon substrate 101 as a semiconductor substrate. A pMISFET 100p and an nMISFET 100n that are (Metal Insulator Semiconductor Field Effect Transistors) are formed.

  The pMISFET 100p is formed in the pMISFET region ap of the silicon substrate 101, which is a semiconductor substrate, and the channel region is defined in the active region where the transistor elements are formed between the element isolation films 102 on the surface layer of the silicon substrate 101. Thus, a pair of source / drain regions 103p are formed at a distance from each other.

  A silicide layer 107p in which nickel (Ni) is silicided is formed on the source / drain region 103p. Then, in the channel region defined by the pair of source / drain regions 103p on the silicon substrate 101, a high dielectric constant (high-k) gate made of a high dielectric constant material is provided from the silicon substrate 101 side as shown in FIG. An insulating film 105p and a nickel (Ni) full silicide gate electrode 104p formed on the high dielectric constant (high-k) gate insulating film 105p are formed.

As the high dielectric constant (high-k) gate insulating film 105p, for example, hafnium silicate (HfSiO), hafnium aluminate (HfAlO), or those obtained by nitriding these are used. The nickel (Ni) full silicide gate electrode 104p is a nickel (Ni) rich nickel (Ni) full silicide gate electrode having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, or Ni ₃ Si.

  A sidewall 106p made of a nitride film is formed on the sidewalls of the high dielectric constant (high-k) gate insulating film 105p and the nickel (Ni) full silicide gate electrode 104p.

  On the other hand, the nMISFET 100n is formed in the nMISFET region ap of the silicon substrate 101, which is a semiconductor substrate, and the channel region is defined in the active region where the transistor element is formed between the element isolation films 102 on the surface layer of the silicon substrate 101. Thus, a pair of source / drain regions 103n are formed at a distance from each other.

  A silicide layer 107n obtained by siliciding nickel (Ni) is formed on the source / drain region 103n. Then, in the channel region defined by the pair of source / drain regions 103n on the silicon substrate 101, a high dielectric constant (high-k) gate made of a high dielectric constant material is provided from the silicon substrate 101 side as shown in FIG. An insulating film 105n and a nickel (Ni) full silicide gate electrode 104n formed on the high dielectric constant (high-k) gate insulating film 105n are formed.

  As the high dielectric constant (high-k) gate insulating film 105n, for example, hafnium silicate (HfSiO), hafnium aluminate (HfAlO), or a material obtained by nitriding these is used. The nickel (Ni) full silicide gate electrode 104n is a nickel (Ni) full silicide gate electrode having a composition of NiSi (nickel monosilicide).

  A sidewall 106n made of a nitride film is formed on the sidewalls of the high dielectric constant (high-k) gate insulating film 105n and the nickel (Ni) full silicide gate electrode 104n.

  An interlayer insulating film 108 is formed so as to cover the element isolation film 102 and the silicided silicide layers 107p and 107n.

  In the semiconductor device 10 according to the present embodiment configured as described above, the high dielectric constant (high-k) gate insulating films 105p and 105n made of a high dielectric constant material are used as the gate insulating film. When the gate insulating film (silicon oxide film) becomes thinner with the miniaturization of semiconductor devices, electrical characteristics due to the generation of leakage current due to tunneling and diffusion of impurities from the gate electrode into the insulating film, etc. Decrease and reliability decrease.

  However, in the semiconductor device 10 according to the present embodiment, the high dielectric constant (high-k) gate insulating films 105p and 105n that can cope with the miniaturization of the semiconductor device without deteriorating the electrical characteristics are used as the gate insulating film. Yes. Therefore, in the semiconductor device according to the present embodiment, a semiconductor device having excellent electrical characteristics and reliability is realized.

  In addition, the semiconductor device 10 according to the present embodiment has a full silicide gate structure using metal silicide as a gate electrode. By having such a full silicide gate structure, the semiconductor device 10 according to the present embodiment is effective due to the depletion of the gate electrode material as in the case where a polysilicon-based material is used as the gate electrode material. An increase in the thickness of the electrical gate insulating film is effectively suppressed. Therefore, in the semiconductor device 10 according to the present embodiment, a semiconductor device capable of reducing the effective gate insulating film thickness is realized.

In the semiconductor device 10 according to the present embodiment, the gate electrode of the pMISFET 100p is nickel (Ni) -rich nickel (Ni) full silicide having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, Ni ₃ Si, or the like. is the gate electrode 104 p, the gate electrode in nMISFET100n has been nickel (Ni) fully silicided gate electrode 104n having a composition of NiSi (nickel mono silicide) or NiSi _2.

  Thus, in the semiconductor device 10 according to the present embodiment, the nickel (Ni) full silicide gate electrode 104p and the nickel (Ni) full silicide gate electrode 104n are composed of materials having different compositions. Due to the difference in composition, the threshold value is controlled to be different between the pMISFET 100p and the nMISFET 100n, and transistors each having an optimum threshold value are formed.

  Therefore, in the semiconductor device 10 according to the present embodiment, the pMISFET 100p and the nMISFET 100n are each provided with a gate electrode made of nickel (Ni) silicide having a different composition, and transistors each having an optimum threshold value are formed.

  Next, a method for manufacturing the semiconductor device 10 according to the present embodiment as described above will be described with reference to the drawings shown in FIGS. First, as shown in FIG. 2A, for example, an element isolation film 102 is formed on the surface of a silicon substrate 101 whose surface layer portion has a (100) plane orientation by a shallow trench isolation (STI) method.

  Subsequently, using an ion implantation method, an n-type well is formed in the pMISFET region ap of the silicon substrate 101 and a p-type well is formed in the nMISFET region an (not shown). A device formation region is formed.

  Subsequently, the surface of the silicon substrate 101 is cleaned using a known cleaning technique, and, for example, using a metal organic chemical vapor deposition (MOCVD) method, as shown in FIG. A metal oxide film 111 for a gate insulating film made of a material is formed. As the metal oxide film 111 made of this high dielectric constant material, for example, hafnium silicate (HfSiO), hafnium aluminate (HfAlO), or those obtained by nitriding these can be used.

  Next, a polysilicon film 112 for a gate electrode is deposited on the metal oxide film 111 as shown in FIG. At this time, the polysilicon film 112 may be doped by performing gate implantation. Then, a hard mask 113 made of a silicon nitride film or the like is formed on the polysilicon film 112 as shown in FIG. This hard mask 113 prevents doping and silicidation reactions to the polysilicon gate electrodes 112ap and 112an when forming source / drain regions 103p and 103n, which will be described later, and forming nickel (Ni) silicide layers 107p and 107n. Preventive layer (mask).

  Thereafter, through a known transistor formation step, the formation of the transistor is performed. That is, the high dielectric constant (high-k) gate insulating films 105p and 105n and the polysilicon gate electrodes 112ap and 112an are formed using a known photolithography technique and etching technique, and the hard mask 113 is replaced with the polysilicon gate electrode 112ap. , 112an to form the hard masks 113ap, 113an. Here, the thicknesses of the polysilicon gate electrode 112ap and the polysilicon gate electrode 112an in the pMISFET region ap and the nMISFET region an are substantially the same. Next, source / drain regions 103p and 103n are formed by a known technique as shown in FIG. A source / drain extension layer may be provided.

  Next, as shown in FIG. 2C, sidewalls 106p made of a nitride film are formed on the sidewalls of the high dielectric constant (high-k) gate insulating film 105p, the polysilicon gate electrode 112ap, and the hard mask 113ap. Further, a sidewall 106n made of a nitride film is formed on the sidewalls of the high dielectric constant (high-k) gate insulating film 105n, the polysilicon gate electrode 112an, and the hard mask 113an.

  A nickel (Ni) silicide layer 107p obtained by siliciding nickel (Ni) by performing a silicidation heat treatment by volume of a nickel film as a metal that undergoes a silicidation reaction on the entire surface of the silicon substrate 101 is shown in FIG. Thus, a nickel (Ni) silicide layer 107n obtained by siliciding nickel (Ni) is formed on the source / drain region 103n as shown in FIG.

  Next, an interlayer insulating film 108 is deposited on the entire surface of the silicon substrate 101, and using a CMP (Chemical Mechanical Polishing) technique, hard masks 113ap and 113an on the polysilicon gate electrodes 112ap and 112an as shown in FIG. The interlayer insulating film 108 is polished until is exposed. Next, the hard masks 113ap and 113an on the polysilicon gate electrodes 112ap and 112an are removed using photolithography and etching techniques to expose the polysilicon gate electrodes 112ap and 112an as shown in FIG. 2-5. .

  Next, a resist film is formed on the entire surface of the silicon substrate 101, and a resist mask 114 having an nMISFET region an opened as shown in FIG. 2-6 is formed using a photoengraving technique. Then, using the resist mask 114 as a mask, as shown in FIG. 2-7, an element that suppresses the silicidation reaction (silicide reaction inhibition element) such as fluorine (F) by ion implantation with respect to the nMISFET region an. ) Is implanted (pre-doping). Thereby, the polysilicon gate electrode 112b into which the silicidation reaction suppressing element is implanted (pre-doped) is formed.

  Here, as shown in FIG. 2-6, a silicidation reaction suppressing element is implanted into the nMISFET region an using a resist mask 114 having an opening in the nMISFET region an. A silicidation reaction suppressing element may be implanted into the silicon gate electrode 112an.

The ion implantation is performed with an implantation energy in the range of 2 keV to 30 keV. Further, in order to prevent the silicidation reaction suppressing element implanted into the polysilicon gate electrode 112an from penetrating into the silicon substrate 101, it is preferable to change the implantation energy depending on the type of element. The amount of silicidation reaction suppressing element implanted is preferably in the range of 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .

  Further, when the silicidation reaction suppressing element is implanted into the nMISFET region an, the pMISFET region ap is covered with a resist mask, and ion implantation of the silicidation reaction inhibiting element is not performed on the pMISFET region ap. That is, when the silicidation reaction suppressing element is implanted into the nMISFET region an, the silicidation reaction inhibiting element is not ion-implanted into the polysilicon gate electrode 112ap.

  Next, the resist mask 114 is removed, and for example, a nickel (Ni) film 115 is deposited on the entire surface of the silicon substrate 101 as shown in FIG. Then, the silicidation heat treatment and the selective removal of unreacted nickel (Ni) are performed by controlling conditions such as the temperature, time, frequency, and selective nickel (Ni) removal timing of the silicidation heat treatment. Here, a case where nickel (Ni) is used as a metal that undergoes a silicidation reaction will be described as an example, but the metal that undergoes a silicidation reaction is not limited to this, and platinum (Pt), cobalt (Co), Metals such as titanium (Ti), hafnium (Hf), erbium (Er), zirconium (Zr), and tantalum (Ta) can also be used.

Here, the thickness of the nickel (Ni) film 115 for siliciding the polysilicon gate electrodes 112a and 112b is substantially the same in the pMISFET region ap and the nMISFET region an. The silicidation heat treatment conditions are also the same in the pMISFET region ap and the nMISFET region an. In this way, by combining the silicidation reaction between the polysilicon gate electrodes 112a and 112b and nickel (Ni) by heat treatment and the selective removal of unreacted nickel (Ni), Ni _x Si _y ( Nickel (Ni) silicide having a composition ratio of x and y is an integer) is formed.

At this time, by controlling conditions such as the thickness of the polysilicon gate electrode 112ap, the deposition thickness of the nickel (Ni) film, the temperature, time, number of times of silicidation heat treatment, and the timing of selective nickel (Ni) removal. By controlling the composition ratio of Ni _x Si _y (x and y are integers), nickel (Ni) such as Ni ₃₁ Si ₁₂ , Ni ₂ Si and Ni ₃ Si is formed in the pMISFET region ap as shown in FIG. 2-9. A rich nickel (Ni) full silicide gate electrode 104p is formed.

On the other hand, the fluorine (F) element is ion-implanted into the nMISFET region an as described above. It is known that when fluorine (F) element is implanted into silicon (Si), the diffusion rate of nickel (Ni) into silicon (Si) is suppressed (for example, “M. Tsuchiaki et al. al., “Suppression of Thermally Induced Leakage of NiSi-Silicide Shallow Junctions by Pre-Silicide Fluorine Implantation” JJAP, 44 (2005) p1673 ”). Therefore, the thickness of the polysilicon gate electrode 112b (the thickness of the original polysilicon gate electrode 112an), the deposition thickness of the nickel (Ni) film, the temperature, time, and number of times of silicidation heat treatment, and selective nickel (Ni) By controlling conditions such as the timing of removal, nickel (Ni) silicide having a composition ratio of Ni _x Si _y (x and y are integers) is formed as a gate electrode.

  At this time, in the nMISFET region an into which the fluorine (F) element is implanted, the nickel (Ni) full silicide gate electrode 104p is formed as shown in FIG. 2-9 due to the silicidation reaction suppression effect of the fluorine (F) element. . The nickel (Ni) full silicide gate electrode 104p has a composition of NiSi (nickel monosilicide). Thus, the semiconductor device 10 according to the present embodiment shown in FIG. 1 can be formed.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, before the silicide metal for siliciding the polysilicon gate electrode 112a is deposited, the polysilicon gate electrode 112a in the nMISFET region an is applied to the polysilicon gate electrode 112a. Then, fluorine (F) element that suppresses silicidation reaction is ion-implanted (pre-doping). Then, for example, a nickel (Ni) film 115 is deposited on the entire surface of the silicon substrate 101 as a metal that undergoes a silicidation reaction, and a silicidation heat treatment is performed.

As a result, the gate polysilicon sufficiently undergoes a silicidation reaction in the polysilicon gate electrode 112ap of the pMISFET region ap in which no fluorine (F) element is implanted, so that the metal (nickel) rich (eg, Ni ₃₁ Si ₁₂ , Ni ₂₎ A nickel (Ni) full silicide gate electrode 104p (having a composition of Si or Ni ₃ Si) is formed. On the other hand, since the polysilicon gate electrode 112an in the nMISFET region an is a polysilicon gate electrode 112b into which fluorine (F) element is implanted, the effect of silicidation reaction of the fluorine (F) element prevents the metal monosilicide. A nickel (Ni) full silicide gate electrode 104n (having a composition of NiSi) is formed.

  That is, according to the method of manufacturing a semiconductor device according to the present embodiment, an element that exhibits a silicidation reaction suppressing effect is previously implanted into a polysilicon layer that reacts with nickel (Ni). It is possible to form gate electrodes made of different NiSix phases on p-type and n-type MISFETs by a simple process compared to the technology. Then, according to the method of manufacturing the semiconductor device according to the present embodiment, the polysilicon gate electrode 112a, the silicide metal film thickness, and the silicidation heat treatment conditions are the same in the pMISFET region ap and the nMISFET region an. It is possible to form gate electrodes made of different NiSix phases on the MISFETs of the n-type and n-type.

  Thereby, the threshold values of the pMISFET 100ap and the nMISFET 100an are controlled to different values, so that transistors having optimum threshold values can be easily formed, and a semiconductor device having excellent electrical characteristics and reliability can be easily manufactured. be able to.

  In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, there is no problem such as a complicated process or deterioration of a transistor shape due to an etch-back process. A quality semiconductor device can be manufactured.

Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) according to a second embodiment of the present invention, and is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) manufactured by applying the present invention. . A semiconductor device 20 according to the second embodiment includes a pMISFET 200p having a nickel (Ni) full silicide gate electrode 204p formed by a method for manufacturing a semiconductor device according to a second embodiment to be described later, and a second embodiment to be described later. And an nMISFET 200n having a nickel (Ni) full silicide gate electrode 204n formed by a method for manufacturing a semiconductor device.

  The configuration other than the silicon substrate 101, the element isolation film 102, the interlayer insulating film 108, the nickel (Ni) full silicide gate electrode 204p in the pMISFET 200p, and the configuration other than the nickel (Ni) full silicide gate electrode 204n in the nMISFET 200n are as described above. Since the semiconductor device 10 is the same as the semiconductor device 10 according to the first embodiment, the same reference numerals as those of the semiconductor device 10 are used, and detailed description thereof is omitted here.

In the semiconductor device 20 according to the present embodiment, the nickel (Ni) full silicide gate electrode 204p is nickel (Ni) -rich nickel (Ni) having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, Ni ₃ Si, or the like. It is a full silicide gate electrode. The nickel (Ni) full silicide gate electrode 204n is a nickel (Ni) full silicide gate electrode having a composition of NiSi (nickel monosilicide).

  In the semiconductor device 20 according to the present embodiment configured as described above, the high dielectric constant (high-k) gate insulating films 105p and 105n made of a high dielectric constant material are used as the gate insulating film. The high dielectric constant (high-k) gate insulating films 105p and 105n can cope with miniaturization of a semiconductor device without deteriorating electrical characteristics. Therefore, in the semiconductor device 20 according to the present embodiment, a semiconductor device having excellent electrical characteristics and reliability is realized in the same manner as the semiconductor device 10 according to the first embodiment described above.

  The semiconductor device according to the present embodiment has a full silicide gate structure using metal silicide as the gate electrode. By having such a full silicide gate structure, the semiconductor device 20 according to the present embodiment is effective due to the depletion of the gate electrode material as in the case where a polysilicon-based material is used as the gate electrode material. An increase in the thickness of the electrical gate insulating film is effectively suppressed. Therefore, in the semiconductor device 20 according to the present embodiment, a semiconductor device capable of reducing the effective gate insulating film thickness is realized in the same manner as the semiconductor device 10 according to the first embodiment.

In the semiconductor device 20 according to the present embodiment, the gate electrode in the pMISFET 200p is nickel (Ni) -rich nickel (Ni) full silicide having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, or Ni ₃ Si. is the gate electrode 204p, the gate electrode in nMISFET200n has been the nickel (Ni) fully silicided gate electrode 204n having a composition of NiSi (nickel mono silicide) or NiSi _2.

  Thus, in the semiconductor device 20 according to the present embodiment, the nickel (Ni) full silicide gate electrode 204p and the nickel (Ni) full silicide gate electrode 204n are composed of materials having different compositions. Due to the difference in composition, the threshold value is controlled to be different between the pMISFET 200p and the nMISFET 200n, and transistors each having an optimum threshold value are formed.

  Therefore, in the semiconductor device 20 according to the present embodiment, the pMISFET 200p and the nMISFET 200n are each provided with a gate electrode made of nickel (Ni) silicide having a different composition, and transistors each having an optimum threshold value are formed.

  Next, a method for manufacturing the semiconductor device 20 according to the present embodiment as described above will be described with reference to the drawings shown in FIGS. First, a process similar to that in the first embodiment described above is performed (corresponding to FIGS. 2-1 to 2-5), and a semiconductor having polysilicon gate electrodes 112ap and 112an as shown in FIG. 4-1. A device (intermediate) is produced.

  Next, a resist film is formed on the entire surface of the silicon substrate 101, and a resist mask 124 having a pMISFET region ap opened as shown in FIG. 4-2 is formed using a photoengraving technique. Then, using the resist mask 124 as a mask, as shown in FIG. 4-3, an element that promotes silicidation reaction (silicide reaction promoting element) is implanted into the pMISFET region ap by ion implantation (pre-doping). To do. By implanting (pre-doping) the silicidation reaction promoting element in this way, the polysilicon gate electrode 112ap is brought into a state where the silicidation reaction is promoted by amorphization or destruction of the polysilicon grains.

  As the silicidation reaction promoting element, for example, an element that promotes the silicidation reaction such as silicon (Si), germanium (Ge), nickel (Ni), platinum (Pt), tungsten (W) or the like alone or Two or more kinds of implanted elements can be used. Thereby, the polysilicon gate electrode 112ap in the pMISFET region ap is used as the polysilicon gate electrode 112c into which the silicidation reaction promoting element is implanted. Here, for example, silicon (Si) is used as the silicidation reaction promoting element. Silicon is also used as a material for semiconductor substrates, and is most preferable as a silicidation reaction accelerating element because there is no possibility of causing contamination in the manufacturing process unlike a metal element.

  Here, as shown in FIG. 4-3, the silicidation reaction promoting element is implanted into the pMISFET region ap using the resist mask 124 having the pMISFET region ap opened. A silicidation reaction promoting element may be implanted into the silicon gate electrode 112ap.

  The polysilicon film 112 for forming the polysilicon gate electrodes 112ap, an is formed in a relatively high temperature environment of several hundred degrees. By injecting silicon (Si) at room temperature into polysilicon formed at a relatively high temperature, the bonding force between Si and Si can be weakened, and then after nickel (Ni) is deposited. When heat treatment is performed, the reaction between nickel (Ni) and silicon (Si) is promoted.

The ion implantation is performed with an implantation energy in the range of 2 keV to 30 keV. In order to prevent the silicidation reaction promoting element implanted into the polysilicon gate electrode 112ap from penetrating into the silicon substrate 101, it is preferable to change the implantation energy depending on the type of element. The amount of silicidation reaction promoting element implanted is preferably in the range of 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .

  Further, when the silicidation reaction promoting element is implanted into the pMISFET region ap, the nMISFET region an is covered with a resist mask, and ion implantation of the silicidation reaction promoting element is not performed on the nMISFET region an. That is, when the silicidation reaction promoting element is implanted into the pMISFET region ap, the silicidation reaction promoting element is not ion implanted into the polysilicon gate electrode 112an.

  Next, the resist mask 124 is removed, and for example, a nickel (Ni) film 115 is deposited on the entire surface of the silicon substrate 101 as shown in FIG. Then, the silicidation heat treatment and the selective removal of unreacted nickel (Ni) are performed by controlling conditions such as the temperature, time, frequency, and selective nickel (Ni) removal timing of the silicidation heat treatment. Here, a case where nickel (Ni) is used as a metal that undergoes a silicidation reaction will be described as an example, but the metal that undergoes a silicidation reaction is not limited to this, and platinum (Pt), cobalt (Co), Metals such as titanium (Ti), hafnium (Hf), erbium (Er), zirconium (Zr), and tantalum (Ta) can also be used.

Here, the thickness of the nickel (Ni) film 115 for siliciding the polysilicon gate electrodes 112an and 112c is substantially the same in the pMISFET region ap and the nMISFET region an. The silicidation heat treatment conditions are also the same in the pMISFET region ap and the nMISFET region an. In this way, by combining the silicidation reaction between the polysilicon gate electrodes 112an and 112c and nickel (Ni) by heat treatment and the selective removal of unreacted nickel (Ni), Ni _x Si _y ( Nickel (Ni) silicide having a composition ratio of x and y is an integer) is formed.

As described above, silicon (Si) element is ion-implanted as a silicidation reaction promoting element in the pMISFET region ap. Thereby, the film thickness of the polysilicon gate electrode 112c (the film thickness of the original polysilicon gate electrode 112ap), the deposited film thickness of the nickel (Ni) film, the temperature, the time and the number of times of the silicidation heat treatment, the selective nickel (Ni ) By controlling conditions such as removal timing, nickel (Ni) silicide having a composition ratio of Ni _x Si _y (x and y are integers) is formed as a gate electrode. At this time, due to the silicidation reaction promoting effect of silicon (Si) element, nickel (Ni) rich nickel such as Ni ₃₁ Si ₁₂ , Ni ₂ Si and Ni ₃ Si is formed in the pMISFET region ap as shown in FIG. 4-5. A (Ni) full silicide gate electrode 204p is formed.

  On the other hand, as shown in FIG. 4-5, a nickel (Ni) full silicide gate electrode 204n having a composition of NiSi (nickel monosilicide) is formed in the nMISFET region an. Thus, the semiconductor device 20 according to the present embodiment shown in FIG. 3 can be formed.

  As described above, in the manufacturing method of the semiconductor device according to the present embodiment, before the silicide metal for siliciding the polysilicon gate electrode 112a is deposited, the polysilicon gate electrode 112ap in the pMISFET region ap is applied to the polysilicon gate electrode 112ap. Then, the silicidation reaction promoting element for promoting the silicidation reaction is ion-implanted (pre-doping). Then, for example, a nickel (Ni) film 115 is deposited on the entire surface of the silicon substrate 101 as a metal that undergoes a silicidation reaction, and a silicidation heat treatment is performed.

Since the polysilicon gate electrode 112ap in the pMISFET region ap is a polysilicon gate electrode 112c into which a silicidation reaction promoting element is implanted (pre-doped), the silicidation promoting effect of the silicidation reaction promoting element results in polysilicon. In the gate electrode 112c, the gate polysilicon sufficiently undergoes a silicidation reaction. As a result, a nickel (Ni) full silicide gate electrode 204p rich in metal (nickel) (for example, having a composition of Ni ₃₁ Si ₁₂ , Ni ₂ Si or Ni ₃ Si) is formed in the pMISFET region ap.

  On the other hand, a nickel (Ni) full silicide gate electrode 204n of metal monosilicide (having a NiSi composition) is formed in the nMISFET region an where no silicidation reaction promoting element is implanted.

  That is, according to the method of manufacturing a semiconductor device according to the present embodiment, by previously injecting an element that exhibits a silicidation reaction promoting effect into a polysilicon layer to be reacted with nickel (Ni), It is possible to form gate electrodes made of different NiSix phases on p-type and n-type MISFETs by a simple process compared to the technology. Then, according to the method of manufacturing the semiconductor device according to the present embodiment, the polysilicon gate electrode 112a, the silicide metal film thickness, and the silicidation heat treatment conditions are the same in the pMISFET region ap and the nMISFET region an. It is possible to form gate electrodes made of different NiSix phases on the MISFETs of the n-type and n-type.

  Thus, the threshold values of the pMISFET 200ap and the nMISFET 200an can be controlled to different values, so that transistors having optimum threshold values can be easily formed, and a semiconductor device having excellent electrical characteristics and reliability can be easily manufactured. be able to.

  In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, there is no problem such as a complicated process or deterioration of a transistor shape due to an etch-back process. A quality semiconductor device can be manufactured.

Embodiment 3 FIG.
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) according to a third embodiment of the present invention, and is a cross-sectional view showing a configuration of a semiconductor device (CMOS device) manufactured by applying the present invention. . A semiconductor device 30 according to the third embodiment includes a pMISFET 300p having a nickel (Ni) full silicide gate electrode 304p formed by a method for manufacturing a semiconductor device according to a third embodiment to be described later, and a later-described present embodiment. And an nMISFET 300n having a nickel (Ni) full silicide gate electrode 304n formed by a method for manufacturing a semiconductor device.

  The configurations other than the silicon substrate 101, the element isolation film 102, the interlayer insulating film 108, the nickel (Ni) full silicide gate electrode 304p in the pMISFET 200p, and the configurations other than the nickel (Ni) full silicide gate electrode 304n in the nMISFET 300n are as described above. Since the semiconductor device 10 is the same as the semiconductor device 10 according to the first embodiment, the same reference numerals as those of the semiconductor device 10 are used, and detailed description thereof is omitted here.

In the semiconductor device 30 according to the present embodiment, the nickel (Ni) full silicide gate electrode 304p is nickel (Ni) -rich nickel (Ni) having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, Ni ₃ Si, or the like. It is a full silicide gate electrode. Also, nickel (Ni) fully silicided gate electrode 304n is nickel (Ni) fully silicided gate electrode having a composition of NiSi (nickel mono silicide) or NiSi _2.

  In the semiconductor device 30 according to the present embodiment configured as described above, the high dielectric constant (high-k) gate insulating films 105p and 105n made of a high dielectric constant material are used as the gate insulating film. The high dielectric constant (high-k) gate insulating films 105p and 105n can cope with miniaturization of a semiconductor device without deteriorating electrical characteristics. Therefore, in the semiconductor device 30 according to the present embodiment, a semiconductor device having excellent electrical characteristics and reliability is realized in the same manner as the semiconductor devices 10 and 20 according to the first and second embodiments.

  The semiconductor device according to the present embodiment has a full silicide gate structure using metal silicide as the gate electrode. By having such a full silicide gate structure, the semiconductor device 30 according to the present embodiment is effective due to depletion of the gate electrode material as in the case where a polysilicon-based material is used as the gate electrode material. An increase in the thickness of the electrical gate insulating film is effectively suppressed. Therefore, in the semiconductor device 30 according to the present embodiment, a semiconductor device capable of being thinned is realized in the same manner as the semiconductor devices 10 and 20 according to the first and second embodiments described above.

In the semiconductor device 30 according to the present embodiment, the gate electrode of the pMISFET 300p is nickel (Ni) -rich nickel (Ni) full silicide having a composition such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, Ni ₃ Si, or the like. The gate electrode 304p is a nickel (Ni) full silicide gate electrode 304n having a composition of NiSi (nickel monosilicide).

  Thus, in the semiconductor device 30 according to the present embodiment, the nickel (Ni) full silicide gate electrode 304p and the nickel (Ni) full silicide gate electrode 304n are composed of materials having different compositions. The threshold value is controlled to be different between the pMISFET 300p and the nMISFET 300n due to the difference in composition, and transistors each having an optimum threshold value are formed.

  Therefore, in the semiconductor device 30 according to the present embodiment, the pMISFET 300p and the nMISFET 300n are provided with gate electrodes made of nickel (Ni) silicide having different compositions, and transistors each having an optimum threshold value are formed.

  Next, a method for manufacturing the semiconductor device 30 according to the present embodiment as described above will be described with reference to the drawings shown in FIGS. First, a process similar to that in the first embodiment described above is performed (corresponding to FIGS. 2-1 to 2-5), and a semiconductor having polysilicon gate electrodes 112ap and 112an as shown in FIG. A device (intermediate) is produced.

  Next, a resist film is formed on the entire surface of the silicon substrate 101, and a resist mask 114 having an nMISFET region an opened as shown in FIG. 6B is formed using a photoengraving technique. Then, using the resist mask 114 as a mask, a silicidation reaction suppressing element such as fluorine (F) is implanted (pre-doped) into the nMISFET region an by ion implantation as shown in FIG. 6-3. Thereby, the polysilicon gate electrode 112b into which the silicidation reaction suppressing element is implanted (pre-doped) is formed.

  Here, as shown in FIG. 6B, a silicidation reaction suppressing element is implanted into the nMISFET region an using a resist mask 114 having an opening in the nMISFET region an. A silicidation reaction suppressing element may be implanted into the silicon gate electrode 112an.

The ion implantation is performed with an implantation energy in the range of 2 keV to 30 keV. Further, in order to prevent the silicidation reaction suppressing element implanted into the polysilicon gate electrode 112an from penetrating into the silicon substrate 101, it is preferable to change the implantation energy depending on the type of element. The amount of silicidation reaction suppressing element implanted is preferably in the range of 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .

  Further, when the silicidation reaction suppressing element is implanted into the nMISFET region an, the pMISFET region ap is covered with a resist mask, and ion implantation of the silicidation reaction inhibiting element is not performed on the pMISFET region ap. That is, when the silicidation reaction suppressing element is implanted into the nMISFET region an, the silicidation reaction inhibiting element is not ion-implanted into the polysilicon gate electrode 112ap.

  Next, the resist mask 114 is removed, a resist film is formed again on the entire surface of the silicon substrate 101, and a resist mask 124 having a pMISFET region ap opened as shown in FIG. 6-4 is formed using photolithography. To do. Then, using the resist mask 124 as a mask, as shown in FIG. 6-5, an element (silicidation reaction promoting element) for promoting the silicidation reaction is implanted (pre-doping) into the pMISFET region ap by an ion implantation method. To do. By implanting (pre-doping) the silicidation reaction promoting element in this way, the polysilicon gate electrode 112ap is brought into a state where the silicidation reaction is promoted by amorphization or destruction of the polysilicon grains.

  As the silicidation reaction promoting element, for example, an element that promotes the silicidation reaction such as silicon (Si), germanium (Ge), nickel (Ni), platinum (Pt), tungsten (W) or the like alone or Two or more kinds of implanted elements can be used. Thereby, the polysilicon gate electrode 112ap in the pMISFET region ap is used as the polysilicon gate electrode 112c into which the silicidation reaction promoting element is implanted. Here, for example, silicon (Si) is used as the silicidation reaction promoting element.

  Here, as shown in FIG. 6-5, the silicidation reaction promoting element is implanted into the pMISFET region ap using the resist mask 124 having the pMISFET region ap opened. A silicidation reaction promoting element may be implanted into the silicon gate electrode 112ap.

  By injecting silicon (Si) at a room temperature into polysilicon formed at a relatively high temperature, the bonding force between the Si and Si of the polysilicon gate electrode 112ap can be weakened, and then nickel (Ni ) Is deposited and heat treatment is performed, the reaction between nickel (Ni) and silicon (Si) is promoted.

  Next, the resist mask 124 is removed, and for example, a nickel (Ni) film 115 is deposited on the entire surface of the silicon substrate 101 as shown in FIG. Then, the silicidation heat treatment and the selective removal of unreacted nickel (Ni) are performed by controlling conditions such as the temperature, time, frequency, and selective nickel (Ni) removal timing of the silicidation heat treatment.

Here, the thickness of the nickel (Ni) film 115 for siliciding the polysilicon gate electrodes 112an and 112c is substantially the same in the pMISFET region ap and the nMISFET region an. The silicidation heat treatment conditions are also the same in the pMISFET region ap and the nMISFET region an. Thus, by combining the silicidation reaction between the polysilicon gate electrodes 112b and 112c and nickel (Ni) by heat treatment and the selective removal of unreacted nickel (Ni), Ni _x Si _y ( Nickel (Ni) silicide having a composition ratio of x and y is an integer) is formed.

As described above, silicon (Si) element is ion-implanted as a silicidation reaction promoting element in the pMISFET region ap. Thereby, the film thickness of the polysilicon gate electrode 112c (the film thickness of the original polysilicon gate electrode 112ap), the deposited film thickness of the nickel (Ni) film, the temperature, the time and the number of times of the silicidation heat treatment, the selective nickel (Ni ) By controlling conditions such as removal timing, nickel (Ni) silicide having a composition ratio of Ni _x Si _y (x and y are integers) is formed as a gate electrode. At this time, due to the silicidation reaction promoting effect of silicon (Si) element, nickel (Ni) rich nickel such as Ni ₃₁ Si ₁₂ , Ni ₂ Si, Ni ₃ Si, etc. is formed in the pMISFET region ap as shown in FIG. 6-7. A (Ni) full silicide gate electrode 304p is formed.

On the other hand, the fluorine (F) element is ion-implanted into the nMISFET region an as described above. Thereby, the film thickness of the polysilicon gate electrode 112b (the film thickness of the original polysilicon gate electrode 112an), the deposited film thickness of the nickel (Ni) film, the temperature, time, number of times of silicidation heat treatment, selective nickel (Ni ) By controlling conditions such as removal timing, nickel (Ni) silicide having a composition ratio of Ni _x Si _y (x and y are integers) is formed as a gate electrode.

  At this time, in the nMISFET region an into which the fluorine (F) element is implanted, the nickel (Ni) full silicide gate electrode 304p is formed as shown in FIG. 6-7 due to the silicidation reaction suppression effect of the fluorine (F) element. . The nickel (Ni) full silicide gate electrode 304p has a composition of NiSi (nickel monosilicide). Thus, the semiconductor device 10 according to the present embodiment shown in FIG. 5 can be formed.

As described above, the semiconductor device manufacturing method according to the present embodiment is a combination of the semiconductor device manufacturing method according to the first embodiment and the semiconductor device manufacturing method according to the second embodiment. It is a manufacturing method. According to the manufacturing method of the semiconductor device according to the present embodiment, the pMISFET region ap has a high metal (nickel) content (for example, Ni ₃₁ Si ₁₂ , Ni ₂ Si) due to the silicidation promoting effect of the silicidation reaction promoting element. And a nickel (Ni) full silicide gate electrode 304p (having a composition of Ni ₃ Si).

On the other hand, due to the silicidation reaction suppressing effect of the silicidation reaction suppressing element, a nickel (Ni) full silicide gate electrode 304n having a low metal content (for example, having a composition of NiSi or NiSi ₂ ) is formed in the nMISFET region an. Thereby, the threshold values of the pMISFET 300ap and the nMISFET 300an can be controlled to be different values, so that transistors having optimum threshold values can be easily formed, and a semiconductor device having excellent electrical characteristics and reliability can be easily manufactured. be able to.

  According to the semiconductor device manufacturing method of the present embodiment, both the silicidation promoting effect of the silicidation reaction promoting element and the silicidation reaction inhibiting effect of the silicidation reaction suppressing element are used. As compared with the first and second embodiments, the threshold values of the pMISFET 300ap and the nMISFET 300an can be reliably controlled by different values, so that transistors having optimum threshold values can be easily formed. A semiconductor device having excellent properties can be easily manufactured.

  Further, according to the method for manufacturing a semiconductor device according to the present embodiment, both the silicidation promoting effect of the silicidation reaction promoting element and the silicidation reaction inhibiting effect of the silicidation reaction suppressing element are used. The control margin is increased, and the degree of freedom of control in the manufacturing process is increased.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a CMOS device, and is particularly suitable for a CMOS device of 45 nm node or later.

It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Semiconductor device 30 Semiconductor device 101 Silicon substrate 102 Element isolation film 103p Source / drain region 103n Source / drain region 104p Full silicide gate electrode 104n Full silicide gate electrode 105p Gate insulation film 105n Gate insulation film 106p Side wall 106n Side wall 107p silicide layer 107n silicide layer 108 insulating film 111 metal oxide film 112 polysilicon film 112ap polysilicon gate electrode 112an polysilicon gate electrode 112b polysilicon gate electrode 112c polysilicon gate electrode 113 hard mask 113ap hard mask 113an hard mask 114 resist mask 115 Nickel film 124 Resist mask 204p Full series Idogeto electrode 204n fully silicided gate electrode 304p fully silicided gate electrode 304n fully silicided gate electrode

Claims (11)

A first gate insulating film made of a high dielectric constant material is formed on a region of the first conductivity type in the semiconductor substrate, and a second gate made of a high dielectric constant material is formed on the region of the second conductivity type in the semiconductor substrate. A gate insulating film forming step of forming a gate insulating film;
A polysilicon gate electrode for forming a first polysilicon gate electrode made of polysilicon on the first gate insulating film and a second polysilicon gate electrode made of polysilicon on the second gate insulating film Forming process;
A first source / drain region is formed in the first conductivity type region where the first polysilicon gate electrode is formed, and a second conductivity type region is formed in the second conductivity type region where the second polysilicon gate electrode is formed. A source / drain region forming step of forming two source / drain regions,
An implantation step of injecting an element of a silicidation reaction suppressing metal that suppresses a silicidation reaction into the first polysilicon gate electrode without being injected into the second polysilicon gate electrode;
A first metal film forming step of forming a first metal film to be silicided on at least the first and second polysilicon gate electrodes after the implantation of the silicidation reaction suppressing metal element;
After the formation of the first metal film, the semiconductor substrate is heat-treated to silicidize the first and second polysilicon gate electrodes to form full silicide electrodes, respectively;
A method for manufacturing a semiconductor device, comprising: Removing the unreacted first metal film in the first heat treatment step;
The method of manufacturing a semiconductor device according to claim 1. The silicidation reaction suppressing metal is fluorine;
The method of manufacturing a semiconductor device according to claim 1. The first metal to be silicided is nickel;
The method of manufacturing a semiconductor device according to claim 1. Between the polysilicon gate electrode forming step and the source / drain region forming step,
And a prevention layer forming step of forming first and second prevention layers for preventing silicidation of the first and second polysilicon gate electrodes on the first and second polysilicon gate electrodes, respectively. ,
Between the source / drain region forming step and the implantation step,
Sidewalls of the first gate insulating film, the first polysilicon gate electrode and the first prevention layer; and sidewalls of the second gate insulation film, the second polysilicon gate electrode and the second prevention layer; Forming sidewalls on the sidewalls; and
A second metal film forming step of forming a second metal film to be silicided on at least the first and second source / drain regions after forming the sidewall;
A second heat treatment step in which the surface of the first and second source / drain regions is silicided by heat-treating the semiconductor substrate on which the second metal film is formed;
Having
The method of manufacturing a semiconductor device according to claim 1. A first gate insulating film made of a high dielectric constant material is formed on a region of the first conductivity type in the semiconductor substrate, and a second gate made of a high dielectric constant material is formed on the region of the second conductivity type in the semiconductor substrate. A gate insulating film forming step of forming a gate insulating film;
A polysilicon gate electrode for forming a first polysilicon gate electrode made of polysilicon on the first gate insulating film and a second polysilicon gate electrode made of polysilicon on the second gate insulating film Forming process;
A first source / drain region is formed in the first conductivity type region where the first polysilicon gate electrode is formed, and a second conductivity type region is formed in the second conductivity type region where the second polysilicon gate electrode is formed. A source / drain region forming step of forming two source / drain regions,
An implantation step of injecting an element of a silicidation reaction promoting metal that promotes a silicidation reaction into the second polysilicon gate electrode without being implanted into the first polysilicon gate electrode;
A first metal film forming step of forming a first metal film to be silicided on at least the first and second polysilicon gate electrodes after the implantation of the silicidation reaction promoting metal element;
After the formation of the first metal film, the semiconductor substrate is heat-treated to silicidize the first and second polysilicon gate electrodes to form full silicide electrodes, respectively;
A method for manufacturing a semiconductor device, comprising: Removing the unreacted first metal film in the first heat treatment step;
A method of manufacturing a semiconductor device according to claim 6. The silicidation reaction promoting metal is silicon;
A method of manufacturing a semiconductor device according to claim 6. The first metal to be silicided is nickel;
A method of manufacturing a semiconductor device according to claim 6. Between the polysilicon gate electrode forming step and the source / drain region forming step,
And a prevention layer forming step of forming first and second prevention layers for preventing silicidation of the first and second polysilicon gate electrodes on the first and second polysilicon gate electrodes, respectively. ,
Between the source / drain region forming step and the implantation step,
Sidewalls of the first gate insulating film, the first polysilicon gate electrode and the first prevention layer; and sidewalls of the second gate insulation film, the second polysilicon gate electrode and the second prevention layer; Forming sidewalls on the sidewalls; and
A second metal film forming step of forming a second metal film to be silicided on at least the first and second source / drain regions after forming the sidewall;
A second heat treatment step in which the surface of the first and second source / drain regions is silicided by heat-treating the semiconductor substrate on which the second metal film is formed;
Having
The method of manufacturing a semiconductor device according to claim 1. A first gate insulating film made of a high dielectric constant material is formed on a region of the first conductivity type in the semiconductor substrate, and a second gate made of a high dielectric constant material is formed on the region of the second conductivity type in the semiconductor substrate. A gate insulating film forming step of forming a gate insulating film;
A polysilicon gate electrode for forming a first polysilicon gate electrode made of polysilicon on the first gate insulating film and a second polysilicon gate electrode made of polysilicon on the second gate insulating film Forming process;
A first source / drain region is formed in the first conductivity type region where the first polysilicon gate electrode is formed, and a second conductivity type region is formed in the second conductivity type region where the second polysilicon gate electrode is formed. A source / drain region forming step of forming two source / drain regions,
A first injection step of injecting an element of a silicidation reaction suppressing metal that suppresses a silicidation reaction into the first polysilicon gate electrode without being injected into the second polysilicon gate electrode;
A second injection step of injecting an element of a silicidation reaction promoting metal that promotes a silicidation reaction into the second polysilicon gate electrode without being injected into the first polysilicon gate electrode;
A metal film forming step of forming a metal film to be silicided on at least the first and second polysilicon gate electrodes after the implantation of the silicidation reaction suppressing metal and the silicidation reaction promoting metal element;
After the formation of the metal film, the semiconductor substrate is heat-treated to silicidize the first and second polysilicon gate electrodes so that each is a full silicide electrode;
A method for manufacturing a semiconductor device, comprising:

Images