JP2008218480A - Compound semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device that can reduce contact resistance and establish high speed performance of an InP-based HEMT even if a double-doped InP-based HEMT or a reverse HEMT InP-based HEMT wherein high reliability can be obtained has a micro-fabricable non-alloy ohmic electrode structure. <P>SOLUTION: The compound semiconductor device is provided with: an InGaAs channel layer 3 formed on a substrate 1; an electron supply layer 5A that is formed between the substrate 1 and the channel layer 3 and is larger in energy band gap as compared with the channel layer 3, and is doped in n type; an electron supply layer 5B that is formed between the channel layer 3 and a gate electrode 9 and is larger in energy band gap as compared with the channel layer 3, and is doped in n type; a semiconductor layer that is formed between the channel layer 3 and the gate electrode 9 and is larger in energy band gap as compared with the channel layer 3; and a source electrode 12 and a drain electrode 13 that are formed in directly contact with the channel layer 3 without being alloyed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high electron mobility transistor (HEMT) having an InGaAs channel layer suitable for use in an ultrahigh-speed operation integrated circuit and a millimeter-wave band MMIC (monolithic integrated circuit).

  In general, HEMTs are used as high-frequency devices and high-speed devices as elements having good high-frequency characteristics and high-speed operability. Among them, the so-called InP-based HEMT having InGaAs (In composition> 0.53) as a channel layer is an ultra-high-speed device capable of obtaining a high-speed characteristic with a cutoff frequency of 500 GHz or more. Application is expected.

  FIG. 3 is a cutaway side view of the main part showing the structure of a normal InP-based HEMT (see, for example, Non-Patent Document 1). An undoped InAlAs buffer layer 2 and an undoped InGaAs channel layer 3 are formed on a semi-insulating InP substrate 1. The undoped InAlAs spacer layer 4, the n-type InAlAs electron supply layer 5, the undoped InAlAs barrier layer 6, the InP stopper layer 7, and the n-type InGaAs cap layer 8 are laminated in this order, and the InP stopper layer 7 The gate electrode 9 and the source electrode 10 and the drain electrode 11 are in contact with the n-type InGaAs cap layer 8, respectively. The n-type InAlAs electron supply layer 5 may be replaced with a soot-doped layer.

  In the InP-based HEMT described above, since the n-type InGaAs cap layer 8 is doped at a high concentration, the source electrode 10 and the drain electrode 11 are not alloyed and are not alloyed. Thus, ohmic contact with the n-type InGaAs cap layer 8 can be obtained.

  By the way, this InP-based HEMT is susceptible to collision ionization in the InGaAs channel layer 3 employed for realizing high-speed operation, and therefore has low reliability when a high drain voltage of, for example, 2 V or higher is applied. It has been reported that there is a problem that the design margin is small, for example, a circuit design in which no voltage is applied is required (see, for example, Non-Patent Document 2).

  The above report describes that a double-doped structure is effective in improving the reliability in the InP-based HEMT shown in FIG.

  FIG. 4 is a cutaway side view of the main part showing the structure of an InP-based HEMT with improved reliability. The parts indicated by the same symbols as those used in FIG. 3 represent the same or equivalent parts. .

  In the InP-based HEMT with improved reliability shown in FIG. 4, the InGaAs channel layer 3 is a stacked body composed of InAlAs spacer layers 4 A and 4 B, n-type InAlAs electron supply layers 5 A and 5 B, and undoped InAlAs barrier layers 6 A and 6 B from above and below. It is said that the double dope structure sandwiched between is effective.

However, in the structure shown in FIG. 4, since the surface-side electron supply layer 5B is thin, an electrode structure in which ohmic contact is made non-alloyed from the cap layer 8 used in a normal InP-based HEMT is adopted. However, the contact resistance is high, and the inherent high speed performance of the InP-based HEMT is not realized. Actually, the mutual conductance (g _m ) of the single doped structure is 873 mS / mm, whereas the mutual conductance (g _m ) of the double doped structure is as low as 729 mS / mm.

  Although there is a means of making contact using alloy ohmic even in a double-doped structure, in alloy ohmic for a semiconductor containing a large amount of In, the electrode surface is rough, resulting in unevenness on the electrode end face (side face), and miniaturization. It becomes an obstacle to advance.

  Further, when the inverse HEMT structure is used, the reliability is improved because there is an electric field concentration relaxation effect as in the case of the double dope structure. However, the high ohmic contact resistance is similar to the double-doped structure.

In short, with the conventional technology related to InP-based HEMTs, it has not been possible to simultaneously realize the high speed, high reliability, and miniaturization.
N. Hara et al., IEEE Transactions on Semiconductor Manufacturing, Volume 16, Issue 3, pp. 370-375 (August 2003) N. Hara et al., 2004 International Conference on Indium Phosphate and Related Materials Conference Processings, pp. 615-618 (May 2004)

  In the present invention, the contact resistance is reduced even in the case of a non-alloy ohmic electrode structure that can be miniaturized in a double-doped InP-based HEMT or an inverse HEMT-structured InP-based HEMT capable of realizing high reliability. The high speed performance inherent to the InP-based HEMT can be realized.

  In the compound semiconductor device according to the present invention, the channel layer made of InGaAs formed on the substrate and the energy band gap formed between the substrate and the channel layer are wider than the channel layer. An n-type doped electron supply layer, a semiconductor layer formed between the channel layer and the gate electrode and having a wider energy band gap than the channel layer, and without being alloyed with the channel layer It is basically provided with a source electrode and a drain electrode formed in direct contact.

  By adopting the above means, in the double doped structure InP-based HEMT or the reverse HEMT structure InP-based HEMT, by forming a non-alloy ohmic electrode that is in direct contact with the channel layer, high speed, high reliability, It has become possible to simultaneously realize the three requirements for miniaturization.

  The present invention improves the ohmic electrode structure in the conventional double-doped InP-based HEMT described with reference to FIG. 4 and the ohmic electrode structure in the inverse HEMT-structured InP-based HEMT.

  The non-alloy ohmic contact resistance is increased due to the band discontinuity between the InP stopper layer 7 and the InAlAs barrier layer 6B. Therefore, an ohmic electrode such as a source electrode or a drain electrode is preferably formed so as to be in direct contact with the InGaAs channel layer 3.

  Similarly, in the inverted HEMT structure, an ohmic electrode that is in direct contact with the InGaAs channel layer may be formed.

  FIG. 1 is a cutaway side view of an essential part showing a double-doped InP-based HEMT embodying the present invention. The parts indicated by the same symbols as those used in FIGS. 3 and 4 are the same or effective parts. It shall represent. In the figure, reference numeral 12 denotes a source electrode, and 13 denotes a drain electrode.

  When this double-doped InP-based HEMT is manufactured, the InGaAs cap layer 8, the InP stopper layer 7, the InAlAs barrier layer 6B, the n-type InAlAs electron supply layer 5B, and the InAlAs in the regions where the source electrode 12 and the drain electrode 13 are to be formed. The spacer layer 4B is removed to form an opening, and the source electrode 12 and the drain electrode 13 are formed on the InGaAs channel layer 3 exposed at the bottom of the opening.

  FIG. 2 is a cutaway side view of a principal part showing an inverse HEMT structure InP-based HEMT embodying the present invention, and the parts indicated by the same symbols as those used in FIG. 1 represent the same or equivalent parts. To do.

  The case of manufacturing the inverse HEMT structure InP-based HEMT is the same as the case of manufacturing the double-doped structure InP-based HEMT described above, and the InGaAs cap layer 8 in the portions where the source electrode 12 and the drain electrode 13 are to be formed, The InP stopper layer 7 and the InAlAs barrier layer 6B are removed to form an opening, and the source electrode 12 and the drain electrode 13 are formed on the InGaAs channel layer 3 exposed at the bottom of the opening.

  When the source electrode 12 and the drain electrode 13 are formed, the alloying heat treatment is not performed and a non-alloy ohmic electrode, which is one of the features of the present invention, is used. Since the composition is 0.53, ohmic contact with sufficiently low contact resistance can be obtained even without alloying heat treatment.

  A case where the double-doped InP-based HEMT described with reference to FIG. 1 is manufactured will be described.

(1)
By using a MOVPE (metalorganic vapor phase epitaxy) method, an undoped InAlAs buffer layer 2 (In composition 0.52; film thickness 300 nm), an undoped InAlAs barrier layer 6A (In composition 0.52) on a semi-insulating InP substrate 1. , Film thickness 5 nm), Si-doped InAlAs electron supply layer 5A (In composition 0.52, film thickness 3 nm, doping concentration 5 × 10 ¹⁸ cm ⁻³ ), undoped InAlAs spacer layer 4A (In composition 0.52; film thickness 3 nm) ), Undoped InGaAs channel layer 3 (In composition 0.53, film thickness 15 nm), undoped InAlAs spacer layer 4B (In composition 0.52; film thickness 3 nm), Si-doped InAlAs electron supply layer 5B (In composition 0.52), thickness 7 nm, the doping concentration of 5 × 10 ¹⁸ cm ^-3), Ndopu InAlAs barrier layer 6B (an In composition 0.52, thickness 5 nm), an undoped InP stopper layer 7 (thickness 5 nm), Si-doped InGaAs cap layer 8 (an In composition 0.53, thickness 50 nm, the doping concentration of 1 × 10 ¹⁹ cm ⁻³ ). Si-doped InAlAs electron supply layers 5A and 5B may be Si-sodium doped layers.

(2)
Next, by using a lithography technique and a wet etching technique, elements other than the element production scheduled portion are etched from the surface until reaching the buffer layer 2 to perform element separation. In the present invention, for example, a phosphoric acid-based etchant is used for etching InGaAs and InAlAs, and a hydrochloric acid-based etchant is used for etching InP.

(3)
Next, using the lithography technique and the wet etching technique, etching is performed from the surface until reaching the channel layer 3 in the region where the source electrode 12 and the drain electrode 13 are to be formed, and then the deposition technique and the lift-off technique are used. Accordingly, the source electrode 12 and the drain electrode 13 made of Mo / Ti / Pt / Au are formed. Of course, the alloying heat treatment after electrode formation is not performed.

(4)
Next, the gate electrode 9 is formed by using the lithography technique, the vapor deposition technique, and the lift-off technique after removing the InGaAs cap layer 8 at the gate recess region formation scheduled part by using the lithography technique and the wet etching technique. . Here, a typical gate length is 0.1 μm. The completed HEMT had a mutual conductance (g _m ) of 890 mS / mm, and the same characteristics as those of a single-doped HEMT were obtained.

  A case where the inverted HEMT structure InP-based HEMT described with reference to FIG. 2 is manufactured will be described.

(1)
By using the MOVPE method, an undoped InAlAs buffer layer 2 (In composition 0.52 and film thickness 300 nm), an undoped InAlAs barrier layer 6A (In composition 0.52 and film thickness 5 nm) on the semi-insulating InP substrate 1; Si-doped InAlAs electron supply layer 5 (In composition 0.52, film thickness 10 nm, doping concentration 5 × 10 ¹⁸ cm ⁻³ ), undoped InAlAs spacer layer 4 (In composition 0.52; film thickness 3 nm), undoped InGaAs channel layer 3 (In composition 0.53, film thickness 15 nm), undoped InAlAs barrier layer 6B (In composition 0.52, film thickness 20 nm), undoped InP stopper layer 7 (film thickness 5 nm), Si-doped InGaAs cap layer 8 (In composition) 0.53, film thickness 50 nm, doping concentration 1 × 10 ¹⁹ cm ⁻³ ). The Si-doped InAlAs electron supply layer 5 may be a Si-sodium doped layer.

(2)
Thereafter, through the same process as in Example 1, element isolation is performed, the source electrode 12 and the drain electrode 13 are formed, the gate recess is formed, and the gate electrode 9 is formed to complete the inverted HEMT structure InP-based HEMT. . The completed HEMT had a mutual conductance (g _m ) of 880 mS / mm, and the same characteristics as those of a single-doped HEMT were obtained.

The following table shows a comparison of the high-speed characteristics for each of the compound semiconductor devices described above, and the compound semiconductor device according to the present invention is superior to the compound semiconductor device according to the prior art. I can see it.

  In the example described above, a device is manufactured using an InP substrate, but Si or GaAs can also be used as the substrate. In addition to the Si, other n-type dopants such as S can be used as the dopant.

It is a principal part cutting side view showing the double dope structure InP type HEMT which implemented this invention. It is a principal part cutting side view showing the reverse HEMT structure InP type HEMT which implemented this invention. It is a principal part cutting side view showing the structure of normal InP type HEMT. It is a principal part cutting side view showing the structure of InP type HEMT which improved reliability.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 InP substrate 2 Undoped InAlAs buffer layer 3 Undoped InGaAs channel layer 4, 4A, 4B Undoped InAlAs spacer layer 5, 5A, 5B n-type InAlAs electron supply layer 6, 6A, 6B Undoped InAlAs barrier layer 7 Undoped InP stopper layer 8 n-type InGaAs cap layer 9 Gate electrode 10 Source electrode (conventional example)
11 Drain electrode (conventional example)
12 Source electrode (present invention)
13 Drain electrode (present invention)

Claims (4)

A channel layer made of InGaAs formed on a substrate;
An electron supply layer formed between the substrate and the channel layer, having an energy band gap wider than that of the channel layer and doped in an n-type;
A semiconductor layer formed between the channel layer and the gate electrode and having a wider energy band gap than the channel layer;
A compound semiconductor device comprising a source electrode and a drain electrode formed in direct contact with the channel layer without being alloyed. A first electron supply layer formed between the substrate and the channel layer, having a wider energy band gap than the channel layer and doped in an n-type;
2. A second electron supply layer which is formed between the channel layer and the gate electrode and has a wider energy band gap than the channel layer and is doped n-type. 2. The compound semiconductor device according to 1. 2. The compound according to claim 1, comprising a single electron supply layer formed between the substrate and the channel layer and having an energy band gap wider than that of the channel layer and doped in an n-type. Semiconductor device. 4. The compound semiconductor device according to claim 1, wherein the electron supply layer is made of InAlAs.

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