JP2008218020A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve image display of high quality by sufficiently vanishing electrons captured by a tunnel insulating layer during a selected period in an unselected period. <P>SOLUTION: The scanning circuit SD1, SD2, SD3, SD4, ... of a scanning driver 2 apply scanning signals to scanning lines 21 one by one. Pulse voltages each having a prescribed width and a prescribed wave height are applied to selected data lines 27 selected by the scanning signals from driving circuits DD1, DD2, DD3, DD4,... . This pulse passes a high-pass filter HPF to obtain positive and negative pulse voltages having narrow widths. This short pulse is applied to the lower electrode of a cathode K, the width of the positive bias voltage having the short width is set to a width of not more than the charging time of the cathode K, and it is thereby prevented that electrons are emitted when extracting captured electrons (blanking period) to cause erroneous emission. Electrons captured by the tunnel insulating layer during a display period are extracted by a reverse bias short pulse applied to the cathode K. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image display device, and is particularly suitable for a cold cathode type image display device also called a self-luminous flat panel display using a thin film electron source array.

  2. Description of the Related Art Planar image display devices (flat panel displays: FPDs) have been developed that use electron emission electron sources, which are also referred to as thin and thin film electron sources. The electron source of this type of image display apparatus is classified into an electron emission type electron source and a hot electron type electron source. The former includes spindt type electron sources, surface conduction type electron sources, carbon nanotube type electron sources and the like, and the latter includes metal-insulator-metal stacked MIM (metal-insulator-metal) type, metal-insulators. There are thin-film electron sources such as MIS (Metal-Insulator-Semiconductor) type, metal-insulator-semiconductor-metal type, etc. in which semiconductors are stacked.

  Regarding the MIM type, for example, in Patent Document 1, the metal-insulator-semiconductor type is the MOS type (Non-Patent Document 1), the metal-insulator-semiconductor-metal type is the HEED type (described in Non-Patent Document 2, etc.), An EL type (described in Non-Patent Document 3 and the like), a porous silicon type (described in Non-Patent Document 4 and the like), and the like have been reported.

The MIM type electron source is also disclosed in Patent Document 2, for example. The structure and operation of the MIM type electron source are as follows. That is, it has a structure in which an insulating layer (tunnel insulating layer) is interposed between the upper electrode and the lower electrode, and a Fermi level in the lower electrode is obtained by applying a voltage between the upper electrode and the lower electrode. Nearby electrons pass through the barrier due to the tunnel phenomenon, and are injected into the conduction band of the tunnel insulating layer, which is the electron acceleration layer, to become hot electrons, and flow into the conduction band of the upper electrode. Among these hot electrons, those that reach the surface of the upper electrode with energy equal to or higher than the work function φ of the upper electrode are released into the vacuum. In the following, the thin film type electron source is also simply referred to as an electron source unless otherwise required. In such an electron source, Patent Document 3 discloses a driving method for suppressing fluctuations in electron emission characteristics due to electrons trapped in the tunnel insulating layer.
JP-A-7-65710 Japanese Patent Laid-Open No. 10-153979 JP-A-7-65710 j.Vac.Sci.Technol.B11 (2) p.429-432 (1993) high-efficiency-electro-emission device, Jpn, j, Appl, Phys, vol. 36, pp. 939 Electroluminescence, Applied Physics Vol. 63, No. 6, p. 592 Applied Physics Vol. 66, No. 5, p. 437

  In an image display apparatus using this type of electron source, a plurality of electron sources (cathodes) are arranged on a cathode substrate in a two-dimensional matrix (also referred to as an array) to form a display region. FIG. 15 is a schematic cross-sectional view illustrating the basic structure of an image display device according to the present invention. A cathode substrate (cathode substrate) 10 having an electron source (cathode) on the main surface (inner surface) and a phosphor substrate (anode substrate) 20 having a fluorescent surface on the main surface are opposed to each other and sealed between the outer surfaces of the opposing surfaces. A vacuum container is configured by bonding together with a predetermined gap through a frame (not shown).

  The cathode K has a laminated structure of a lower electrode 11 and an upper electrode 13 formed on the lower electrode 11 via an insulating layer (hereinafter referred to as a tunnel insulating layer) 12. The lower electrode 11 is made of an aluminum film or an aluminum alloy film, and the tunnel insulating layer 12 is an amorphous oxide film obtained by anodizing the surface of the lower electrode 11. The lower electrode 11 and the upper electrode 13 are electrically insulated by the field insulating layer 14 and the interlayer insulating layer 15. On the interlayer insulating layer 15, a scanning wiring (scanning line bus wiring) 21 composed of three layers of a lower metal 16, an intermediate metal 17 and an upper metal 18 is formed. The lower metal 16 is, for example, chromium (Cr), the intermediate metal 17 is aluminum (Al), and the upper metal 18 is chromium. The lower metal 16 protrudes outward from the intermediate metal 17 on the electron source side, forms an inclined surface together with the interlayer insulating layer 15 and the field insulating layer 14, and the ultrathin upper electrode 13 formed on the upper layer of the scanning wiring. Electrical connection with the upper electrode 13 is ensured. On the opposite side, the lower metal 16 is retracted inward from the edge of the intermediate metal 17 by the etching back, and the edge of the intermediate metal 17 forms a step that becomes a ridge with respect to the lower metal 16 by this retreat. is doing. The adjacent pixels (pixels on the right side in FIG. 14) are separated by this step.

  A black matrix 26 is formed on the main surface of the anode substrate 20, and the phosphor 22 is applied to the opening of the black matrix 26. A counter electrode (anode) 24 is formed to cover the black matrix 26 and the phosphor 22. A spacer 23 is provided between the black matrix 26 of the anode substrate 20 and the scanning wiring 21 of the cathode substrate 10 to maintain a gap of about several mm between the substrates.

The lower electrode 11 is a signal wiring (or data line). By applying a voltage Vd (= 3 to 10 kV) between the lower electrode 11 and the anode electrode 24, an electron source is generated according to the principle described in FIG. 16 below. Electrons e ⁻ are emitted from the light source, hit the phosphor 22 applied to the lower layer of the anode electrode 24, excite the phosphor 22, and light L having a predetermined wavelength or wavelength range according to the material of the phosphor. Released.

FIG. 16 is an explanatory diagram of the operating principle of the electron source (cathode) shown in FIG. This electron source, that is, the cathode, applies a driving voltage Vd between the upper electrode 13 and the lower electrode 11 so that the electric field in the tunnel insulating layer 12 is about 1 to 10 MV / cm. The electrons in the vicinity pass through the barrier due to the tunnel phenomenon, are injected into the conduction band of the tunnel insulating layer 12 which is the electron acceleration layer, become hot electrons, and flow into the conduction band of the upper electrode 13. Among these hot electrons, electrons e ⁻ that reach the surface of the upper electrode 13 with energy equal to or higher than the work function φ of the upper electrode 13 are emitted into the vacuum.

  FIG. 17 is a schematic diagram for explaining a circuit configuration of an image display device configured by arranging cathodes in a two-dimensional matrix to form a display region and combining this with a drive circuit. The plurality of cathodes K are formed by a plurality of lower electrodes 11 formed by data lines 27 wired in the vertical direction (up and down direction in FIG. 16) and scanning lines 21 wired in the horizontal direction (left and right direction in FIG. 16). The display area AR is formed at the intersections with the plurality of upper electrodes 13.

  Display data is supplied to the data line 27 from the data driver 1 via the switch 4. The data driver 1 is connected to drive circuits DD1, DD2, DD3, DD4,... Corresponding to the data lines 27, respectively. The scanning lines (scan lines) 21 are sequentially scanned with a scanning signal applied from the scan driver 2. The scan driver 2 is connected to the scanning circuits SD1, SD2, SD3, SD4,. The switch 4 is connected to a reverse bias application circuit 5 and is a reverse bias application switch for preventing a decrease in electron emission capability due to trapped electrons in a tunnel insulating layer described below.

  18A to 18H are explanatory diagrams of energy band changes in the process of reducing trapped electrons during the selection period and the non-selection period in the MIM type cathode. FIG. 18A is an explanatory diagram of an energy band in a state where the cathode is isolated, and there is a band offset φb between the lower electrode 11 and the tunnel insulating layer 12 forming the laminated structure of the cathode, and the upper electrode 13 and the tunnel insulating layer 12. A state in which there is a band offset φt in between.

  FIG. 18B shows a state in which the cathode K is in a non-selection period. Both the lower electrode 11 and the upper electrode 13 are at the ground GND potential, and the energy level is the same (no charge is accumulated). FIG. 18C shows a state in which a negative potential is applied from the potential source E to the lower electrode 11 and a positive bias Vd is applied to the upper electrode 13 at the initial stage of the selection period in which the cathode is selected by the scan line.

  FIG. 18D shows a steady state when the cathode K is in the selection period, and shows a state where electrons are trapped in the tunnel insulating layer 12 from the lower electrode 11. FIG. 18E shows a state in which a non-selection period is reached when electrons are trapped in the tunnel insulating layer 12. FIG. 18F shows an initial state in which reverse bias is applied from the potential source E to the lower electrode 11 in the state shown in FIG. 18E. The reverse bias is applied by switching the switch 4 in FIG. 16 to the reverse bias application circuit 5 side. A steady state where a reverse bias is applied is shown in FIG. 18G. In the steady state shown in FIG. 18G, some of the electrons remain captured, and some of the captured electrons remain even in the non-selection period (FIG. 18H).

  Thus, in the conventional reverse bias application technique, since the MIM cathode is a diode, it is difficult for an electron current to flow when the reverse bias is applied (low electron mobility), and the trapped electrons are extracted to the lower electrode side in a short time. It is difficult to eliminate trapped electrons in the tunnel insulating layer. If trapped electrons trapped in the tunnel insulating layer remain in the selection period, the electron emission ability from the cathode fluctuates, resulting in an afterimage and a decrease in luminance, thereby degrading display quality.

  An object of the present invention is to provide an image display device that realizes high-quality image display by sufficiently erasing electrons trapped in a tunnel insulating layer during a selection period during a non-selection period.

  In order to achieve the above object, the present invention (1) extracts trapped electrons when a positive bias having a high electron mobility is applied. (2) At this time, in order to prevent simultaneous electron injection and erroneous light emission, the pulse width of the positive bias is limited to less than the charging time of the MIM capacitor. (3) To facilitate this, a high-pass filter (high-pass filter) is provided between the signal line and the drive circuit, and a pulse of a predetermined magnitude having a width equivalent to the signal voltage applied from the drive circuit is provided. A short pulse (differential pulse) obtained by passing through a high-pass filter is applied as a reverse voltage to the lower electrode.

  It is possible to provide an image display device that realizes high-quality image display because electrons trapped in the tunnel insulating film disappear in a short period of time, and fluctuations in the electron emission ability from the cathode are suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of the examples. In the following, an embodiment of the present invention will be described by taking an image display device using an MIM (metal-insulator-metal) type electron source as an example, but it has an electron acceleration layer, and electrons are captured during the electron emission period. The present invention can be similarly applied to an image display apparatus using another electron source having a mechanism that is influenced by, for example, fluctuation of the electron emission characteristics of the captured electrons.

  First, a high-pass filter (high-pass filter) HPF used in the image display device of the present invention will be described. FIG. 19 is a typical circuit diagram of a high-pass filter. FIG. 20 is an explanatory diagram of the input signal waveform and output signal of the high-pass filter shown in FIG. The high-pass filter includes a resistor inserted in series for signal transmission and a capacitor C connected in parallel to the signal output side of this resistor. When the rectangular pulse shown in FIG. 20A is applied as the input signal Sin to the input of the high-pass filter shown in FIG. 19, the differentiated pulse shown in FIG. 20B is output as the output signal Sout. For example, when the pulse width of the input signal Sin is 10 to 100 μsec, the pulse width of the output signal Sout is 1 to 10 μsec.

  1 and 2 are schematic diagrams for explaining an embodiment of the image display device of the present invention. FIG. 1 shows a state in which image display is performed by the cathode K (display period in one frame), and FIG. A state of erasing electrons trapped in the tunnel insulating layer of the cathode K (non-display period: blanking period in one frame) is shown. FIG. 3 is a diagram for explaining the operation of the embodiment. As in FIG. 17, the image display apparatus of this embodiment is configured by arranging cathodes K in a two-dimensional matrix to form a display area and combining this with a drive circuit. The plurality of cathodes K are formed by a plurality of lower electrodes 11 formed by data lines 27 wired in the vertical direction (up and down direction in FIG. 1) and scanning lines 21 wired in the horizontal direction (left and right direction in FIG. 1). The display area AR is formed at the intersections with the plurality of upper electrodes 13.

  As in FIG. 17, display data is supplied from the data driver 1 to the data line 27 via the switch 4. The data driver 1 is connected to drive circuits DD1, DD2, DD3, DD4,... Corresponding to the data lines 27, respectively. The scanning lines (scan lines) 21 are sequentially scanned with a scanning signal applied from the scan driver 2. The scan driver 2 is connected to the scanning circuits SD1, SD2, SD3, SD4,. The data line 27 is provided with a high-pass filter HPF in parallel, and the switch 4 is connected to the data line 27 with any of the drive circuits DD1, DD2, DD3, DD4,. It is installed to switch between.

In the display period, the switch 4 connects the data driver 1 to the data lines 27 and supplies display data to the data lines 27 from the drive circuits DD1, DD2, DD3, DD4,. A state in which the switch 4 is connected to the data line 27 side is shown as a high level (H) state in FIG. This display is performed in the display period T _D of one field F of the image signal (video signal) shown in FIG. That is, the scanning circuits SD1, SD2, SD3, SD4,... Of the scan driver 2 sequentially apply scanning signals to the scan lines 21. In FIG. 3, the scanning signals are denoted by SD1, SD2, SD3, SD4,. This scan signal is applied to the scan line 21 to which SD1, SD2, SD3, SD4,... Are applied, that is, the lower electrode of the cathode K connecting the upper electrode to the selected scan line, the drive circuits DD1, DD2 of the data driver 1 , DD3, DD4,... Is supplied with display data (indicated by DD1, DD2, DD3, DD4,...), And electrons emitted from the upper electrode strike the phosphor and excite it. It emits light of a predetermined wavelength.

1 line display period T _D is finished becomes flyback period (blanking period) T _B moving to the next line, the switch 4 is switched to the high-pass filter HPF side. In FIG. 3, the switch 4 is shown as being at a low (L) level. Similarly, in the blanking period T _B, the scan driver 2 the scanning circuit SD1, SD2, SD3, SD4, ··· is sequentially applied to the scanning signal to the scan line 21. A pulse voltage having a predetermined width and a predetermined wave height as shown in FIG. 20A is applied to the data line 27 selected by this scanning signal from the driving circuits DD1, DD2, DD3, DD4,. This pulse voltage may be approximately the same as the level corresponding to the maximum gradation of the display data, for example. The resistance R of the high-pass filter HPF uses the wiring resistance of the lower electrode (data line), but an external resistor may be used depending on the resistance value of the wiring material.

This pulse signal passes through the high-pass filter HPF to obtain a positive / negative pulse voltage (see FIG. 20B) having a short width as shown by dd1, dd2,. A pulse is applied to the lower electrode of the cathode K. By making the width of the pulse voltage of the short positive bias applied to the lower electrode of the cathode K less than the charging time of the cathode K, the trapped electrons are extracted to the upper electrode side (blanking period), and at the same time new Incorrect electrons are injected and emitted from the upper electrode to prevent erroneous light emission. Then, together with a reverse-biased short pulse applied to the cathode K, electrons trapped in the tunnel insulating layer during the display period are extracted. It is also possible to move sequentially all scan lines to the width of the blanking period T _B. However, since the blanking period T _B have a limited time, full scan line, may be applied simultaneously pulse to all the data lines.

  4A to 4D are explanatory diagrams of energy band changes in the process of reducing trapped electrons in Example 1 during the selection period and the non-selection period in the MIM type cathode. FIG. 4A is a schematic diagram of the cathode in a non-selection period in which trapped electrons remain in the tunnel insulating layer (electron acceleration layer) 12 as in FIG. 18E. In this state, a blanking period starts, and a short pulse is applied to the lower electrode 11 as shown in the initial stage of trapped electron erasure in FIG. 4B. As a result, positive and reverse bias are applied.

  In the steady state of trapped electron erasure in FIG. 4C, electrons trapped in the tunnel insulating layer 12 are extracted from the upper electrode 13 to the ground GND and erased. Then, as shown in FIG. 4D, the trapped electrons disappear in the tunnel insulating layer 12, and, similarly to the state shown in FIG. 18B, the next selection waits in the absence of the trapped electrons in the cathode K non-selection period. .

  Thereby, the diode characteristic fluctuation of the cathode due to the trapped electrons is suppressed, and a high-quality image display without an afterimage or luminance reduction can be obtained.

  FIG. 5 is a plan view of a principal part for explaining a detailed configuration example of the pixel included in the cathode substrate of the image display device of the present invention. In FIG. 4, the upper electrode 13 connected to the scanning line bus wiring 21 via the field insulating layer 14 and the interlayer insulating layer 15 is orthogonally crossed on the main surface of the cathode substrate 10 on the lower electrode 11 which is a signal line (data line). The cathode is formed at the intersection. A tunnel insulating layer (electron acceleration layer) 12 below the upper electrode 13 is shown as a rectangle above the upper electrode 13. The upper electrode 13 is formed on the side of the tunnel insulating layer 12 (above the scanning line bus wiring 21) of the pixel selected by the scanning line bus wiring 21. The lower metal 16 and the interlayer insulating layer 15 of the scanning line bus wiring 21, and the field insulating layer. 14 is electrically and reliably connected to the scanning line bus wiring 21 by the tapered portion (arrow A) of the side wall formed by 14. Below the scanning line bus line 21, the pixel is separated from the adjacent pixels by the step (arrow B).

  As an example of the structure of the cathode, the lower electrode 11 is an aluminum-neodymium alloy (Al-2 atomic% Nd), and the tunnel insulating layer 12 having a thickness of about 2 to 10 nm formed by anodizing the surface of the lower electrode 11; Then, the upper electrode 13 is laminated and formed thereon. The upper electrode 13 is formed by sequentially sputtering, for example, gold (Au): 1 nm / platinum (Pt): 1 nm / iridium (Ir): 0.3 nm.

  Next, the detailed structure of the cathode substrate according to the image display device of the present invention will be described with reference to the manufacturing steps shown in FIGS. First, as shown in FIG. 6, a metal film for the lower electrode 11 is formed on the glass substrate 10. An Al-based metal is used as the material of the lower electrode 11. The reason for using an Al-based metal is that a high-quality insulating film can be formed by anodic oxidation. Here, as described above, an Al—Nd alloy in which Nd is doped at 2 atomic weight% was used. For film formation, for example, a sputtering method is used. The film thickness was 100 to 300 nm.

  After film formation, a stripe-shaped lower electrode 11 was formed by a patterning process and an etching process (FIG. 7). The electrode width of the lower electrode 11 varies depending on the size and resolution of the image display device, but is about the pitch of its subpixels (three color subpixels constituting a color pixel), or about 100 to 200 microns. For the etching, for example, wet etching using a mixed aqueous solution of phosphoric acid, acetic acid and nitric acid is used. Since this electrode has a wide and simple stripe structure, resist patterning can be performed by inexpensive proximity exposure or printing.

  Next, a field insulating layer (also referred to as a protective insulating layer) 14 and a tunnel insulating layer 12 are formed to limit the electron emission portion and prevent electric field concentration on the edge of the lower electrode 11. First, a portion to be an electron emission portion on the lower electrode 11 shown in FIG. 8 is masked with the resist film 25, and the other portion is selectively thickly anodized to form the field insulating layer. A field insulating layer 14 having a thickness of about 100 to 200 nm is formed at a formation voltage of 100V. Thereafter, the resist film 25 is removed and the surface of the remaining lower electrode 11 is anodized. For example, when the formation voltage is 6 V, an insulating layer (tunnel insulating layer) 12 having a thickness of about 10 nm is formed on the lower electrode 11 (FIG. 9).

  Next, the spacer is electrically connected to the scanning wiring for disposing the interlayer insulating layer 15, the scanning wiring (also referred to as scanning line bus wiring) serving as a power supply line to the upper electrode 13, and the spacer (see FIG. 15). A metal film to be a spacer electrode is formed by sputtering, for example (FIG. 10). When the field insulating film 14 formed by anodic oxidation has a pinhole, the interlayer insulating layer 15 fills the defect and plays a role of maintaining insulation between the lower electrode 11 and the scanning line bus wiring. A thick Al wiring is used as the metal intermediate layer 17 of the scanning wiring, and a three-layer film sandwiched between the metal lower layer 16 and the metal upper layer 18 is formed. Here, Cr was used for the metal lower layer 16 and the metal upper layer 18. The film thickness of Al is made as thick as possible in order to reduce the wiring resistance. Here, the metal lower layer 16 has a thickness of 100 nm, the metal intermediate layer 17 has a thickness of 4 μm, and the metal upper layer 18 has a thickness of 100 nm. It is also possible to form the metal intermediate layer 17 by screen printing of a conductive paste. Needless to say, the scanning wiring is not limited to the above structure.

  Subsequently, the metal upper layer 18 is processed into a stripe shape orthogonal to the lower electrode 11 by patterning and etching processes. For this etching, for example, wet etching with an aqueous solution of ammonium cerium nitrate is used. (FIG. 11).

  Next, as shown in FIG. 12, the metal lower layer 16 is processed into a stripe shape orthogonal to the lower electrode 11 by patterning and etching processes. Etching is performed by wet etching with a mixed aqueous solution of phosphoric acid and acetic acid. At that time, one side of the metal lower layer 16 (on the electron source forming side, the left side of the cross-sectional view taken along the line BB ′ in FIG. 12) is projected (protruded) from the metal upper layer 18 and is connected to the upper electrode 13 in a later step. Etching back using the metal upper layer 18 as a mask on the opposite side of the metal lower layer 16 (on the side opposite to the electron source formation side, right side of the sectional view taken along the line BB ′ in FIG. 12) To form an undercut (step), and to form a ridge that separates the upper electrode 13 in a later step. Accordingly, it is possible to form the scanning line bus wiring for separating the upper electrode 13 in a self-aligning manner and supplying power. It is also possible to use a silicon film instead of the metal lower layer 16 and form a ridge by undercutting with an isotropic etching characteristic of dry etching. At this time, there is a method of forming an aluminum film so as to cover the cathode side of the scanning wiring to ensure electrical connection with the upper electrode.

Subsequently, the interlayer insulating layer 15 is processed to open an electron emission portion. The electron emission portion is formed in a part of the orthogonal portion of the space sandwiched between one lower electrode 11 in the subpixel and two upper bus electrodes orthogonal to the lower electrode 11. Etching can be performed by dry etching using an etchant mainly composed of CF ₄ or SF ₆ , for example (FIG. 13).

  Finally, the upper electrode 13 is formed. As this film formation method, for example, sputtering film formation is used. As the upper electrode 13, for example, a laminated film of Ir, Pt, and Au is used, and the film thickness is 6 nm here. At this time, the upper electrode 13 has one of the two scanning line bus wirings sandwiching the electron emission portion (on the right side of the cross-sectional view along the line BB ′ in FIG. 14), and has a saddle structure formed by receding the metal lower layer 16. Disconnected. On the other hand, on the left side of FIG. 14, the contact portion (indicated by an arrow 19) of the metal lower layer 16 of the scanning line bus wiring is connected without causing disconnection and is supplied with power (FIG. 14).

It is explanatory drawing of the state (display period in 1 frame) in which the image display by the cathode explaining the Example of the image display apparatus of this invention is performed. It is explanatory drawing of the state (non-selection period: the blanking period in 1 frame) which erase | eliminates the electron trapped by the tunnel insulating layer of the cathode. It is operation | movement explanatory drawing of the Example of the image display apparatus of this invention. It is a schematic diagram of a cathode in a non-selection period in which trapped electrons remain in a tunnel insulating layer (electron acceleration layer). It is a schematic diagram of the energy band in the initial stage of the non-selection period when reverse bias is applied with trapped electrons remaining in the tunnel insulating layer (electron acceleration layer). It is a schematic diagram of the energy band in the steady state of the non-selection period when reverse bias is applied with trapped electrons remaining in the tunnel insulating layer (electron acceleration layer). It is a schematic diagram of the energy band of a non-selection period in a state where trapped electrons are erased from the tunnel insulating layer (electron acceleration layer). It is a principal part top view explaining the detailed structural example of the pixel which has in the cathode substrate of the image display apparatus of this invention. It is a figure which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 6 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 7 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 8 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 9 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 10 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 11 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 12 which shows the manufacturing method of the thin film type electron source of this invention. It is a figure following FIG. 13 which shows the manufacturing method of the thin film type electron source of this invention. It is a cross-sectional schematic diagram explaining the basic structure of the image display apparatus which concerns on this invention. It is explanatory drawing of the operation principle of the thin film type electron source shown in FIG. FIG. 2 is a schematic diagram for explaining a circuit configuration of an image display apparatus configured by arranging cathodes in a two-dimensional matrix to form a display area and combining a drive circuit with the display area. It is explanatory drawing of the energy band in the isolated state in a MIM type | mold cathode. It is explanatory drawing of the energy band in the MIM type cathode without the accumulation charge of the non-selection period. It is explanatory drawing of the energy band in the initial stage of the selection period in a MIM type | mold cathode. It is explanatory drawing of the energy band in the steady state of the selection period in a MIM type | mold cathode. It is explanatory drawing of the energy band with the trap electric charge of the non-selection period in a MIM type cathode. It is explanatory drawing of the initial energy band at the time of the inversion pulse application in the non-selection period in a MIM type cathode. It is explanatory drawing of the energy band in the steady state at the time of the inversion pulse application in the non-selection period in a MIM type | mold cathode. It is explanatory drawing of the energy band of a state with a residual trap charge in the non-selection period in a MIM type cathode. It is a typical circuit diagram of a high-pass filter. The input signal waveform and output signal of the high-pass filter shown in FIG. 19 are explanatory diagrams of the total.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data driver, 2 ... Scan driver, 3 ... Wide-pass filter (high pass filter), 4 ... Switch, 10 ... Cathode substrate, 11 ... Lower electrode (Signal wiring, data) Wire), 12 ... tunnel insulating layer (electron acceleration layer), 13 ... upper electrode, 14 ... field insulating layer, 15 ... interlayer insulating layer, 20 ... phosphor substrate, 21 ... Operation wiring (scanning line bus wiring), 22 ... phosphor, 23 ... spacer, 24 ... anode (anode), 26 ... black matrix, K ... cathode (electron source), AR ··Indicated Area.

Claims (5)

A cathode substrate in which a plurality of cold cathode electron sources are arranged in a matrix to form a display region; and an anode substrate on which a phosphor is disposed opposite to each of the plurality of cold cathode electron sources,
A plurality of signal lines extending in one direction through the display region of the cathode substrate and formed in parallel in the other direction intersecting the one direction;
The signal lines extend in the other direction through an insulating layer, and a plurality of scanning lines formed in parallel in the one direction;
Outside the display area, a signal line driving circuit for supplying a display signal to the signal line and a scanning line driving circuit for applying a scanning signal to the scanning line,
The cold cathode electron source is formed such that the signal line is a lower electrode at an intersection of the signal line and the scanning line, an electron acceleration layer is formed on the lower electrode, and further covers the electron acceleration layer. Having a laminated structure of upper electrodes connected to the scanning lines;
The cold cathode electron source has a display mechanism for obtaining light emission by causing electrons emitted from the upper electrode to collide with the phosphor by applying a positive bias to the upper electrode with respect to the lower electrode,
A circuit for applying a positive bias having a pulse width of τ = Rd × Cd (seconds) or less to the lower electrode to the lower electrode, where Rd is a series resistance of the signal line and Cd is a capacitance. An image display device comprising: In claim 1,
An image display device comprising: a switching switch for switching and connecting the output of the circuit instead of the display signal to the lower electrode. In claim 2,
The image display device, wherein the change-over switch performs the change in a non-display period other than a display period in which the display signal is supplied to the lower electrode. In claim 1,
The image display device, wherein the circuit is a series circuit of the signal line driving circuit and a high-pass filter. In claim 1,
The lower electrode is aluminum or an aluminum alloy, and the electron acceleration layer is an anodized film of the lower electrode.

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