JP2008211214A - Device-specific fil structure for improved annealing uniformity and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor wafer structure which makes the interior of a wafer surface uniform in reflection factor, in order to acquire an uniform temperature change over a wafer whole region, when a rapid thermal annealing process of a semiconductor structure including a combination of different semiconductor materials is carried out. <P>SOLUTION: In a semiconductor wafer structure in which a first device 401 includes epitaxial growth silicon germanium with a first reflection factor, and a second device 402 includes single crystal silicon with a second reflection factor, a uniform reflection factor is obtained by distributing a first device 451 as a non-functionality dummy including silicon germanium, and a second device 452 as a non-functionality dummy including single crystal silicon over the wafer whole region to obtain the same overall ratio and same density as a distribution of the first and the second device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates generally to semiconductor wafers, and more particularly to a semiconductor wafer structure that balances variations in reflection and absorption properties and a method of forming the structure.

  The manufacture of semiconductor wafers typically involves the use of rapid thermal annealing (RTA) processes that affect the electrical properties of active devices on the wafer. In particular, the RTA process can be used to activate the dopant, diffuse the dopant, re-amorphize the structure, repair damage from the ion implantation process, and the like. RTA is typically performed by a powerful halogen lamp-based heating device that allows rapid changes in wafer temperature by directing radiation onto the wafer surface. However, non-uniform temperature changes across the wafer can occur as a result of reflection and absorption variations in different wafer regions (eg, differing by 10 ° C. or more).

  Variations in reflection and absorption properties can be caused by different factors, such as different materials and / or different material thicknesses in different regions of the wafer. These non-uniform temperature changes can change dopant activation, damage repair, etc. across the wafer, thereby causing variations in threshold voltage, sheet resistance, operating current, leakage current, and the like. Thus, non-uniform temperature changes can cause large variations in device performance that are position dependent.

  Recently developed complementary metal oxide semiconductor (CMOS) devices incorporate epitaxially grown silicon germanium (eSiGe) in the source / drain region of p-type field effect transistors to enhance performance. Thus, these devices include both pFETs with silicon-germanium and n-type field effect transistors (nFETs) with single crystal silicon. However, the reflection and absorption characteristics of silicon germanium and single crystal silicon are different and can cause performance variations. In particular, the reflectivity of eSiGe can be up to 10% higher than that of single crystal silicon, which can cause performance variations of up to 20%.

  Similarly, the silicon-on-insulator (SOI) area has one orientation (eg, 110) to enhance the performance of one type of field effect transistor (eg, pFET) and the bulk silicon area is another type. Hybrid orientation (HOT) wafers with different orientations (eg, 100) have been developed to enhance the performance of other field effect transistors (eg, nFETs). However, the SOI area and the bulk silicon area have different reflective properties due to their different thicknesses. In particular, the reflectivity of the SOI area can be up to 15% higher than the bulk silicon area, which can result in performance variations of up to 30%.

  In addition, as technology continues to shrink, annealing ramp times will continue to decrease (eg, up to sub-second ramps), and these faster ramp times will cause reflection and absorption characteristics across the wafer. This is accompanied by greater sensitivity to fluctuations.

US Pat. No. 6,262,435 US patent application Ser. No. 11 / 678,783 US patent application Ser. No. 11 / 678,756 US patent application Ser. No. 11 / 678,799

  Accordingly, there is a need in the art for semiconductor wafer structures and associated techniques that ensure uniform temperature changes across the wafer during the rapid thermal annealing process.

  In view of the above, disclosed herein provides a uniform reflectivity across the wafer to ensure a uniform temperature change across the wafer during rapid thermal annealing (ie, reflective properties). Embodiments of semiconductor structure and related structure forming method using dummy fill structure having various configurations (such as balancing absorption characteristics with each other, ensuring substantially equal reflection and absorption characteristics, etc.) It is. One embodiment allows a fill structure comprising different semiconductor materials to achieve approximately the same overall ratio and density between different semiconductor materials within each region of the wafer and optimally within each sub-region. By distributing over the entire wafer, uniform reflectivity is achieved. Another embodiment provides a fill structure that includes one or more hybrid fill structures that include various proportions of different semiconductor materials, with different semiconductors within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that approximately the same overall ratio and density between materials is achieved. Yet another embodiment provides a fill structure comprising semiconductor materials having different thicknesses, with approximately the same overall between semiconductor materials having different thicknesses within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that ratio and density are achieved.

  More particularly, each embodiment of the semiconductor structure of the present invention includes a wafer having multiple regions where individual dies will eventually be cut. In general, each region will include an integrated circuit and will further include a number of sub-regions that include various different circuits of the integrated circuit. Each of these circuits may consist of both a first type device (eg, a p-type field effect transistor (pFET)) and a second type device (eg, an n-type field effect transistor (nFET)).

  In the first two embodiments of the structure, the two different types of devices can include different materials with different reflective and absorbing properties. These different materials can be selected for optimal field effect transistor performance. That is, each of the first devices can include a first material having a first reflectivity (eg, a pFET with epitaxially grown silicon germanium in the source / drain regions). Similarly, each of the second devices can include a second material having a second reflectivity (eg, an nFET having single crystal silicon in a source / drain region).

  The first embodiment of the structure includes a fill structure (ie, a first fill structure and a second fill structure). The first fill structure is, for example, a non-functional, structured in the same manner as the first device to include a dummy first device (ie, the same first material (eg, silicon germanium) as the first device) Sex device). Similarly, the second fill structure has been structured in the same manner as the second device, eg, to include a dummy second device (ie, the same second material (eg, single crystal silicon) as the second device). Non-functional devices). To achieve uniform reflectivity across the wafer (ie, to balance reflection and absorption characteristics, to give approximately equal reflection and absorption characteristics, etc.), between regions on the wafer and each The distribution of the first and second fill structures between the sub-regions in the region may be changed according to the distribution of the first and second devices.

  More particularly, if each region of the wafer, optimally any given sub-region within each region, has approximately the same overall ratio and density of different materials having different reflectivities, then approximately A uniform reflectivity can be achieved. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie quantity and position) of the first and second fill structures necessary to achieve such reflectivity will also vary.

  The second embodiment of the structure includes at least one hybrid fill structure. The hybrid fill structure includes both a first material (eg, silicon germanium) and a second material (eg, single crystal silicon) in a predetermined ratio. Similar to the previous embodiment, the first and second devices to achieve uniform reflectivity (ie, to balance reflection and absorption characteristics, to provide approximately equal reflection and absorption characteristics, etc.) The distribution of the fill structure over the entire wafer relative to is predetermined.

  More particularly, if each region of the wafer, optimally any given sub-region within each region, has approximately the same overall ratio and density of different materials having different reflectivities, then approximately A uniform reflectivity can be achieved. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie, quantity and location) of the fill structure (including at least one hybrid fill structure having a predetermined ratio of the first material and the second material) necessary to achieve such reflectivity is also As well as the ratio of the first material to the second material in the hybrid fill structure within those regions or sub-regions, it will vary between regions and between sub-regions.

  A third embodiment of the structure includes a hybrid orientation wafer (HOT) wafer. The HOT wafer has a first region having a first orientation (eg, single crystal silicon having a 110 orientation) and a first thickness, a second orientation (eg, single crystal silicon having a 100 orientation) and a second thickness having a second thickness. And two zones. The first area is positioned on the dielectric layer (ie, a silicon on insulator (SOI) area). As a result of the different thicknesses of the first and second areas, the reflection and absorption characteristics between the areas are also different. Similar to the previously described embodiments, each region of the HOT wafer in the third embodiment includes an integrated circuit and further includes a number of sub-regions including various different circuits of the integrated circuit. Each of these circuits may consist of both a first type device (eg, a p-type field effect transistor (pFET)) and a second type device (eg, an n-type field effect transistor (nFET)). However, in this embodiment, the two different types of devices are formed in different silicon areas of the HOT wafer instead of containing different materials, and thus have different crystal orientations of the same semiconductor material, as well as different thicknesses. Therefore, it has different reflection and absorption characteristics.

  This third embodiment also includes a plurality of fill structures (ie, first and second fill structures). The first fill structure can include, for example, a dummy first device having the same thickness and the same reflectivity as the first device. Similarly, the second fill structure can include, for example, a dummy second device having the same thickness and the same reflectivity as the second device. To achieve uniform reflectivity across the wafer (ie, to balance reflection and absorption characteristics, to give approximately equal reflection and absorption characteristics, etc.), between regions on the wafer and each The distribution of the first and second fill structures between the sub-regions in the region may be changed according to the distribution of the first and second devices.

  More specifically, each region of the wafer, optimally any given sub-region within each region, has approximately the same overall ratio and density of materials having different thicknesses and thus different reflectivities. In some cases, a substantially uniform reflectivity can be achieved. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie quantity and position) of the first and second fill structures necessary to achieve such reflectivity will also vary.

Also disclosed is a method for manufacturing the structure.
In a first embodiment of the method, a wafer and a design for an integrated circuit to be formed on the wafer are provided. The integrated circuit design includes a first type device (eg, a p-type field effect transistor (pFET)) that includes a first material having a first reflectivity (eg, epitaxially grown silicon germanium), and a second material having a second reflectivity. Multiple circuits can be included that incorporate both second type devices (eg, n-type field effect transistors (nFETs)) that include (eg, single crystal silicon). Based on the integrated circuit design, the first and second devices that will form the circuit are mapped onto the wafer. Next, based on the mapping of the first and second devices, of the fill structure between regions on the wafer and between sub-regions within each region (ie, of the first and second fill structures). The distribution is predetermined so that the reflectance over the entire wafer is substantially uniform.

  More particularly, the fill structure is distributed such that each region of the wafer, optimally each sub-region within each region, has approximately the same overall ratio and density of different materials having different reflectivities. In this way, a substantially uniform reflectivity (ie balanced reflection and absorption characteristics, approximately equal reflection and absorption characteristics, etc.) can be achieved. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie quantity and position) of the first and second fill structures necessary to achieve such reflectivity will also vary.

  Once the circuit is mapped and the position and amount of the fill structure are predetermined, the first and second devices and the first and second fill structures are formed simultaneously on the wafer. Further, when the first device is formed, for example, a dummy first device (ie, a non-functional device) structured in the same manner as the first device to include the same first material as the first device. By forming, the first fill structure can be formed. Similarly, when the second device is formed, for example, a dummy second device (ie, a non-functional device) structured in the same manner as the second device to include the same second material as the second device. By forming the second fill structure, the second fill structure can be formed.

  The second embodiment of the method also includes providing a design for the wafer and the integrated circuit to be formed on the wafer. The integrated circuit design includes a first type device (eg, a p-type field effect transistor (pFET)) that includes a first material having a first reflectivity (eg, epitaxially grown silicon germanium), and a second material having a second reflectivity. Multiple circuits can be included that incorporate both second type devices (eg, n-type field effect transistors (nFETs)) that include (eg, single crystal silicon). Based on the integrated circuit design, the first and second devices that will form the various circuits are mapped onto the wafer.

  Next, based on the mapping of the first and second devices, the composition and distribution of the fill structure between regions on the wafer and between sub-regions within each region is such that the reflectivity across the wafer is approximately equal. It is predetermined so that it may become. The fill structure may include a first fill structure that includes a first material, a second fill structure that includes a second material, and / or one or more hybrid fill structures that include both materials. it can. Accordingly, determining the composition and distribution of the fill structure determines the distribution (ie, amount and position) of the first fill structure, and determines the distribution (ie, amount and position) of the second fill structure. And determining the distribution (ie quantity and position) of different hybrid fill structures having different predetermined ratios of the first material and the second material.

  More specifically, the fill structure across the wafer for the first and second devices to achieve substantially uniform reflectivity (ie, balanced reflection and absorption characteristics, approximately equal reflection and absorption characteristics, etc.). The distribution of the body (including the hybrid fill structure having a predetermined ratio of the first material to the second material) reflects differently in each area of the wafer, and optimally in each sub-area within each area. It is predetermined to have approximately the same overall ratio and density of different materials having rates. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie, amount and position) of the fill structures (including hybrid fill structures) necessary to achieve such reflectivity will also vary from region to region and from region to region.

  Once the circuit is mapped and the configuration of the different fill structures, and their respective locations and quantities, are predetermined, the first and second devices, and fill structures (including hybrid fill structures) are transferred to the wafer. Can be formed simultaneously.

  A third embodiment of the method includes providing a hybrid orientation (HOT) wafer. The HOT wafer is formed using conventional processing techniques so that the first zone contains 110 oriented single crystal silicon that is optimal for pFET performance and the second zone contains 100 oriented single crystal silicon that is optimal for nFET performance. Can do. Because of the process used to form the first and second areas, they will have different thicknesses. As a result, the first and second areas will have different reflection and absorption characteristics (ie, first reflectivity and second reflectivity, respectively).

  A design for an integrated circuit to be formed on a wafer is also provided. An integrated circuit design can incorporate both a first type device (eg, a p-type field effect transistor (pFET)) and a second type device (eg, an n-type field effect transistor (nFET)). Based on the integrated circuit design and the configuration of the HOT wafer, a first device and a second device are mapped onto the wafer. Specifically, the first and second devices are mapped to be formed in the first and second areas, respectively, to ensure optimal performance. For example, if the first silicon area is 110-oriented and the first device is a pFET, the first device will be formed in the first area to ensure optimal performance. Similarly, if the second silicon area is 100-oriented and the second device is an nFET, the second device will be formed in the second area to ensure optimal performance.

  Next, based on the mapping of the first and second devices, the distribution of fill structures (ie, first and second fill structures) between regions on the wafer and between sub-regions within each region. (I.e., quantity and position) is predetermined such that the reflectivity across the wafer is substantially uniform (i.e., the balance between reflection and absorption properties is balanced, etc.). More particularly, each region of the wafer, optimally any given sub-region within each region, includes a semiconductor material having a first thickness and a first reflectance and a second thickness and a second reflection. A substantially uniform reflectivity can be achieved if it has approximately the same overall ratio and density as a semiconducting material having a reflectivity. The ratio between the first device and the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design, so that The distribution (ie quantity and position) of the first and second fill structures necessary to achieve such reflectivity will also vary.

  Once the circuit is mapped and the position and amount of the fill structure are predetermined, the first and second devices and the first and second fill structures are formed simultaneously on the wafer. The first and second devices, for example, form a pFET having a first orientation (eg, 110) silicon in the first area and an nFET having a second orientation (eg, 100) silicon in the second area on the same HOT wafer. Can be formed using conventional processing techniques. Further, when the first device is formed, the first fill structure is formed, for example, by forming a dummy first device (ie, a non-functional device) that includes the same orientation of silicon having the same thickness. be able to. Similarly, when the second device is formed, the second fill structure is formed, for example, by forming a dummy second device (ie, a non-functional device) that includes silicon of the same orientation and the same thickness. can do.

  These and other aspects of embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. However, it is to be understood that the following description, which sets forth the preferred embodiment of the invention and its many specific details, is given for purposes of illustration and not limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit of the invention, and the embodiments of the invention include all such modifications.

Embodiments of the present invention will be better understood from the following detailed description with reference to the drawings.
The embodiments of the present invention and its various features and advantageous details are more fully described with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Is done. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques have been omitted so as not to unnecessarily obscure the embodiments of the present invention. The examples used herein are merely intended to facilitate an understanding of the manner in which embodiments of the present invention are implemented and to further enable those skilled in the art to practice the embodiments of the present invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.

  As mentioned above, variations in reflection and absorption properties may be caused by different factors such as different materials and / or different material thicknesses in different regions of the wafer. These non-uniform temperature changes can change dopant activation, damage repair, etc. across the wafer, which can cause variations in threshold voltage, sheet resistance, operating current, leakage current, etc. . Thus, non-uniform temperature changes can cause large position-dependent variations in device performance.

  Recently developed complementary metal oxide semiconductor (CMOS) devices incorporate epitaxially grown silicon germanium (eSiGe) in the source / drain region of p-type field effect transistors to enhance performance. Thus, these devices include both pFETs with silicon-germanium and n-type field effect transistors (nFETs) with single crystal silicon. However, the reflection and absorption characteristics of silicon germanium and single crystal silicon are different and can cause performance variations. In particular, the reflectivity of eSiGe can be up to 10% higher than that of single crystal silicon, which can cause performance variations of up to 20%. Similarly, the silicon-on-insulator (SOI) area has one orientation (eg, 110) to enhance the performance of one type of field effect transistor (eg, pFET) and the bulk silicon area is another type. Hybrid orientation (HOT) wafers with different orientations (eg, 100) have been developed to enhance the performance of other field effect transistors (eg, nFETs). However, SOI and bulk silicon areas have different reflective properties due to their different thicknesses. In particular, the reflectivity of the SOI area can be up to 15% higher than the bulk silicon area, which can result in performance variations of up to 30%. Furthermore, as the technology continues to shrink, the anneal ramp time will continue to decrease (eg, up to sub-second ramps), and these faster ramp times will increase the reflection and absorption characteristics across the wafer. This is accompanied by greater sensitivity to fluctuations. Accordingly, there is a need in the art for semiconductor wafer structures and related techniques that ensure uniform temperature changes across the wafer during a rapid thermal annealing process.

  In view of the above, disclosed herein provides a uniform reflectivity across the wafer to ensure a uniform temperature change across the wafer during rapid thermal annealing (ie, reflective properties). A semiconductor structure using a dummy fill structure having various configurations, and a method for forming the related structure, and the like. It is a form. One embodiment allows a fill structure comprising different semiconductor materials to achieve approximately the same overall ratio and density between different semiconductor materials within each region of the wafer and optimally within each sub-region. A uniform reflectivity is achieved by distributing over the entire wafer. Another embodiment provides a fill structure that includes one or more hybrid fill structures that include various proportions of different semiconductor materials, with different semiconductors within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that approximately the same overall ratio and density between materials is achieved. Yet another embodiment provides a fill structure comprising semiconductor materials having different thicknesses, with approximately the same overall between semiconductor materials having different thicknesses within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that ratio and density are achieved.

  More particularly, referring to FIG. 1, each embodiment of the semiconductor structure of the present invention includes a wafer 100 having multiple regions 110 where individual dies will eventually be cut. These regions 110 can be separated by a scribe line 150, for example.

  FIG. 2 shows an exploded view of a region 210 of the wafer structure as seen in FIG. In general, each region will contain an integrated circuit, and a number of sub-regions (eg, static random access memory (SRAM), logic circuitry, etc.) that contain various different circuits of the integrated circuit (eg, 211, 212). Each of these circuits incorporates both individual devices, eg, first type device 201 (eg, p-type field effect transistor (pFET)) and second type device 202 (eg, n-type field effect transistor (nFET)). And complementary metal oxide semiconductor (CMOS) devices.

  FIG. 3 shows an exploded view of a region 310 of the wafer structure as seen in FIG. Until now, the dummy fill structure 300 has uniformly distributed the device density across the entire wafer (eg, as shown in US Pat. Thus, to reduce variations in etch bias and tilt profiles of structures formed at various locations across the wafer, the various devices around the wafer (ie, the first device 301 and the second device 302). Around). These dummy fill structures 300 are typically all of the same type (ie, formed from the same material with the same thickness and constructed in the same manner).

  On the other hand, embodiments of the present invention not only distribute the device density uniformly, but also distribute the reflection and absorption properties uniformly across the wafer, thereby making it uniform during rapid thermal annealing processes. In order to insure a uniform temperature change, a number of different dummy fill structures having a variety of different materials, thicknesses and / or configurations are used.

  Referring to FIGS. 4 and 5, in the first two embodiments of the structure, two different types of devices (eg, 401-402 in FIG. 4 and 501-502 in FIG. 5) have different reflections and Different materials having absorbent properties can be included. These different materials can be selected for optimal field effect transistor performance. More particularly, each of the first devices 401, 501 can include a first material having a first reflectivity (eg, a pFET having epitaxially grown silicon-germanium in the source / drain region). Similarly, each of the second devices 402, 502 can include a second material having a second reflectivity (eg, an nFET having single crystal silicon in a source / drain region).

  FIG. 4 is an exploded view of two adjacent regions 410, 420 of the wafer structure as in FIG. In this first embodiment, the fill structure 450 can include both a first fill structure 451 and a second fill structure 452. The first fill structure 451 is structured in the same manner as the first device 401 to include, for example, a dummy first device (ie, the same first material (eg, silicon germanium) as the first device 401). Non-functional devices). Similarly, the second fill structure 452 may be structured in the same manner as the second device 402, for example, to include a dummy second device (ie, the same second material (eg, single crystal silicon) as the second device 402). Non-functional devices).

  To achieve uniform reflectivity across the wafer (ie, to balance reflection and absorption characteristics, to give approximately equal reflection and absorption characteristics, etc.), between regions on the wafer and each The distribution of the first and second fill structures 451 and 452 between the sub-regions in the region may be changed according to the distribution of the first and second devices 401 and 402. More particularly, for each region 410, 420 of the wafer, optimally for a given sub-region within each region (eg, sub-region 411-412 of region 410, sub-region 421-422 of region 420, etc.). A substantially uniform reflectivity can be achieved when both have approximately the same overall ratio and density of different materials having different reflectivities. That is, each region 410, 420, optimally each sub-region, is the sum of the surface area of the first material in the first device and first fill structure and the second material in the second device and second fill structure. Has approximately the same overall ratio between the total surface area. This same overall ratio can be predetermined, for example, based on the ratio of all first devices 401 on the wafer to all second devices 402 on the wafer.

  Thus, for illustrative purposes only, if the wafer design includes 100 first devices and 300 second devices, a predetermined ratio of first material to second material for each region 410, 420 Should be approximately 1: 3. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution (ie, amount and position) of the first and second fill structures 451, 452 required to achieve uniform reflectivity will also vary.

  For example, each of the regions 410 and 420 may have a ratio of approximately 1: 3 of the first material to the second material (ie, the sum of the surface area of the first material in the first device and the first fill structure and the second device and (Ratio with the sum of the surface areas of the second material in the second fill structure) is shown. However, the circuitry in sub-regions 411-412 of region 410 and the circuitry in sub-regions 421-422 of region 420 are different (ie, they include different numbers and / or configurations of first and second devices 401, 402). Therefore, the distribution of the first and second fill structures 451 and 452 varies between the regions 410 and 420. Further, since the different sub-regions have different ratios of the first device and the second device, the distribution of the first and second fill structures 451, 452 between the different sub-regions may also change.

  FIG. 5 is an exploded view of two adjacent regions 510, 520 of the wafer structure as in FIG. In this second embodiment, one, some, or all of the fill structures can be composed of hybrid fill structures 550. The hybrid fill structure 550 is a fill structure that includes both a first material (eg, silicon germanium) and a second material (eg, single crystal silicon). To achieve uniform reflectivity (ie, to balance reflection and absorption characteristics, to provide approximately equal reflection and absorption characteristics, etc.), across the wafer for the first and second devices 501, 502 The distribution of the fill structures (a first fill structure 556 including a first material, a second fill structure 557 including a second material, and / or one or more hybrid structures 550) is predetermined.

  More particularly, for each region 510, 520 of the wafer, optimally a given sub-region within each region (eg, sub-region 511-513 of region 510, sub-region 521-523 of region 520, etc.). A substantially uniform reflectivity can be achieved when both have approximately the same overall ratio and density of different materials having different reflectivities. That is, each region 510, 520, optimally each sub-region, is a surface area of the first material in the first device 501, a surface area of the first material in the first fill structure 556, and in the hybrid fill structure 550. The sum of the surface areas of the first material, the surface area of the second material in the second device 502, the surface area of the second material in the second fill structure 557, and the surface area of the second material in the hybrid fill structure 550. Can have approximately the same overall ratio. Similar to the previous embodiment, this same overall ratio can be predetermined, eg, based on the ratio of all first devices 501 on the wafer to all second devices 502 on the wafer. Can do.

  Thus, for purposes of illustration only, if the wafer design includes 100 first devices and 300 second devices, a predetermined ratio of the first material to the second material for each region 510, 520 Should be approximately 1: 3. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution (ie, amount and location) of the fill structure, including the hybrid fill structure 550, necessary to achieve uniform reflectivity, is also the first and second materials within the hybrid structure 550. As in the case of the ratio, it varies between regions and between subregions.

  For example, each of the regions 510 and 520 has a ratio of approximately 1: 3 of the first material to the second material (ie, in the first device 510, the first dummy device 556, and any hybrid fill structure 550). The ratio of the total surface area of the first material to the total surface area of the second material in the second device 502, the second dummy device 557, and the hybrid fill structure 550). However, because the circuitry in sub-region 511-512 of region 510 and the circuit in sub-region 521-522 of region 520 are different (ie, they include different numbers and / or configurations of first and second devices 501, 502). , The distribution of fill structures 556, 557, and 550, and the ratio of the first material to the second material in hybrid fill structure 550 may also vary. That is, the first fill structure 556, the second fill structure 557, and / or one or more hybrids having different ratios of the first and second materials to ensure uniform reflectivity. Fill structure 550 (see, for example, hybrid fill structure 551-552) can be formed on the wafer.

  For example, sub-regions that are not very dense (eg, sub-region 513 of region 510 and sub-region 523 of region 520) or sub-regions that already exhibit a predetermined ratio of first material to second material (eg, of region 510) In the sub-region 511), the first hybrid fill structure 551 having the same ratio of the first material and the second material as the predetermined ratio (eg, 1: 3) for each region, and / or the same predetermined The first and second dummy devices 556, 557 in a ratio of However, in sub-regions where the ratio of the first device to the second device is greater or less than the predetermined ratio for each region, additional hybrid fill structures (eg, 552-553) and / or first Different ratios of the dummy device 556 and the second dummy device 557 can be used. For example, in the sub-region 512 of region 510, the larger ratio of the first device to the second device is a second hybrid that has a proportionally greater amount of the second material compared to the first hybrid fill structure 551. A balance can be achieved by the fill structure 552. Alternatively, in the sub-regions 521-522 of the region 520, the smaller ratio of the first device to the second device is a proportionately smaller amount of the second material compared to the first hybrid fill structure 551. A third hybrid fill structure 553 with can be balanced.

  FIG. 6 is an exploded view of two adjacent regions 610, 620 of the wafer structure as in FIG. In a third embodiment of this structure, the wafer 100 comprises in particular a hybrid orientation (HOT) wafer. As shown in FIG. 7, the HOT wafer has semiconductor material areas (ie, first and second areas 751, 752) having different orientations separated from each other by a dielectric layer 780 and an isolation structure 790. That is, the HOT wafer includes a first area 751 having a first orientation (eg, single crystal silicon having a 110 orientation) and a second area 752 having a second orientation (eg, a single crystal silicon having a 100 orientation). Can do. The first area 751 is positioned on the dielectric layer 780 (ie, a silicon on insulator (SOI) area). The second section 752 is positioned adjacent to the first section 751 and is separated from the first section 751 by the separation structure 790. The second area 752 (ie, the bulk silicon area) further extends into and / or through the dielectric layer 780 to the semiconductor substrate. Accordingly, the first and second areas 751-752 have different orientations and different thicknesses (eg, 761 and 762, respectively). As a result of the different thicknesses of the SOI and bulk areas, the reflection and absorption characteristics between the areas 751-752 are also different (ie, the first area 751 has a first reflectivity and the second area 752 has a second reflectivity. Have).

  Referring to FIGS. 6 and 7 in combination, each region of the wafer (eg, 610, 620) includes an integrated circuit, as in the previous embodiment. In general, each region 610, 620 includes an integrated circuit and a number of sub-regions (eg, static random access memory (SRAM), logic circuitry, etc.) that include various different circuits of the integrated circuit (eg, 611 of area 610, 621-622 of area 620, etc.). Each of these circuits is associated with an individual device, eg, a first type device 601 (eg, a p-type field effect transistor (pFET)) and a second type device 602 (eg, an n-type field effect transistor (nFET)). It can consist of complementary metal oxide semiconductor (CMOS) devices that incorporate both. However, in this embodiment, instead of including different materials, two different types of devices 601, 602 are formed in different silicon areas of the HOT wafer so that different crystal orientations of the same semiconductor material as well as different thicknesses. Thus having different reflection and absorption characteristics. For example, the first device 601 can be formed in a first area 751 of a HOT wafer for optimal performance, can have a first thickness 761, and includes a pFET with 110-oriented silicon. The second device 602 can be formed in the second silicon area 752 for optimal performance, can have a second thickness 762, and includes an nFET with 100-oriented silicon. it can.

  Similar to the previous embodiment, each region 610, 620 of the wafer can also include a plurality of fill structures 650 positioned adjacent to the first and second devices 601, 602 of the integrated circuit. In this embodiment, the fill structure 650 can include both a first fill structure 651 and a second fill structure 652. The first fill structure 651 is, for example, the same method as the first device in the first area 751 of the HOT wafer to have a dummy first device (ie, the same thickness 761 as the first device 601 and thus the same reflectivity). A non-functional device formed in Similarly, the second fill structure 652 can be, for example, a dummy second device (ie, the second device 602 in the second area 752 of the HOT to have the same thickness 762 as the second device 602 and thus the same reflectivity). A non-functional device structured in the same way.

  To achieve uniform reflectivity across the wafer (ie, to balance reflection and absorption characteristics, to give approximately equal reflection and absorption characteristics, etc.), between regions on the wafer and each The distribution of the first and second fill structures 651 and 652 between the sub-regions in the region may be changed according to the distribution of the first and second devices 601 and 602. More particularly, for each region 610, 620 of the wafer, optimally for a given sub-region within each region (eg, sub-region 611-612 of region 610, sub-region 621-622 of region 620, etc.). A substantially uniform reflectivity can be achieved if both have approximately the same overall proportion and density of materials having different thicknesses and thus different reflectivities. That is, each region 610, 620, and optimally, each sub-region, includes the total surface area of the semiconductor material having the first thickness 761 in the first device 601 and the first fill structure 651 and the second device 602 and Between the sum of the surface area of the semiconductor material having the second thickness 762 in the two-fill structure 652 has approximately the same overall ratio. This same overall ratio can be predetermined, for example, based on the ratio of all first devices 601 on the wafer to all second devices 602 on the wafer. Thus, for purposes of illustration only, if the wafer design includes 100 first devices and 300 second devices, a predetermined ratio of first material to second material for each region 610, 620 Should be approximately 1: 3. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution (ie, amount and position) of the first and second fill structures 651, 652 required to achieve uniform reflectivity will also vary.

  For example, each of regions 610 and 620 may have a ratio of approximately 1: 3 of a semiconductor material having a first thickness and a semiconductor material having a second thickness (ie, in first device 601 and first fill structure 651). The ratio of the total surface area of the semiconductor material having the first thickness 761 to the total surface area of the semiconductor material having the second thickness 762 in the second device 602 and the second fill structure 652 is illustrated. However, because the circuitry in sub-region 611-612 of region 610 and the circuitry in sub-region 621-622 of region 620 are different (ie, they include different numbers and / or configurations of first and second devices 601 602). The distribution of the first and second fill structures 651 and 652 varies between the regions 610 and 620. Further, since the different sub-regions have different ratios of the first device and the second device, the distribution of the first and second fill structures 651, 652 between the different sub-regions may also change.

Also disclosed is a method for manufacturing the structure.
Referring to FIG. 8 in combination with FIG. 4, in one embodiment of the method of the present invention, a wafer and a design for an integrated circuit to be formed on the wafer are provided (802-804). .

  An integrated circuit design may include a number of circuits (eg, static random access memory (SRAM) and logic circuitry), each of these number of circuits having a first reflectivity, for example, a first reflectivity. A first type device 410 (eg, p-type field effect transistor (pFET)) that includes a material (eg, epitaxially grown silicon germanium) and a second type device that includes a second material (eg, single crystal silicon) having a second reflectivity. Complementary metal oxide semiconductor (CMOS) devices that incorporate both 402 (eg, n-type field effect transistors (nFETs)) may be included (806-808).

  Based on the integrated circuit design, the first device 401 and the second device 402 that will form the circuit are mapped onto the wafer (810). Next, based on the mapping of the first and second devices 401-402, fill structures 450 (ie, first and second fill structures) between regions on the wafer and between sub-regions within each region. The distribution (ie quantity and position) of the bodies 451, 452) so that the reflectivity and absorption characteristics are approximately equal so that the reflectivity across the wafer is substantially uniform (ie, the balance between reflection and absorption characteristics). And so on) are predetermined (812).

  More specifically, each region 410, 420 of the wafer, optimally each sub-region within each region (eg, sub-region 411-412 of region 410, sub-region 421-422 of region 420, etc.). By distributing the fill structure 450 to have approximately the same overall ratio and density of different materials having different reflectivities, a substantially uniform reflectivity can be achieved (814). That is, the distribution of the fill structures 451 and 452 is such that each region 410, 420, optimally each sub-region, has a second surface area of the first material 401 and the first fill structure 451 plus the second surface area. It is predetermined to have approximately the same overall ratio between the total surface area of the second material in device 402 and second fill structure 452. This same overall ratio can be predetermined, for example, based on the ratio of all first devices 401 on the wafer to all second devices 402 on the wafer. Thus, for illustrative purposes only, if the wafer design includes 100 first devices and 300 second devices, a predetermined ratio of first material to second material for each region 410, 420 Should be approximately 1: 3. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution (ie, amount and position) of the first and second fill structures 451, 452 required to achieve a uniform reflectivity will also change.

  Once the circuit is mapped and the position and amount of the fill structure 450 are predetermined, the first and second devices 401, 402 and the first and second fill structures 451-452 are simultaneously formed on the wafer. (818). The first and second devices 401, 402 are, for example, conventional for forming a pFET having an epitaxially grown silicon germanium source and drain region and an nFET having a single crystal silicon source and drain region on the same wafer. It can form using the processing technique of this. Further, when the first device 401 is formed, it is structured in the same manner as the first device, for example, to include the same first material (eg, epitaxially grown silicon germanium source / drain region) as the first device. A first fill structure 451 can be formed 820 by forming the formed dummy first device (ie, non-functional device). Similarly, when the second device 402 is formed, for example, a dummy second structured in the same manner as the second device so as to include the same second material (eg, single crystal silicon) as the second device. A second fill structure 452 can be formed 822 by forming a device (ie, a non-functional device).

  Referring to FIG. 9 in combination with FIG. 5, another embodiment of the method also includes providing a design for the wafer and the integrated circuit to be formed on the wafer (902-904). . An integrated circuit design may include a number of circuits (eg, static random access memory (SRAM) and logic circuitry), each of these number of circuits having a first reflectivity, for example, a first reflectivity. A first type device 501 (eg, p-type field effect transistor (pFET)) that includes a material (eg, epitaxially grown silicon germanium) and a second type that includes a second material (eg, single crystal silicon) having a second reflectivity. Complementary metal oxide semiconductor (CMOS) devices that incorporate both of the devices 502 (eg, n-type field effect transistors (nFETs)) can be included (906-908).

  Based on the integrated circuit design, the first device 501 and the second device 502 that will form various circuits are mapped 910 on the wafer. Next, based on the mapping of the first and second devices 501-502, the composition and distribution (ie quantity and position) of the fill structure 550 between regions on the wafer and between sub-regions within each region. Is predetermined (912-916) such that the reflectivity across the wafer is substantially uniform (ie, the reflection and absorption characteristics are approximately equal to balance the reflection and absorption characteristics, etc.). . The fill structure includes a first fill structure 556 having a first material, a second fill structure 557 having a second material, and / or one or more hybrid fill structures 550 having both materials. Can be included. Accordingly, determining the composition and distribution of the fill structure determines the distribution (ie, amount and position) of the first fill structure, and determines the distribution (ie, amount and position) of the second fill structure. And determining the distribution (ie quantity and position) of different hybrid fill structures having different predetermined ratios of the first material and the second material (see, eg, hybrid fill structures 551-553). Including.

  More specifically, to achieve a substantially uniform reflectivity, the configuration and distribution of fill structures (including hybrid fill structure 550) for the first and second devices 501, 502 are determined for each of the wafers. The regions 510, 520 and optimally each sub-region within each region (eg, sub-region 511-513 of region 510, sub-region 521-523 of region 520, etc.) is approximately of different materials having different reflectivities. Predetermined to have the same overall ratio and density. That is, the structure and distribution of the fill structure is such that each region 510, 520, optimally, each sub-region has a surface area of the first material in the first device 501, a surface area of the first material in the first fill structure 556. And the total surface area of the first material in the hybrid fill structure 550, the surface area of the second material in the second device 502, the surface area of the second material in the second fill structure 557, and in the hybrid fill structure 550 It is predetermined to have approximately the same overall ratio with the total surface area of the second material.

  Similar to the previous embodiment, this same overall ratio can be predetermined, eg, based on the ratio of all first devices 501 on the wafer to all second devices 502 on the wafer. be able to. Thus, for purposes of illustration only, if the wafer design includes 100 first devices and 300 second devices, a predetermined ratio of the first material to the second material for each region 510, 520 Should be approximately 1: 3. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution of fill structures necessary to achieve uniform reflectivity (ie, the amount and location of the fill structures, including the hybrid fill structures 550), and the first material in the hybrid structures 550 Similar to the ratio with the second material, it varies between regions and between subregions.

  For example, each of the regions 510 and 520 may have a ratio of approximately 1: 3 of the first material to the second material (ie, the surface area of the first material in the first device 501, the first material in the first fill structure 556). The total surface area and the surface area of the first material in the hybrid fill structure 550, the surface area of the second material in the second device 502, the surface area of the second material in the second fill structure 557, and the hybrid fill structure 550. The ratio to the total surface area of the second material in FIG. However, because the circuitry in sub-region 511-512 of region 510 and the circuit in sub-region 521-522 of region 520 are different (ie, they include different numbers and / or configurations of first and second devices 501, 502). The distribution of the fill structure including the hybrid fill structure 550 and the ratio of the first material to the second material in the hybrid fill structure 550 may also change.

  For example, sub-regions that are not very dense (eg, sub-region 513 of region 510 and sub-region 523 of region 520) or sub-regions that already exhibit a predetermined ratio of first material to second material (eg, of region 510) In the sub-region 511), the first hybrid fill structure 551 having the same ratio of the first material and the second material (eg 1: 3) as the predetermined ratio for each region and / or the same ratio First and second fill structures 556, 557 can be formed. However, in sub-regions where the ratio of the first device to the second device is greater or less than the predetermined ratio for each region, additional hybrid fill structures (eg, 552-553), first fill structures The body 556 and / or the second fill structure 557 can be used. For example, in the sub-region 512 of region 510, the larger ratio of the first device to the second device is a second hybrid that has a proportionally greater amount of the second material compared to the first hybrid fill structure 551. A balance can be achieved by the fill structure 552. Alternatively, in the sub-regions 521-522 of the region 520, the smaller ratio of the first device to the second device is a proportionately smaller amount of the second material compared to the first hybrid fill structure 551. A third hybrid fill structure 553 with can be balanced.

  Once the circuit is mapped and the position and amount of the fill structure including the hybrid fill structure 551-553 is predetermined, the first and second devices 501, 502 and the hybrid fill structure 551-553 are It can be formed simultaneously on the wafer (918). Similar to the previous embodiment, the first and second devices 501, 502 include a pFET having an epitaxially grown silicon germanium source and drain region and an nFET having a single crystal silicon source and drain region on the same wafer. It can be formed using conventional processing techniques for forming. On the hybrid structure 550, only a portion of the structure is replaced by epitaxially grown silicon germanium.

  Referring to FIG. 10 in combination with FIGS. 6 and 7, yet another embodiment of the method provides a design for a hybrid orientation (HOT) wafer and an integrated circuit to be formed on the wafer. (1001-1006).

  In particular, referring to FIG. 7, a HOT wafer can be formed, for example, by depositing a dielectric layer 780 on a semiconductor substrate 700 and depositing a semiconductor layer on the dielectric layer. The semiconductor layer should be selected to have a different crystal orientation than the semiconductor substrate. The trench can be patterned downwardly into the semiconductor layer and the dielectric layer toward the semiconductor substrate to form a semiconductor material area having a first orientation (eg, first area 751). Next, the same semiconductor material may be epitaxially grown on the substrate in the trench so as to have the same orientation as the substrate to form an additional area of semiconductor material having a second orientation (eg, second area 752). it can. The first region 751 can include, for example, 110-oriented single crystal silicon that is optimal for pFET performance, and the second region 752 can include, for example, 100-oriented single crystal silicon that is optimal for nFET performance. The first and second areas 751, 752 will have different thicknesses due to the process used to form. That is, the first thickness 761 of the first region 751 of the semiconductor material having the first crystal orientation is smaller than the second thickness 762 of the second region 752 of the semiconductor material having the second crystal orientation. As a result, the first and second areas 751, 752 will have different reflection and absorption characteristics (ie, first reflectivity and second reflectivity, respectively) (1001-1003).

  An integrated circuit design may include a number of circuits (eg, static random access memory (SRAM) and logic circuitry), each of which is, for example, a first type device 601 (eg, Complementary metal oxide semiconductor (CMOS) devices that incorporate both a p-type field effect transistor (pFET)) and a second type device 602 (eg, an n-type field effect transistor (nFET)) may be included ( 1004-1006, see FIG.

  Based on the integrated circuit design and the configuration of the HOT wafer, the first device 601 and the second device 602 are mapped onto the wafer (1008). In particular, the first and second devices 601 and 602 are mapped to be formed in the first and second areas 751 and 752, respectively, to ensure optimal performance (1009-1010). For example, if the first silicon area 751 is 110-oriented and the first device 601 is a pFET, the first device 601 will be formed in the first area 751 to ensure optimal performance. (1009). Similarly, if the second silicon area 752 is 100 oriented and the second device 602 is an nFET, the second device 602 will be formed in the second area 752 to ensure optimal performance. (1010).

  Next, based on the mapping of the first and second devices 601-602, a fill structure 650 between regions on the wafer and between sub-regions within each region (ie, the first and second fill structures). The distribution (ie quantity and position) of the bodies 651, 652) so that the reflectivity and absorption characteristics are approximately equal so that the reflectivity across the wafer is approximately uniform (ie, the reflection and absorption characteristics are balanced). And so on))) predetermined (1012). More particularly, each region 610, 620 of the wafer, optimally a given sub-region within each region (eg, sub-region 611-612 of region 610, sub-region 621-622 of region 620, etc.). Are substantially uniform when they have approximately the same overall ratio and density of the semiconductor material having the first thickness and the first reflectivity and the semiconductor material having the second thickness and the second reflectivity. Reflectance can be achieved (1014). That is, the distribution of the fill structures 651 and 652 is such that each region 610, 620, optimally, each sub-region has a first thickness 761 in the first device 601 and the first fill structure 651. It is predetermined to have approximately the same overall ratio between the total surface area and the total surface area of the semiconductor material having the second thickness 762 in the second device 602 and the second fill structure 652. This same overall ratio can be predetermined, for example, based on the ratio of all first devices 601 on the wafer to all second devices 602 on the wafer. Thus, for purposes of explanation only, if the wafer design includes 100 first devices and 300 second devices, the predetermined ratio for each region 610, 620 should be approximately 1: 3. It is. However, the ratio of the first device to the second device and their position in any given region and / or any given sub-region of the wafer will vary depending on the design. The distribution (ie, amount and position) of the first and second fill structures 651, 652 required to achieve a uniform reflectivity will also change.

  Once the circuit is mapped and the position and amount of the fill structure 650 are predetermined, the first and second devices 601, 602 and the first and second fill structures 651-652 are simultaneously formed on the wafer. (1018). The first and second devices 601, 602 have, for example, a pFET having a first orientation (eg, 110) silicon in a first area and a second orientation (eg, 100) silicon in a second area on the same HOT wafer. It can be formed using conventional processing techniques for forming nFETs. Furthermore, when the first device 601 is formed, the first fill structure 651 is structured in the same manner as the first device 601 to include, for example, silicon of the same thickness and the same orientation on the wafer. It can be formed by forming a dummy first device (ie, a non-functional device) formed in the same first area (1020). Similarly, when the second device 602 is formed, the second fill structure 652 is structured in the same manner as the second device 602 to include, for example, silicon of the same thickness and the same orientation on the wafer. Can be formed (1022) by forming a dummy second device (ie, a non-functional device) formed in the same second area.

  FIG. 11 shows a block diagram of an exemplary design flow 1100. The design flow 1100 may vary depending on the type of IC being designed. For example, the design flow 1100 for building an application specific IC (ASIC) may be different from the design flow 1100 for designing standard components. The design structure 1120 is preferably an input to the design process 1110 and may come from an IP provider, core developer, or other design company, or may be generated by a design flow operator. Or may come from other sources. The design structure 1120 includes the circuits of FIGS. 1-7 in the form of a schematic diagram or HDL, ie, a hardware description language (eg, Verilog, VHDL, C, etc.). Design structure 1120 may be stored on one or more machine-readable media. For example, the design structure 1120 may be a text file or a graphical representation of the circuits of FIGS. The design process 1110 preferably synthesizes (or translates) the circuits of FIGS. 1-7 into a netlist 1180 that describes, for example, connections to other elements and circuits in the integrated circuit design; A list of wiring, transistors, logic gates, control circuits, I / O, models, etc. recorded on at least one machine readable medium. This may be an iterative process where the netlist 1180 is re-synthesized one or more times depending on the design specifications and parameters for the circuit.

  The design process 1110 is a set of commonly used, including models, layouts, and symbolic representations for various inputs, eg, a given manufacturing technology (eg, different technology nodes, 32 nm, 45 nm, 90 nm, etc.). Library elements 1130 that can contain elements, circuits and devices, design specifications 1140, characteristic data 1150, verification data 1160, design criteria 1170, and test data file 1185 (which may include test patterns and other test information). Using the input from). The design process 1110 may further include standard circuit design processes such as, for example, timing analysis, verification, design criteria checking, location and route operations, etc. Those skilled in the art of integrated circuit design can recognize the range of possible electronic design automation tools and applications used in the design process 1110 without departing from the scope and spirit of the present invention. The design structure of the present invention is not limited to any particular design flow.

  The design process 1110 preferably converts an embodiment of the invention into a second design structure 1190, along with any additional integrated circuit design or data (if applicable), as shown in FIG. To do. The design structure 1190 is a data format (eg, GDSII (GDS2), GL1, OASIS, or other suitable format for storing such a design structure) used for the exchange of integrated circuit layout data. It resides on a storage medium. The design structure 1190 includes, for example, test data files, design content files, manufacturing data, layout parameters, wiring, metal levels, vias, shapes, data for routing through the manufacturing line, and FIG. Information such as any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown may be included. The design structure 1190 then proceeds to stage 1195 where, for example, the design structure 1190 that has been taped out is published to manufacturing, published to the mask manufacturer, or sent to another designer. Or sent back to the customer.

  Accordingly, disclosed above is a dummy fill structure having a variety of configurations that provides uniform reflectivity across the wafer to ensure uniform temperature variation across the wafer during rapid thermal annealing. Is an embodiment of a semiconductor structure and a related method of forming a structure. One embodiment allows a fill structure comprising different semiconductor materials to achieve approximately the same overall ratio and density between different semiconductor materials within each region of the wafer and optimally within each sub-region. A uniform reflectivity is achieved by distributing over the entire wafer. Another embodiment provides a fill structure that includes one or more hybrid fill structures that include various proportions of different semiconductor materials, with different semiconductors within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that approximately the same overall ratio and density between materials is achieved. Yet another embodiment provides a fill structure comprising semiconductor materials having different thicknesses, with approximately the same overall between semiconductor materials having different thicknesses within each region of the wafer and optimally within each sub-region. Uniform reflectivity is achieved by distributing across the wafer so that ratio and density are achieved.

  The inventors of the above embodiments have the following additional inventions relating to the reflection and absorption properties of the wafer during rapid thermal annealing, each of which is filed concurrently with this application and is hereby incorporated by reference in its entirety: (1) U.S. Patent Application No. 11 / 678,783 entitled "Localized Temperature Control During Rapid Thermal Anneal" Patent application 3 entitled "Wafer Structure With Balanced Reflectance And Absorption Characteristics For Rapid Thermal Anneal Uniformity" and (3) "Localized Temperature Control During Rapid Thermal Anneal" of US Patent Application No. 11 / 678,799 It should be noted that the inventions related to Patent Document 4 filed at the same time have been made.

  The above description of specific embodiments sufficiently clarifies the general nature of the invention, and others can apply such knowledge to various embodiments without departing from the generic concept by applying current knowledge. Can be easily modified and / or adapted for use with such applications, and such adaptations and modifications should and should be encompassed within the meaning and scope of equivalents of the disclosed embodiments. Is intended to be. It should be understood that the terminology or terminology used herein is for the purpose of description and is not limiting. Accordingly, one of ordinary skill in the art may implement the embodiments of the invention with modifications within the spirit and scope of the appended claims.

1 is a schematic diagram illustrating an exemplary wafer. FIG. 1 is a schematic diagram illustrating an exemplary integrated circuit. FIG. FIG. 3 is a schematic diagram illustrating a fill structure incorporated in a wafer structure. It is the schematic which shows embodiment of the structure of this invention. It is the schematic which shows another embodiment of the structure of this invention. It is the schematic which shows another embodiment of the structure of this invention. 1 is a schematic diagram illustrating an exemplary hybrid orientation (HOT) wafer. FIG. 3 is a flow diagram illustrating an embodiment of the method of the present invention. 6 is a flow diagram illustrating another embodiment of the method of the present invention. 6 is a flow diagram illustrating yet another embodiment of the method of the present invention. 2 is a flow diagram of a design process used for semiconductor design, manufacturing, and / or testing.

Explanation of symbols

100: Wafers 110, 210, 310, 410, 420, 510, 520, 610, 620: regions 201, 301, 401, 501, 601: first devices 202, 302, 402, 502, 602: second devices 211, 212, 411, 412, 421, 422, 511, 512, 513, 521, 522, 523, 611, 612, 621, 622: Sub-regions 300, 450, 650: Fill structure 550: Hybrid fill structure 700: Semiconductor substrate 751: first area 752: second area 761: first thickness 762: second thickness 780: dielectric layer

Claims (11)

A wafer,
A plurality of first devices on the wafer, the first device comprising a first material having a first reflectivity;
A plurality of second devices on the wafer, the second device comprising a second material having a second reflectivity different from the first reflectivity;
A plurality of first fill structures and second fill structures on the wafer, wherein the first fill structure includes the first material, the second fill structure includes the second material, The first fill structure and the second fill structure over the entire wafer with respect to one device and the second device are provided so that the reflectance is substantially uniform over the entire wafer. 1 fill structure and the second fill structure;
A semiconductor structure comprising: The wafer includes multiple regions;
In each of the regions, the first fill structure and the second fill structure with respect to the first device and the second device have a ratio of the first material to the second material in each of the regions. The semiconductor structure according to claim 1, which is provided so as to be substantially the same. A wafer,
A plurality of first devices on the wafer, the first device comprising a first material having a first reflectivity;
A plurality of second devices on the wafer, the second device comprising a second material having a second reflectivity different from the first reflectivity;
A plurality of fill structures including at least one hybrid fill structure, wherein the at least one hybrid fill structure includes both the first material and the second material, the first device and the The plurality of fill structures provided to the second device so that the reflectivity is substantially uniform over the entire area of the wafer;
A semiconductor structure comprising: The wafer includes multiple regions;
In each of the regions, the plurality of fill structures are provided with respect to the first device and the second device so that a ratio of the first material to the second material is substantially the same in each of the regions. The semiconductor structure according to claim 3.   The semiconductor structure according to claim 3, wherein the ratio of the first device to the second device is different in different regions of the wafer, and the plurality of fill structures are provided differently.   4. The semiconductor structure according to claim 3, wherein in different sub-regions in at least one of the regions, the ratio of the first device to the second device is different, and the plurality of fill structures are provided differently.   The semiconductor structure of claim 3, wherein the at least one hybrid fill structure includes the first material in a predetermined ratio with respect to the second material. A wafer,
A plurality of first devices on the wafer, the first device comprising a semiconductor material having a first thickness;
A plurality of second devices on the wafer, the second device comprising a semiconductor material having a second thickness different from the first thickness;
A plurality of first fill structures and second fill structures on the wafer, wherein the first fill structure includes the semiconductor material having the first thickness, and the second fill structure is the second fill structure. The semiconductor material having a thickness, and the first fill structure and the second fill structure over the entire wafer relative to the first device and the second device have substantially the same reflectance over the entire wafer. The first fill structure and the second fill structure provided to be
A semiconductor structure comprising:   A first area of the semiconductor material having the first thickness and a first orientation; and a second area of the semiconductor material having the second thickness and a second orientation adjacent to the first area. And wherein the first device and the first fill structure are in the first area, and the second device and the second fill structure are in the second area. 9. The semiconductor structure according to 8.   The semiconductor structure of claim 8, wherein the semiconductor material comprises single crystal silicon. The wafer includes multiple regions;
In each of the regions, the first fill structure and the second fill structure with respect to the first device and the second device, the semiconductor material having the first thickness in each of the regions. 9. The semiconductor structure according to claim 8, wherein the semiconductor structure is provided so that a ratio to a semiconductor material having the second thickness is substantially the same.

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