TW200901323A - Structure and method for device-specific fill for improved anneal uniformity - Google Patents

Abstract

Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance and a design structure embodiment thereof. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region.

Description

200901323 IX. Invention Description. [Related application] This application is part of the US patent application 11/678,745 filed on February 26, 2007. The full disclosure of the application will be incorporated. This is for reference. TECHNICAL FIELD OF THE INVENTION The present invention relates generally to semiconductor wafers, and more particularly to a semiconductor wafer structure and a method of forming a structure that balances differences in reflectance and absorption characteristics. [Prior Art] The fabrication of semiconductor wafers typically involves the use of a rapid annealing (RTA) process to affect the electrical properties of the active devices on the wafer. Specifically, the tRTA & order can be used to activate the dopant, diffuse the dopant, make the structure = amorphous, repair damage caused by the ion implantation process, and the like. The RTA is performed by a heating device based on a glare-based halogen lamp that directs the Korean shot to the surface of the wafer to allow a rapid temperature culture of the wafer. However, the difference in reflectance and absorption in different areas of the wafer will cause uneven temperature variations across the wafer (e.g., variation i 〇 C or more than 10 ° C). 1 If the ΐ rate and the suction (4) (4) difference material _ factors are caused, the different thickness of different materials and / or materials in different areas of the old circle is 200901323 degrees. The temperature variation of these uneven sentences will cause changes in dopant activation, damage repair, etc. on the entire wafer, resulting in differences in threshold voltage, sheet resistance, drive current, and leakage current. Therefore, uneven temperature changes will result in significant, position-dependent differences in device performance. Recently, a complementary metal oxide semiconductor (CMOS) device has been developed to incorporate insect-grown germanium (eSiGe) in the source/drain region of a P-type field effect transistor in order to improve performance. Therefore, these devices include both PFETs with germanium and n-type field effect transistors (NFETs) with single crystal germanium. However, the reflectance and absorption characteristics of the stone scorpion and the single crystal yttrium are different, and the performance is dissipated. Specifically, the reflectivity of eSiGe is higher than that of single crystal stone by as much as 10%, resulting in performance dissipation of up to 2%. Similarly, hybrid orientation (H〇T) wafers have been developed with a SOI segment on the insulating layer that has an orientation that enhances a field effect transistor type (eg, PFE^I^ performance (eg, 11〇), and its massive 矽 section has different orientations (such as 'na) that improve the performance of another field of transistor type (eg, NFET). However, due to its different thickness, SOI segment and block 矽 zone & Having different reflectivity characteristics. Specifically, the reflectivity of the s〇I section is as high as 15% of the reflectivity of the block 矽 section, resulting in performance dissipation of up to 3〇〇/Q. The technology continues to progress, the annealing completion time will continue for 200901323 = , 'reduced to the sub-second completion time, and in addition to these more than 20% of the time, 'there is a difference in reflectivity and acceptance characteristics on the entire wafer. Greater sensibility. SUMMARY OF THE INVENTION The present invention discloses a semiconductor structure in which a method of filling a junction 2 far structure is used, which uses a varying configuration of the radiance. f, to provide uniform reflectivity across the wafer (ie, to balance the anti-reflection and recovery properties to ensure reflectivity and absorption characteristics _, near-phase specificity) to ensure rapid annealing on the entire wafer Uniform temperature change during the period. A specific embodiment achieves uniform reflectivity by distributing a fill structure comprising different semiconductor materials across the wafer 'in a per-region and preferably in each sub-region of the wafer, at a different The probability and density between semiconductor materials is achieved. In addition, the specific compensation is obtained by distributing the filling structure including one or more mixed filling structures containing different proportions of varying proportions (4) over the entire wafer. It is preferred to achieve nearly the same total ratio and density between the semiconductor materials in each sub-region of the wafer. Another-specific implementation of the 11% or less square money into the average reflectivity. On a single wafer, the distribution of semiconductor materials containing different thicknesses, so that in each region and preferably in the wafer per-sub = In the meantime, nearly two total ratios and densities are achieved between semiconductor materials having different thicknesses. In particular, each semiconductor structure embodiment of the present invention includes a wafer having a plurality of regions from which the individual dies are ultimately cut. In general, each region includes an integrated circuit and further includes a plurality of sub-regions containing various different circuits of the integrated circuit. Each of these circuits may be comprised of a first type of device (e.g., a p-type field effect transistor (PFET)) and a second type of device (e.g., an n-type field effect transistor (NFET)). In the first two structural embodiments, two different types of devices may comprise different materials having different reflectivity and absorption characteristics. These different materials can be chosen to achieve the best field effect transistor performance. That is, each of the first devices may comprise a first material having a first reflectivity (e.g., a PFET having a stray growth crack in the source and the polar regions). Similarly, each second device may comprise a second reflective material (e.g., an NFET with an early crystal cut in the source/> and polar regions). The first structural embodiment includes a filling structure (i.e., a first filling structure and a second filling structure). For example, the first fill structure can comprise a dummy first device (i.e., an inactive device constructed in the same manner as the first device such that it contains the same first material (e.g., 矽) of the first device). Likewise, for example, the second filling structure can comprise a dummy second device (ie, an inactive device constructed in the same manner as the second device, such that it contains the same second material of the second device (eg, single crystal germanium)) . 200901323 is the uniform reflectivity of the entire wafer (that is, the absorption property of the reflective material which is nearly constant). The distribution of the first and second fill structures in different regions on the wafer and in each region may vary depending on the distribution of the first and second devices.吏 Exactly say 'when each area of the wafer (preferably when each area)

When any of the special sub-regions of the ^) have different reflectivities of different materials 2 and the same total ratio and density, the near-average sentence can be achieved. The ratio of the anti-animation to the second device and its presence in the crystal The position in the upper circle and/or in any particular sub-area will vary depending on the change of the root and the second filling structure to achieve uniform reflectivity (ie, 'quantity and position') will also vary. The second structural embodiment includes at least a configuration. The hybrid fill structure comprises a fill ratio at a predetermined ratio ^; and a second material (e.g., single crystal eve). Like the material of the sheep first (eg, Shi Xi. έ+Φ/Β), the specific embodiment of the first ,, see the uniform reflectivity (ie 'to make the reflectivity and balance, to provide nearly equal reflectivity and suction retention + Decide that the fill structure is allocated on the entire wafer relative to the first it's. The kun of the Jiuji device is the same as the day of the J, and the area of the J-mother (the most cups of the coffin-^ domain) has different reflectivity: = -10- 200901323 Near: The same total ratio and density, the reflection of a nearly uniform sentence can be achieved. Because of the ratio of the first device to the second device and 1 within the two roots and / or any specific sub-region The position of the 'change' padding structure (including at least one of the required distributions (ie, quantity and position) with a predetermined 1 uniform reflectance will vary in different ί domains and in the _ sub-regions, The ratio of the first material to the material: as in any hybrid fill structure within the two or sub-regions of these regions may also vary. The second embodiment of the wafer includes a hybrid directional wafer (Kenting) The HOT wafer may comprise a first orientation (eg, a single crystal germanium having an orientation of 11 turns) and a a first segment of thickness and a second segment having a second orientation (eg, a single crystal germanium oriented with 100 orientations) and a second thickness of the second thickness. The first region is located on the dielectric layer (ie, the upper layer of the insulating layer (ie s 〇 I) segment). The reflectivity and absorption characteristics between the segments also vary due to the different thicknesses of the second and second segments. As with the specific embodiments previously described, the second specific implementation Each region of the HOT wafer in the example includes an integrated circuit and further includes a plurality of sub-regions including various circuits of the integrated circuit. Each of these circuits can be a device of the first type (., p-type field effect) A crystal (PFET) and a second type of device (eg, an n-type field effect ribbon (NFET)). However, in this embodiment, the material is not different, but in different stone regions of the wafer. Two different types of devices are formed in the segment 'so the two different types of devices have 200901323 different and not thicker' and thus have ~ ', ~ ν " 6 melon (four) 唭 brother structure (ie, the first

& and second fill structure). For example, the first fill structure can comprise a dummy first eat having the same thickness and the same reflectivity of the garment. Likewise, for example, the second fill structure can comprise a dummy second device having a second = co-reflectivity. To achieve a uniform reflectance over the entire =0 (ie 'balance the reflectivity and absorption characteristics to provide nearly equal reflectivity and absorption characteristics 曰 in different regions and in different sub-regions within each region And the allocation of the second filling structure may vary according to the first and the first allocation. It is said that each region of the wafer, and preferably any specific sub-region within a region, has a near The same is true: When the total ratio and density of the materials with different reflectivity are: ^ Nearly uniform reflectivity. Because of the ratio of the first device to the second device, it is in any specific region on the crystal. The position within the axis and/or any particular sub-area 3 will vary depending on the design, and the first and second fills: the distribution required to achieve a uniform reflectance (ie, the amount and position will vary) The method of forming the above structure is also disclosed. -12- 200901323

In a first method embodiment, a wafer and a design for forming an integrated circuit on the wafer are provided. The integrated circuit design can include a plurality of circuits that incorporate a first type of device (eg, a P-type field effect transistor (PFET)) having a first reflective first material (eg, a silicon grown germanium) and A second type of device having a second reflective second material (eg, single crystal germanium) (eg, an n-type field effect transistor (NFET)). Mapping the on-wafer based on the integrated circuit will form the first and second events of the circuit. Then, based on the mapping of the first and second devices, the allocation of the filling structures (ie, the first and second filling structures) in different regions on the wafer and in different sub-regions in each region is determined in advance, The reflectivity across the wafer is nearly uniform. The 汉 隹 ❿ 的 的 的 的 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿And preferably, each sub-region within each region has a total ratio and density of nearly identical materials of different reflectivity. Since the ratio of the first device to the second device and its location within the wafer and/or any particular sub-region _ position will vary according to the design, m is configured to achieve a uniform distribution (ie, quantity and position). ) will also change. Once the mapping circuit and the position and amount of the filling structure are predetermined, -13· 200901323 simultaneously forms the first and second devices and the first and second filling structures on the wafer. In addition, as the first device is formed, it may be formed, for example, by forming a dummy first device (ie, no action device) of the same first material of the first device in the same manner as the first device. Fill the structure. Similarly, as the second device is formed, it can be constructed by forming a second device of the same second material of the device (ie, no action rotation) by forming the second device in the same manner. Two filled structures. The second embodiment of the method similarly includes the design of providing the wafer and the integrated circuit formed in the crystal. The integrated circuit can include a circuit that is incorporated into the first material having the first reflectivity (eg, epitaxial and type-type devices (eg, 场-type field effect transistor (PFET)) type A second type of two reflective second material (eg, single crystal germanium) is a two-n-type field effect transistor (NFET). Based on the integrated circuit design (4), the mapping will form the first device of the various circuits and the second device on the first circle in different regions and in each: = shot, pre-determined crystal filling structure composition and sub-== Nearly different hooks in different sub-areas. The filling structure may comprise a structure in which the reflectivity on the wafer is filled, and the first filling of the second material comprising the second material comprises a mixture of two materials, a structure, and a mouth structure. Therefore, it is decided that the filling junction -14 - Ο Ο 200901323 ====:, the allocation of the structure (that is, and the decision to have the -::; ί mixed filling structure of the distribution w, f and m pre-expansion rate is more clear To achieve a nearly uniform, nearly equal reflection of the second = ® upper fill structure (including the first fill ratio of the first material containing the first fill ratio of the filling structure) relative to the first - and so that the wafer per-area And preferably, the total ratio and density of materials having nearly the same reflectivity in each of the two (four) "! + regions. Since the first device is placed on the second device and in any particular area of the wafer and/or Or in any special two or two: the position will vary according to the design 'fill structure if, mixed fill structure' to achieve the uniform reflectivity required for the separation) in different areas and in the same sub The region maps the pen path and once the different filling structures are determined, and the configuration of the t mesh and the amount is set, the first and the tenth and the filling structure (including any mixed filling structure) can be simultaneously formed on the wafer. A second method embodiment includes a wafer that provides hybrid directional wafer (HOT). The ττ wafer can be formed using conventional processing techniques, -15- 200901323 3 paragraph = 11 () fiPFET performance is the best orientation sheet:: 曰: the first section contains the best performance for bribery Ergu has the same thickness due to the procedures used to form the first and second sections. Therefore, the first and second sections will have rate and absorption characteristics (i.e., first-reflectivity and second reflectivity, respectively).

The design of the integrated circuit formed on the Japanese yen. Integral two-in-one-type device (eg, p-type field effect transistor and first type device (eg, n-type field effect transistor. Based on integrated circuit design and configuration of HOT wafer, in crystal The mapping of the first device and the second device. Specifically, the mapping of the first and the younger = device makes it divided into the first and the second segment, to ensure optimal performance. For example, if the first stone eve The segment is 11〇 oriented and the first device is a PFET, then the first device will be formed in the first segment to ensure optimal performance. 'Similarly, if the second segment is 1〇〇 oriented and the second farm The second device will be formed in the second segment to ensure optimal performance. Then, based on the mapping of the first and second devices, the filling structure (ie, the first and second filling structures) is predetermined in the crystal. The distribution (ie, amount and position) in different regions of the circle and in different sub-regions within each region makes the reflectivity across the wafer nearly uniform (ie, balances the known reflectance and absorption characteristics) Etc.) More specifically, when each area of the crystal-16-200901323 circle ( Preferably, when the first thickness and the first reflective semiconductor material and the second thickness and the second reflective semiconductor material have nearly the same total ratio and density in any particular sub-region within each region) Nearly uniform reflectivity can be achieved. Since the ratio of the first device to the second device and its position in any particular area on the wafer and/or in any particular sub-area will vary depending on the design, first And the distribution (ie, amount and position) required for achieving a uniform reflectance in the second filling structure will also vary. Once the mapping circuit and the position and amount of the filling structure are predetermined, the first and the first on the wafer are formed. a second device and first and second fill structures. For example, a PFET can be formed in a first segment of a first orientation (eg, 110) on the same HOT wafer and in a second orientation (eg, 100) The second section of the crucible forms a conventional processing technique for the NFET to form the first and second devices. Additionally, as the first device is formed, for example, a dummy first device comprising the same orientation 相同 of the same thickness can be formed ( which is, Actuating means) forming a first filling structure. Likewise, as the second means is formed, for example, a second filling can be formed by forming a dummy second means (ie, no acting means) comprising the same orientation enthalpy of the same thickness The above and other aspects of the specific embodiments of the present invention will become more apparent from the following description and the accompanying drawings. <RTIgt; </ RTI> <RTIgt; 200901323 is intended to be illustrative only and not limiting. The specific embodiments of the present invention may be modified and modified without departing from the scope of the invention. Such a modification. [Embodiment] Unlimited restrictions will be explained in detail with reference to the accompanying drawings and the following description.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention, as well as various features and advantageous details thereof, are described in detail. I mean, the characteristics of the schema solution may not be in accordance with the system. The 鳞 鳞 鳞 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The use of the exemplification of the present invention is only to facilitate understanding of the implementation of various embodiments of the present invention, and to enable the skilled artisan to practice the various aspects of the present invention. Therefore, the examples are not to be considered as limiting the scope of the specific embodiments of the invention. As noted above, the difference in reflectance and absorption characteristics is caused by different causes, such as different thicknesses of different materials and/or materials in different regions of the wafer. These uneven temperature changes will cause the activation of the tamper on the entire wafer, damage repair, etc., resulting in a wide variation of the threshold, sheet resistance, drive current, leakage current, etc. Uniform temperature changes will make the performance of the device significantly similar to the recent development of complementary metal oxide semiconductor (CMOS) skirts for the purpose of -18-200901323 isotropic 忐, incorporated in the source/no-polar region of the p-type field effect transistor Epitaxially grown germanium (eSiGe). Therefore, these devices include both PFETs with germanium and n-type field effect transistors (NFETs) with single crystal germanium. However, the reflectance and absorption characteristics of germanium and single crystal germanium are different, and thus the performance is dissipated. Specifically, the reflectivity of eSiGe is higher than that of single crystal germanium by up to 10%, resulting in performance dissipation of up to 2%. Similarly, Ο

C ^ has developed a combined orientation (HOT) wafer with a germanium (s〇I) region on the insulating layer and a trend in the performance of a field-effect transistor type (eg, pFET) in the south (eg '110) And its block-like stellite section has a (5) orientation (eg, 100) that improves the performance of another field-effect transistor type (eg, NFET). However, due to their different thicknesses, the SOI segment and the block-like segment have a reflectivity characteristic of not f. Specifically, the reflectivity of the SQI segment is higher than the reflectivity of the (10)-like Shixia segment by as much as 15% 'causing the performance to dissipate as much as the other'. As the technology continues to progress, the annealing completion time will be reduced to the next second. The completion time), in addition to the completion time of these ^, is accompanied by the reflection on the entire wafer, the sensitivity difference is even greater. Therefore, in the art, the entire wafer is uniform during the annealing process: a scoop half V-well wafer structure and related technology. For example and description, the related method disclosed in the present invention is a method for implementing a semiconductor structure, which uses a variable configuration of the dummy structure to provide uniform reflectivity on the entire wafer (ie, to make the reverse... And the absorption characteristics are balanced 'to provide nearly equal reflectivity•19-200901323 and absorption characteristics, etc.) to ensure uniform temperature variation over the entire wafer during rapid annealing. A specific embodiment achieves a uniform reflectance by dispensing a fill structure comprising different semiconductor materials throughout the wafer such that it is different in each region and preferably in each sub-region of the wafer. Nearly the same total ratio and density are achieved between semiconductor materials. Another embodiment achieves uniform reflectivity by dispensing a fill structure comprising one or more mixed fill structures of varying semiconductor materials of varying proportions across the wafer, such that in each region and preferably Nearly the same total ratio and density are achieved between different semiconductor materials in each sub-area of the wafer. Yet another embodiment achieves uniform reflectivity by dispensing a fill structure comprising semiconductor materials of different thicknesses over the entire wafer such that in each region, and preferably within each sub-region of the wafer, Nearly the same total ratio and density are achieved between semiconductor materials having different thicknesses. With particular reference to Figure 1, each semiconductor structure embodiment of the present invention includes a wafer 100 having a plurality of regions 110 from which individual dies are finally cut. These regions 110 can be separated, for example, by a score line 150. 2 depicts an exploded view of region 210 of the wafer structure of FIG. In general, each region includes an integrated circuit, and further includes a plurality of sub-regions (such as 211, 212), which contain various integrative circuits -20-200901323: (, ^ ° 'static random access memory ( SRAMs), logic circuits, each of these circuits can be reduced by side devices, for example, incorporating a jaw type 2〇1 (such as a p-type field effect transistor (pFET)) and a second type of 2〇2 (such as an n-type) Complementary Metal Oxide Semiconductor (CMOS) device for Field Effect Transistor (NFET).

Fig. 3 is an exploded view of the area 31Θ of the wafer structure shown in Fig. 1. In the past, the dummy fill structure 300 incorporated into the wafer was a variety of circuits (i.e., near the first device 310 and the second device) for evenly distributing the device money across the wafer, and thereby reducing the overall </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; These dummy fill structures are generally all of the same type (i.e., made of the same material, of the same thickness, and configured in the same manner).

Conversely, embodiments of the present invention use a plurality of different dummy fill structures of varying materials, thicknesses, and/or configurations to evenly distribute device density evenly across the wafer and evenly distribute reflectance And absorption characteristics, thereby ensuring rapid annealing to uniform temperature changes. / S Referring to Figures 4 and 5' In the first two structural embodiments, two different types of devices (such as 401-402 of Figure 4 and 5〇1_5〇2 of Figure 5) -2]- 200901323 contain ^ Reflectivity and money characteristics (four) material. In order to achieve the performance of Jiajing 5, these different materials can be selected. More specifically, the "brothers" - devices 401, 5"1 may comprise a first material having a first reflectivity (e.g., a PFET having a telecrystal growth in the source/drain region). Similarly, each second farm 4, 2, 5, 2 may comprise a second material having a second reflectivity (e.g., an NFET in the source/drain region and single crystal). Ο Ο Figure 4 shows the sub-quote of the two adjacent areas of the wafer structure, 41〇, · 420. In this first embodiment, the filling structure 450 can include a first filling structure 451 and a second filling structure 452. For example, the first fill structure 451 can include a dummy first device (i.e., an inactive device constructed in the same manner as the first device 401, such that it contains the same first material (e.g., helium) at the first device 401). Likewise, for example, the 'second fill structure 452 can include a dummy second device (ie, an inactive device constructed in the same manner as the second I-set 402, such that it contains the same second material in the second device 402 (eg, Crystal 矽)). In order to achieve uniform reflectivity across the wafer (ie, to maintain reflectivity and absorption characteristics balanced to provide nearly equal reflectivity and absorption characteristics, etc.), according to the first and second devices 4〇1, 402 The assignment of the first and second fill structures 45 452 in different regions on the wafer and in different sub-regions within each region varies. More specifically, 'When each area of the wafer is 41〇, 420 (preferably -22-200901323), any specific sub-area in each area of the clothing (such as the sub-area of the area 41〇 411_412, the sub-area of the area 420) When the regions 421-422, etc.)) have a total ratio and density of different materials having nearly the same different reflectivities, the town achieves a nearly uniform reflectance. That is, each region 41〇, 42〇 (preferably each sub-region) in the first device and the first filling structure, the sum of the material/surface area and the second material and the second material in the second and second filling structures There is almost the same total ratio between the sums. This same overall ratio can be predetermined, and this total ratio can depend, for example, on the ratio of all of the first devices 401 on the wafer to all of the second devices 4〇2 on the wafer. For the purpose of description, if the wafer design includes one hundred first garments and two hundred second devices, the predetermined ratio of the first material to the second material of each of the regions 410, 420 should be approximately 1: 3. However, the ratio of the first device to the second device and its location in any particular area on the wafer and/or in any particular sub-area will vary depending on the design, the first and second filling structures 45 452 The distribution (ie, quantity and location) required to achieve a uniform reflectance will also vary. For example, regions 410 and 420 each describe a nearly 1:3 ratio of the first material to the second material (ie, the sum of the 'th surface area of the first device and the first filling structure' versus the second device and the second filling structure The ratio of the total surface area of the second material). However, since the circuit in sub-area 411 412 of area 410 and sub-area 421-422 of area 420 is not -23·200901323 (ie, 冬冬古丁401, 402,), &gt;_ the same, the number and/or configuration The distribution of the first and second device regions 410 3 and the second filling structures 451, 452 has a variation in the region. In addition, due to the difference between the different sub-second fillings and the ratio of the clothes to the second device, the first and the other are changed. . The allocation of Bu 452 is also between different sub-areas.

520 is one and two of two adjacent regions 510' of the wafer structure of FIG. In this second embodiment, the fill structure t-fill or all of the fill structure may comprise a hybrid fill structure 550. Mixed (such as a single 包含 containing the first material (such as 矽锗) and a second material 射 rate: t:: real: sentence uniform reflectivity (ie 'to make the opposite and absorb the special (four) + balance to provide almost equal The second of the reflectivity materials determines the filling structure (including: including the first -, the filling, the second filling::, and / or - or a plurality of mixed structures 55) The distribution of the entire wafer relative to the second and the second device 5〇1, 5〇2. ^ , specifically, each region of the wafer 510, 520 (preferably when any in each region) A specific sub-area (eg, sub-area 511_5U of area 51Θ, sub-area of area 52〇 like _523, etc.)) has a total ratio of three different materials of different reflectivity and a density of 3 inches, which can achieve near uniformity The reflectivity. That is, each region 51〇, 520 (preferably each sub-region) is at the first -24-Ο Ο 200901323 material surface area of the first device 5〇1, any first filling structure 556 The 550th eve flute "the first material surface area, and any mixed filling structure 55 brother: between the sum of the surface area of the material, has a near phase Ratio of mother to ί: as with the specific embodiments described above, the same ratio can be predetermined, and the total ratio can depend, for example, on the ratio of wafer training to all second devices 502 on the wafer. A 2' is only a description (4) 'If the wafer design includes - a hundred f-coating and three hundred second devices, then the predetermined ratio of the first material to the second material of each region 51〇, 52〇 should be close 1:3. However, the ratio of the second device to the second device and its position in the wafer or in any particular sub-region will be based on the configuration, the filling structure (including any hybrid filling structure 550). The distribution (ie, amount and position) required to achieve uniform reflectance may vary in different regions and in the non-sub-region, and the first material in any hybrid structure 550 versus the second material The ratio will also vary. 'For example, Q fields 510 and 520 each describe a nearly 1:3 ratio of the first material to the second material (ie, first device 51〇, any first dummy device 556, and any hybrid fill) Structure 55 第 - material table = product sum for the second device 502, any The second dummy device 557, and the ratio of the total surface area of the second material in the hybrid filling structure 550. However, due to the circuit of the sub-regions 511-512 in the region 510 and the sub-regions 521-522 in the region 520 The circuit is different (i.e., it contains different numbers and/or configurations of first and second devices 501, 502), the distribution of fill structures 556, 557, and 550, and the first material pair in any hybrid fill structure 550 The ratio of materials will vary. That is, a first fill structure 556, a second fill structure 557, and/or one or more having a different ratio of first material to second material may be formed on the wafer. The fill structure 550 is mixed (see, for example, the hybrid fill structures 551-552) to ensure uniform reflectivity. For example, in a less dense sub-region (such as sub-region 513 of region 510 and sub-region 523 of region 520) or a sub-region that has a predetermined ratio of first material to second material (eg, sub-region of region 510) In 511), a first mixed filling structure 551 comprising a first material to a second material ratio (eg, 1:3) having the same ratio as a predetermined ratio of each region, and/or first and second ratios of the same predetermined ratio may be used. Two dummy devices 556, 557. However, in a sub-region where the ratio of the first device to the second device is greater than or less than a predetermined ratio of each region, an additional hybrid fill structure (eg, 552-553) and/or a first dummy device 556 may be used for the second dummy Different ratios of devices 557. For example, in sub-region 512 of region 510, a second hybrid fill structure 552 having a second, greater amount of material than the first hybrid fill structure 551 can be utilized to balance a larger ratio of the first device to the second device. . Alternatively, in the sub-regions 521 - 522 of the region 520 -26 - 200901323 'the third hybrid filling structure 553 ' having a smaller ratio than the first hybrid filling structure 5 51 may be utilized to balance the first device pair A smaller ratio of the second device. Figure 6 depicts an exploded view of two adjacent regions 61, 620 of the wafer structure of Figure 1. In this third structural embodiment, the wafer 1 〇〇 specifically includes a hybrid directional wafer (HOT) wafer. As depicted in Figure 7, the HOT wafer has segments of semiconductor material of different orientations (i.e., first and second sections 751, 752) that are isolated from each other by dielectric layer 78 and isolation structure 790. That is, the HOT wafer can include: a first segment 751 having a first orientation (eg, a single crystal germanium having an orientation of 11 turns) and a second segment 752 having a second orientation (eg, having a orientation of 1) Single crystal stone eve). The first segment two 51 is located on the dielectric layer 780 (i.e., the upper layer of the insulating layer (s〇I)). The first section 752 is positioned adjacent to the first section 751 and is separated from the first section 751 by an isolation structure 790. The second segment, 2 (i.e., the bulk germanium segment), additionally extends to the dielectric layer 78 and/or through the dielectric layer 78A to the semiconductor substrate. Therefore, the first and second sections 751_752 have different orientations and different thicknesses (e.g., 761 and 762, respectively). The reflectivity and absorption characteristics between sections 751_752 also vary due to the different thicknesses of the soi section and the bulky section (ie, the first section 751 has a first reflectivity and the second section 752 has Second reflective). Referring to Figures 6 and 7, in conjunction with the specific embodiments previously described, each region of the -27-200901323 wafer (e.g., 610, 620) includes an integrated circuit. In other words, each of the regions 610, 620 includes an integrated circuit and further includes two sub-regions (eg, 611412 of region 610, region 62 221-622, etc.), which contain various circuits of the integrated circuit. (such as static bear random access memory (SRAM), logic circuits, etc.). Each of these circuits may be comprised of individual devices, for example, incorporating a first type of device 601 (such as a p-type field effect transistor (PFET)) and a second type of device 6〇2&quot; (such as an n-type field effect transistor (NFET) )) A complementary metal oxide semiconductor (CM〇s) device. However, in this particular embodiment, different materials are not included, but two different types of devices 601, 602 are formed in different different segments of the HOT wafer. Thus, the two different types of devices have different The crystal orientation and the same semiconductor material of different thicknesses and thus different reflectance and absorption characteristics. For example, the first device 601 can be formed in the first section 751 of the HOT wafer to have a first thickness 761,

And a PFET that can include 110 directional turns of optimum performance; and the second device 602 can be formed in the second turn section 752, can have a second thickness 762, and can include an orientation of 最佳 optimal performance. NFET. As with the previously described embodiments, each region 610, 620 of the wafer also includes a plurality of fill structures 650 positioned adjacent to the first and second devices 601, 602 of the integrated circuit. In this embodiment, the fill structure 650 includes a first fill structure 651 and a second fill structure 652. The first filling structure 651 includes, for example, a dummy first device (ie, an inactive device formed in the same manner as the phase -28 - 200901323 of the first device in the second segment 751 of the HOT wafer, such that it has the same device 601 as the first device 601 The same thickness 761 and therefore the same reflectivity). Likewise, the second fill structure 652 includes, for example, a dummy second device (ie, an inactive device constructed in the same manner as the second device 602 in the second segment 752 of the HOT such that it has the same thickness 762 as the second device 602 And therefore have the same reflectivity). 〇According to the distribution of the first and second devices 601, 602 in order to achieve uniform reflectivity across the wafer (ie, to maintain reflectivity and absorption characteristics balanced to provide nearly equal reflectivity and absorption characteristics, etc.) The assignment of the first and second fill structures 651, 652 in different regions on the wafer and in different sub-regions within each region is varied. More specifically, each region 610, 620 of the wafer (preferably any particular sub-region within the parent-region) (eg, sub-regions 611-612 of region 610, sub-regions 621-622 of region 620) Etc.)) When the total ratio and density of materials having different thicknesses and thus different reflectivities are similar, a nearly uniform reflectance can be achieved. That is, each region 610, 620 (preferably each sub-region) has a first thickness 761 of semiconductor material surface area sum in the first device 6〇1 and the first filling structure 651 to the second device 602 and Between the sum of the surface areas of the semiconductor material having the second thickness 762 in the second fill structure 652, there is approximately the same overall ratio. This same overall ratio can be predetermined, and this total ratio can depend, for example, on the ratio of all first devices 6〇1 on the wafer to all second devices 602 on the wafer. Therefore, for the purpose of description only, such as -29. 200901323 If the wafer design includes one hundred first devices and three hundred second devices, the predetermined ratio of the first material to the second material of each region 610, 620 should be Almost 1:3. However, since the ratio of the first device to the second device and its position in any particular region on the wafer and/or in any particular sub-region will vary depending on the design, the first and second fill structures 651, 652 The distribution (ie, amount and position) required to achieve a uniform reflectance will also vary. For example, regions 610 and 620 each describe a semiconductor composition of a first thickness 601 and a semiconductor material having a first thickness 761 in a first device 601 and a first filling structure 651. The sum of the surface areas is the ratio of the surface area of the semiconductor material having the second thickness 762 of the second device 602 and the second filling structure 652). However, since the circuits in sub-regions 611-612 of region 610 and sub-regions 621-622 of region 620 are different (ie, they contain different numbers and/or configurations of first and second devices 601, 602), the first The distribution of the second fill structures 651, 652 varies between regions 610 and 620. In addition, since the different sub-regions have different ratios of the first device to the second device, the allocation of the first and second filling structures 651, 652 also varies between different sub-regions. A method of forming the above structure is also disclosed. Referring to FIG. 8 in conjunction with FIG. 4, in the method of the present invention, the implementation of the method -30-200901323 'providing the wafer and the integrated circuit formed on the wafer (802-804) ° integrated circuit design may include a plurality of circuits (such as static memory (SRAM) and logic circuits), and the plurality of circuits: two may include, for example, a complementary metal oxide semiconductor (CM〇s) device, such as a type device 410 (eg, having a reflective type - material (such as Lei = growth 矽锗) p-type field effect transistor (PFET)) and a second type 402 (such as 'the first reflective second material (such as single crystal eve) The type of corpse transistor (NFET) (806-808). Based on the integrated circuit design, the first device 4〇1 and the first device 402 forming the circuit are mapped to the wafer (81〇). Then, based on the mapping of the first and second devices 401-402, the filling structure 450 (ie, the first and second filling structures 451) in different regions on the wafer and in different sub-regions in each region are predetermined. , 452) the distribution (ie, quantity and position), so that the reflectivity on the entire wafer is nearly uniform (ie, the reflectivity and absorption characteristics are balanced, so that the reflectivity and absorption characteristics are nearly phase, etc.) (812 ). More specifically, 'nearly uniform reflectivity can be achieved by allocating a fill structure 450 such that each region of the wafer 41〇, 420 (preferably in each sub-region within each region ( Such as sub-areas 411-412 of area 41〇, sub-area 42M22 of area 420, etc.)) -31 - 200901323

U has a total ratio and density of nearly identical materials of different reflectivity (814). That is, the distribution of the filling structures 451 and 452 is predetermined such that the sum of the first surface areas of the first device 401 and the first filling structure 451 for each of the regions 410, 420 (preferably each sub-region) There is approximately the same overall ratio between the sum of the surface areas of the first materials in the second device 402 and the second filling structure 452. This same overall ratio can be predetermined, and this total ratio can depend, for example, on all of the first device 401 on the wafer and all of the second devices on the wafer 4:2 ratio. Therefore, for the purpose of description only, if the wafer design includes one hundred first devices and three hundred second devices, the predetermined ratio of the first material to the second material of each region 41〇, 42〇 should be approximately 1 . However, since the ratio of the first device to the second device and its position in any particular region on the wafer and/or in any particular sub-region will vary, the first and second filling structures 45 452 are The distribution (ie, amount and position) required to achieve a uniform reflectance will also vary. The mapping circuit and the position and amount of the filling structure are determined in advance, that is, the first and second devices 40 and the second and second filling structures 451 to 452 (818) are simultaneously formed on the wafer. For example, it is possible to use the conventional method of forming a stone-like source and a immersed region with a stray crystal growth on a ^7 circle and a single crystal stone source and a wave region. And second devices 401, 402. In addition, the first filling structure 451 can be formed into a first filling structure 451 by forming a dummy first device (ie, an inactive device) constructed in the same manner, so as to include the same first device as the first device. A material (such as the source/drain region of the epitaxial growth) (82〇). Similarly, as the second device 402 is formed, the second filling structure 452 can be formed to be included with the second device, for example, by forming a dummy second device constructed in the same manner as the second device (ie, inactively mounted) ^The same second material (such as single crystal germanium) (822). In conjunction with Figure 5, McCatur 9, another method embodiment similarly includes the design of providing the wafer and the integrated circuit to be formed on the wafer. (902-904) The integrated circuit design may include a plurality of circuits (eg, static random access memory (SRAM) and logic circuits), and each of these may include, for example, a complementary metal oxide semiconductor (CM〇s) a device that incorporates a first type of device 501 (such as a p-type field effect transistor with a first reflective first material (eg, epitaxial growth germanium) (PFE1^ and a second type device 5G2 (if with a second Reflective second material (such as single crystal ^' η type field effect transistor (NFET)) (806-808). Based on the integrated circuit design, the first device 501 and the second device will form various circuits. 502 is mapped to the wafer (91 〇). Then, based on the first and second devices Xie's @ mapping, the wafer is pre-determined Filling structure composition and distribution (ie, amount and position) in different regions and in different sub-regions of each region, so that the reflectivity on the entire wafer is nearly uniform (ie, 'to make reflectance and absorption The characteristics are balanced, such that the reflectance and absorption characteristics are nearly phased, etc. (10) by (6). Filling 33 - 200901323 The filling structure may comprise: a first filling structure 556 comprising a first material, a second filling structure 557 comprising a second material And/or one or more mixed filling structures 55〇 comprising two materials. Therefore, determining the filling structure composition and the distribution comprises: determining the distribution of the first filling structure (ie, Cao and position), and determining the second filling structure. The distribution (ie, amount and position), and the distribution (ie, amount and position) of the different mixed filling structures of the first predetermined material to the second material at different predetermined ratios (eg, see hybrid filling structure 551-553). More specifically, in order to achieve a nearly uniform reflectivity, it is predetermined that the configuration and distribution of the charging structure (including any mixed filling structure 5 5 相对) relative to the first second device 501, 502 Each region 510, 520 of the wafer (preferably each sub-region within each region (eg, sub-region 511_513 of region 510, sub-region 523 4 of region 52 ))) has nearly the same The total ratio and 妓 of different materials with different reflectivity. It is also said that the configuration and distribution of the pre-shirt filling structure 'cause each area 510, 520 (preferably each sub-area) in the first-loaded i5〇1 The first material surface area, the first material surface area of any first fill 3 556, and the sum of the surface area of any mixed fill structure 550 to the second material f area of the second device 5〇2, any second fill structure Between the second material surface area of 557, the sum of the surface areas of the second material of any mixed fill structure 55Q, there is approximately the same total ratio. -34- 200901323 she = with the specific embodiment described above, the same, , 'B ratio can be determined in advance and the total ratio can be determined, for example, by all the first devices on the wafer = 1, all on the wafer The ratio of the second device 502. Therefore, for the purpose of description, if the wafer design includes one hundred first devices and two hundred first devices, the predetermined ratio of the first material to the second material in each region 510, 520 should be approximately 1 : 3. However, due to the first device, the ratio of the second device and its position in any particular area of the wafer &quot; and / or in any particular sub-area will vary according to the design, the filling structure is to achieve uniformity The required distribution (ie, the amount and location of the filling structure including any such filling structure) will vary in the different = domain and in the non-sub-region, and will be mixed. The ratio of the first material to the second material may also vary, for example, 〇°° and 520, each describing the first material to the second material ', the 'f1/3 ratio (ie, the first device - 〇 〇 - material The surface knows the structure of the material - the surface area of the filling structure 556, and the:: 2: 13 structure 550, the sum of the surface area of the first material, the second surface area of the first material, any second filling structure 557 Ratio of the sum of the second areas in the product and any mixed fill structure 550 However, due to the region 51 〇 neutron circuit and region 52 〇 neutron region 521_522, it contains different numbers and / or configurations of the first and second, 502) 'including any mixed filling structure of the filling junction -35 - 200901323 The distribution of the structure and the ratio of the first material to the second material in any of the hybrid fill structures 550 will vary, for example, in less dense sub-regions (e.g., sub-region 513 and region 520 of region 510) In the sub-region 523) or in a sub-region (such as the sub-region 511 of the region 520) that has been presented with a predetermined ratio of the first material to the second material, the formation may include the same ratio as each region (eg, 1:3) a first mixed fill structure 551 of the first material to second material ratio and/or first and second fill structures 556, 557 in the same ratio. However, the ratio of the first device to the second device is greater or less than each In a sub-region of a predetermined ratio of regions, an additional hybrid fill structure (e.g., 552-553), a first fill structure 556, and/or a second fill structure 557 may be used. For example, in sub-region 512 of region 510, Proportion A hybrid fill structure 551 has a second mixed fill structure 552 of a second amount of material to balance a larger ratio of the first device to the second device. Alternatively, in the sub-regions 521-522 of region 520, a ratio can be utilized A third hybrid fill structure 553 having a second amount of material less than the first hybrid fill structure 551 to balance a smaller ratio of the first device to the second device. Once the mapping circuit and predetermined to include any hybrid fill structure 551- The position and amount of the 553 filling structure allows the first and second devices 501, 502 and the hybrid filling structures 551-553 (918) to be simultaneously formed on the wafer. As with the specific embodiments previously described, it can be used at -36- 200901323

Extreme and immersed area: [The familiar knowledge of FET 癦 5〇2. Part of the hybrid structure 55〇. Referring to FIG. 10 in conjunction with FIGS. 6 and 7

Specifically, referring to FIG. 7, a HOT wafer can be formed, for example, by depositing a dielectric layer 780 on a semiconductor substrate, and depositing a dielectric layer thereon. The semiconductor layer should be chosen such that it has a different crystal orientation than the semiconductor substrate. The trench is patterned to the semiconductor and down to the semiconductor substrate, thus forming a segment (e.g., first segment 751) having a first orientation of material. The same semiconductor material is then epitaxially grown in the trenches on the substrate such that it has the same orientation as the substrate, thus forming an additional segment of the second oriented semiconductor material (e.g., second segment 752). The first section 75A can, for example, comprise 11 〇 oriented single crystal germanium that is optimal for PFET performance, while the second section 752 can, for example, comprise 1 〇〇 oriented single crystal germanium that is optimal for NFET performance. These sections have different thicknesses due to the procedure used to form the first and second sections 751, 752. That is, the first thickness 761 of the first segment 751 of the semiconductor material having the first orientation will be less than the second thickness 762 of the second segment 752 of the semiconductor material having the second orientation. Since 37-200901323 7^52 will have different reflectivity and first reflectivity and the second s will reflect the absorption characteristics of the first and second sections 751, 752 4 (ie, first nature) (1001-1003). The integrated circuit design may include a plurality of circuits (such as static random access memory (SRAM) and logic circuits)' and each of the plurality of circuits may include, for example, a complementary metal oxide semiconductor (CM〇s) device, One type of device 601 (such as p-type field effect transistor (PFET)) and the second type = device 602 (such as n-type field effect transistor (NFET)) (904-906, see Figure 6) based on integrated circuit design and The configuration of the HOT wafer 'maps the first device 601 and the second device 602 to the wafer (丨008). In particular, the first and first devices 601, 602' are mapped such that they will be formed in the first and second segments 751, 752, respectively, to ensure optimal performance (1009-1010). For example, if the first Shishi section is η. The orientation and first device 601 is a pFET, and the first device 601 will be formed in the first segment 751 to ensure optimal performance (1 〇〇 9). Similarly, if the second turn section 752 is 100 oriented and the second device 6〇2 is an NFET, the second device 602 will be formed in the second section 2 to ensure optimal performance (1010). Then, based on the mapping of the first and second devices 601-602, the filling structure 65〇 (ie, the first and second filling structures) in different regions on the wafer and in different sub-regions in each region is predetermined. -38- 200901323 65 652) the distribution (ie, amount and position) such that the reflectivity across the wafer is nearly uniform (ie, the reflectivity and absorption characteristics are balanced, such that the reflectance and absorption characteristics are nearly equal) ) (1012). More specifically, each region 610, 620 of the wafer (preferably when each region = any particular sub-region (e.g., sub-region 01K612 of region 610, sub-regions 621-622 of region 620, etc.)) When the first thickness and the first reflective semiconductor material have nearly the same total ratio and density for the second thickness and the second reflective semiconductor material, a nearly uniform reflectance (1014) can be achieved. That is, the distribution of the filling structures 65ι and 652 is predetermined such that each of the regions 610, 620 (preferably each sub-region) has a semiconductor material having a thickness 761 in the first device 601 and the first filling structure 651. The sum of the surface areas has approximately the same total ratio between the sum of the surface areas of the semiconductor materials having the second thickness 762 of the second device 602 and the second filling structure 652. This same overall ratio can be predetermined&apos; and this total ratio can depend, for example, on the ratio of all of the first device 601 on the wafer to all of the second devices 602 on the wafer. Therefore, (J is for descriptive purposes only, if the wafer design includes one hundred first devices and three hundred second devices, the predetermined ratio of each region 610, 620 should be approximately 1:3. However, due to the first The ratio of the device to the second device and its location within any particular region of the wafer and/or any particular sub-region will vary depending on the design, and the first and second fill structures 651, 652 achieve uniform reflectance The required allocation (ie, quantity and position) will also vary. -39- 200901323 Once the mapping circuit and the position and amount of the filling structure 650 are predetermined, the first and second devices 601 are simultaneously formed on the wafer, 602 and first and second fill structures 65 652 (1018). For example, a PFET for forming a first segment having a first orientation (eg, 110) 在 on the same HOT wafer and having a second The prior art process of directing (e.g., 100) the second section of the NFET forms the first and second devices 601, 602. Additionally, as the first device 601 is formed, it may be formed and The device 601 is constructed in the same manner and formed on the wafer. The dummy first device (i.e., the inactive device) in the segment forms the first filling structure 651 to include the same orientation of the crucible (1020) having the same thickness. Similarly, as the second device 602 is formed, The second filling structure 652 can be formed, for example, by forming a dummy second device (ie, an inactive device) that is constructed in the same manner as the second device 602 and formed in the same second segment on the wafer. The same orientation of 矽 (1022) of the same thickness. (j Figure 11 shows a block diagram of an example design flow 00. The design flow 1100 can vary depending on the type of 1C being designed. For example, the design flow for building an application specific IC (ASIC) The 1100 differs from the design flow 1100 of the design standard component. The design structure 1120 is preferably an input to the design program 1110 from an IP provider, a core developer, or other design company, or may be generated by a design process operator or from another Source generation. Design structure 1120 includes the circuits of Figures 1-7 in the form of schematics or HDL, hardware description languages (eg, -40 - 200901323)

Verilog, VHDl, c Multiple machines can read in the media.纟 can be included in the - or Figure W circuit of the text meter structure coffee can be better than the figure U7, the shape table does not. Design light sequence 1110 compared to _, where the line connection L = or? For the line connection table, the control circuit, the circuit, the transistor, the other connection table in the logic circuit design's description of the accumulation: a machine readable medium = connection, and recorded in at least the road design Specification 22 is reversed, preface, which is based on electricity or multiple times. The road connection table 1180 can be recombined into a top program. The program 1110 includes the use of various inputs, such as input from the following items: a program block opener, which houses a set of common components, clothing, including specific manufacturing techniques ( Models, layouts, and symbolic representations such as 'different technology nodes: nm 5_, 90 nm, etc.; design specification data 1150; confirmation data 1160; design specifications Jim's and test poor materials file ιΐ85 (including test mode and other = test News). The design program 111G further includes, for example, a standard circuit 5 program, such as timing analysis, confirmation, design rule check, setting wiring work, and the like. Without departing from the scope and spirit of this (4) scale, the integrated circuit is designed to be a range of applications for the electronic design automation tools and design programs lnG. The design structure of the present invention is not limited to any mosquito design flow. 41 200901323 § § Ten Procedures 111 〇 Better County The example, together with any additional integrators, is translated into the second series of Qiu (10). The layout data of the nrtn integrated circuit is "^ 0 for the father to change, or for the =====(1), the stored (four) data format to reside in the second = combined =

Ο ==r test _, design = shape, in-process, - ί majority, line, metal level, via hole, shape invented ΓΓΓ line information, and semiconductor manufacturers for the production of two 椹 椹; m: implementation Any other information required for the example. Arranging 1&quot;19〇:, then proceeding to stage 1195, where (for example) designing the knot ♦ • proceeding to tape-out, publishing for manufacturing, sending to the mask for scrapping to another design factory, Return to the customer, etc. The above is a semiconductor structure embodiment and the formation of the junction = correlation method using a dummy fill structure with a variable configuration to provide a uniform reflectance of the entire wafer ± to ensure that the entire wafer is in a deceleration annealing period. Uniform temperature change. A specific embodiment achieves a uniform reflectivity by &quot;I: distributing the filling structure of the semiconductor material over the entire wafer, so that in each region and in the most sub-region of the wafer, The same total ratio and density are formed between different semiconductor materials. Another embodiment achieves a uniform reflectance by disposing a filling structure comprising a plurality of mixed filler junctions of different semiconductor materials containing varying proportions of -43-200901323 over the entire wafer, resulting in Within a region and preferably within each sub-region of the wafer, nearly identical total ratios and twists are achieved between different semiconductor materials. Yet another embodiment achieves uniform reflectivity by distributing a fill structure comprising semiconductor materials of different thicknesses throughout the wafer such that in each region, and preferably within each sub-region of the wafer, Nearly the same total ratio and density are achieved between semiconductor materials having different thicknesses.

It should be noted that the inventors of the above-described embodiments have invented the following additional inventions relating to the reflectance and absorption characteristics of wafers during rapid annealing, each of which is hereby incorporated by reference in its entirety herein in its entirety herein in U.S. Patent Application Serial No.: 11/678,783, entitled "Localized Temperature Control During Rapid Thermal Anneal", Agent File Number: BUR 920060028US1; (2) Commonly Applied US Patent Application Case No.: 11/678756, entitled "Semiconductor Wafer Structure With Balanced Reflectance And Absorption Characteristics For Rapid Thermal Anneal Uniformity", Agent Building Case No.: BUR 920060024US1; and (3) U.S. Patent Application Serial No. 11/678,799, entitled "Localized Temperature Control During Rapid Thermal Anneal", Agent Building Number: BUR - 43 · 200901323 92006 0130 US1 ° The description of the specific embodiments above fully discloses the general characteristics of the present invention, and thus, by applying the present knowledge, such specific embodiments can be modified and/or adapted to various applications without departing from the general concept. Therefore, such adaptations and modifications should be understood within the meaning and scope of the equivalents of the specific embodiments disclosed. It should be understood that the phrase or phrase used herein is for the purpose of description and not limitation. Therefore, it is to be understood by those skilled in the art that the specific embodiments of the invention may be practiced. BRIEF DESCRIPTION OF THE DRAWINGS The specific embodiments of the present invention will be more fully understood from the following detailed description of the drawings, wherein: FIG. 1 is not intended to describe an exemplary wafer, and FIG. FIG. 4 is a schematic diagram for describing a specific embodiment of the structure of the present invention; FIG. 5 is a schematic diagram for describing another embodiment of the present invention. FIG. Figure 6 is a schematic diagram showing still another structural embodiment of the present invention; Figure 7 is a schematic diagram depicting an exemplary hybrid orientation (HOT) wafer; -44- 200901323 Figure 8 is a flow chart describing a specific embodiment of the method of the present invention Figure 9 is a flow chart depicting another embodiment of the method of the present invention; Figure 10 is a flow chart depicting another embodiment of the method of the present invention; and Figure 11 is used in semiconductor design, fabrication, and/or testing Flow chart of the design program. .. [Major component symbol description] 100 wafer 110 region 150 scribe line 201 first device 202 second device 210 region 211 '-212 sub-region 300 dummy fill structure 301 first device 302 second device 401 first device 402 Second device 410, 420 area 411, 412, 421, 422 sub-area 450 filling structure -45 - 200901323

451 451 first filling structure 452 second filling structure 501 first device 502 second device 510, 520 region 511, 512, 513, 521, 522, 523 sub-region 550 ' 551 ' 552 ' 553 hybrid filling structure 556 first dummy Device 557 second dummy device 601 first device 602 second device 610, 620 region 611, 612, 621, 622 sub-region 650, 651, 652 filling structure 700 semiconductor substrate 751 first segment 752 second segment 761 first Thickness 762 Second Thickness 780 Dielectric Layer 790 Isolation Structure 1100 Design Flow 1110 Design Procedure 1120 Design Structure -46- 200901323 1130 Library Element 1140 Design Specification 1150 Characteristic Data 1160 Confirming Poor Material 1170 Design Rule 1180 Line Connection Table 1185 Test Dividend Case 1190 Design Structure 1195 Stage

C -47-

Claims (1)

200901323 Patent Application Range: 1. A semiconductor structure comprising: 圆 and a plurality of first devices on the wafer, wherein the first device comprises a first material having a first reflectivity; The second device is mounted on the wafer, wherein the second wafer comprises a second material having a second reflectivity, and wherein the first reflectivity is different from the second reflectivity; a plurality of first filling structures and a second filling structure on the crystal, wherein the first filling structure comprises the first material, and the first filling structure comprises the two materials; wherein the first filling structure and the second The distribution of the filling structure over the wafer relative to the first device and the second device causes the reflectivity across the crystal gj to be nearly uniform. 2. = item] the semiconductor structure described, wherein =: two of the first-filled structure and the second fill for the ~-device and the second device in the region of the distribution system cause each of the regions - The area has a nearly opposite ratio of the ratio of the material to the second material. 3. The semiconductor region according to claim 2 has a different ratio of the first device to the middle of the device, and thus has a different first-filled junction ^ = -48- 200901323 charge The semiconductor structure of item 3, wherein the at least region=the different sub-regions of the region have different first-device pairs and thus have different first-filled structures and the second-filled structure distribution. 5. The semiconductor structure of the request item 1 contains a stone fault, and wherein the second material comprises a stone semiconductor structure, which comprises a wafer containing a device, on the wafer, Wherein the first device 3 has one of the first materials of the discriminating property; a plurality of the second materials are on the wafer, and the second material of the second reflective material is different from the first material. a second plurality of filling structures, comprising at least one mixed filling junction and the YiH. The hybrid filling structure comprises the first material, wherein the filling structure is on the entire wafer relative to the first distribution system The semiconductor structure of the above-mentioned: -49-200901323, wherein the wafer comprises a plurality of rafts and the filling structure of the mosquito relative to the first 裒 and the first device is occluded in each of the regions in the region , the ratio of the material to the second material in each region of the region. The structure of the wafer, wherein the different regions of the wafer have different t-rates of the second device to the second device, And thus have different assignments of the Wei structure. 9. The semiconductor structure of claim 8, wherein the different sub-regions in one of the regions have different ratios of: = clothing, and thus have different filling structures. 10 as recited in claim 6. Semiconductor structure, structure package m material: fixed ratio. χ乐一材# one pre-n· semiconductor as claimed in claim 1G; r contains multiple mixed filling structures = predetermined ratio of material 枓 to the second material亥"Hai 12" The semiconducting M, as described in claim 11, wherein the first material of the hybrid filling -50-200901323 structure differs in the predetermined ratio of the second material. 13. The semiconductor structure of claim 6, wherein the first material comprises germanium, and wherein the second material comprises germanium. 14. A semiconductor structure, comprising: a wafer, a plurality of first devices on the wafer, wherein the first device comprises a semiconductor material having a first thickness; and a plurality of second devices are on the wafer The second device includes a second material having a second thickness, and wherein the first thickness is different from the second thickness; and the plurality of first filling structures and the second filling structure are on the wafer, wherein The first filling structure includes the semiconductor material having the first thickness, and the second filling structure comprises the semiconductor material having the second thickness; wherein the first filling structure and the second filling structure are on the entire wafer The distribution relative to the first device and the second device causes the reflectivity across the wafer to be nearly uniform. 15. The semiconductor structure of claim 14, wherein the wafer comprises a hybrid directional wafer comprising: a first segment of the semiconductor material having the first thickness and a first orientation, and adjacent The first -51 - 200901323 section and the second section having the second thickness and the second orientation of the material, and wherein the first device and the first filling structure are in the first section, And a structure in the first &amp; second device and the second padding 16.:=: the semiconductor structure, wherein the semiconductor material has a plurality of regions, and: JV: : J椹 ten of the wafer comprises a structure The second true charging structure and the second filling junction of the parent region of the μ region are opposite to the first device, so that each region of the region has a second, and the second has a thickness of 5 The ratio of the semiconductor material to the semiconductor material of the younger generation. The semiconductor structure of claim π, the first device of the first device, the semiconductor structure described in claim 18, wherein the region is different from the second The regions have different ratios of the first mounts and thus have different assignments of the first fill structure and the first fill structure. The semiconductor structure of claim 14, wherein the first orientation comprises a 110 orientation and the first device comprises a p-type field effect transistor, and wherein the second orientation comprises a 100 orientation and The second device comprises an n-type field effect transistor. 21. A method of forming a semiconductor structure, comprising: forming a first device comprising a first material having a first reflectivity and a second material comprising a second reflective material on a wafer a second device; and forming, on the wafer, a plurality of filling structures including the first material and the second material, the forming being included on the entire wafer relative to the first device and the second device The fill structure results in a nearly uniform reflectivity across the wafer. 22. The method of claim 21, further comprising mapping each of the first device and the second device based on a design prior to the forming of the first device, the second device, and the fill structure. To the wafer. 23. The method of claim 22, wherein the forming of the plurality of fill structures comprises: forming a first fill structure comprising the first material and a second fill structure comprising the second material. The method of claim 23, further comprising determining the amount and location of the first filling structure and the second filling structure based on the mapping such that each region of the wafer has approximately the same The ratio of the first material to the second material. 25. The method of claim 24, wherein the forming of the first filling structure comprises forming an inactive first device during the forming of the first device, and wherein the forming of the second filling structure is included During this formation of the second device, an inactive second device is formed. 26. The method of claim 23, wherein the first material comprises epitaxially grown germanium, and wherein the second material comprises single crystal germanium. 27. The method of claim 21, wherein the forming of the plurality of filling structures comprises forming at least one hybrid filling structure comprising the first material and the second material. 28. The method of claim 27, further comprising determining a location and a first material to second material ratio for the at least one hybrid fill structure based on the mapping. 29. The method of claim 27, wherein the forming of the plurality of fill structures comprises forming a plurality of hybrid fill structures having different predetermined first material pairs -54 - 200901323 second material ratio, and wherein the plurality The different predetermined first material to second material ratio of the hybrid fill structures ensures that each region of the wafer has approximately the same ratio of the first material to the second material. 30. A method of forming a semiconductor structure, the method comprising: forming a first device comprising a semiconductor material having a first thickness and a second device comprising the semiconductor material having a second thickness on a wafer; And forming a first filling structure comprising the semiconductor material having the first thickness and a second filling structure comprising the semiconductor material having the second thickness on the wafer, wherein the first filling structure and the second The forming of the fill structure includes dispensing the first fill structure and the second fill structure over the entire wafer relative to the first device and the second device such that the reflectivity across the wafer is nearly uniform. The method of claim 30, wherein the providing of the wafer comprises providing a hybrid directional wafer comprising a first germanium segment having the first thickness and a first orientation And a second meandering section having the second thickness and a second orientation. 32. The method of claim 31, wherein the forming of the first device and the forming of the first filling structure comprise simultaneously forming the first device and the first portion in the first region -55-200901323 A fill structure, and the formation of the second device and the formation of the second fill structure comprise simultaneously forming the second device and the second fill structure in the second turn region. The method of claim 30, wherein the forming of the first filling structure further comprises forming an inactive first device, and wherein the forming of the second filling structure comprises forming an inactive second device. 34. The method of claim 30, before the forming of the device and the filling structure, further comprising: mapping each of the first device and the second device to the wafer based on a design; Determining, according to the mapping, the amount and position of the first filling structure and the second filling structure, such that each region of the wafer has nearly the same thickness of the semiconductor material having the first thickness The ratio of the semiconductor material. 35. A design structure embodied in a machine readable medium for use in a design program. The design structure comprises the semiconductor structure of any one of claims 1 to 2. 3 6 - The design structure as claimed in claim 3' wherein the design structure includes a line connection table describing one of the circuits. The design of claim 35, wherein the design structure resides in a storage medium as a data format for the exchange of layout data for the integrated circuit. 3 8. The design structure of claim 3, wherein the design structure comprises at least one of a test poor condition, a characteristic feed, a confirmation tribute, and a design specification. 39. A design structure embodied in a machine readable medium for use in a design program, the design structure comprising the semiconductor structure of any one of claims 6-10. 40. The design structure of claim 39 wherein the design structure includes a line connection table describing a circuit. 41. The design structure of claim 39 wherein the design structure resides in a storage medium as a data format for the exchange of layout data for the integrated circuit. 42. The design structure 5 of claim 39, wherein the design structure comprises at least one of a test data file, a feature data, a confirmation data, and a design specification. - 57- 200901323 43. A design structure embodied in a machine readable medium for use in a design program, the design structure comprising the semiconductor structure of any one of claims 14-17. 44. The design structure of claim 43 wherein the design structure includes a line connection table describing a circuit. 45. The design structure of claim 43, wherein the design structure resides in a storage medium as a data format for the exchange of layout data for the integrated circuit. 46. The design structure of claim 43 wherein the design structure comprises at least one of a test data file, a feature data, a confirmation material, and a design specification. -58-