JP2008209696A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time required for stabilization of a common potential in a semiconductor integrated circuit that drives a LCD panel by inverting the common potential. <P>SOLUTION: The semiconductor integrated circuit includes: an image signal generating circuit generating an image signal; a power supply circuit generating a first power supply potential higher than the image signal, a second power supply potential lower than the image signal, a third power supply potential lower than the first power supply potential and a fourth power supply potential higher than the second power supply potential; and a common potential generating circuit that supplies the third power supply potential to an output node while a control signal holds a first level and supplies the fourth power supply potential to the output node while the control signal holds a second level, as well as supplies the first power supply potential to the output node while the potential of the output node rises to the third power supply potential so as to accelerate the rising of the common potential, and supplies the second power supply potential to the output node while the potential of the output node falls to the fourth power supply potential so as to accelerate the falling of the common potential. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to a semiconductor integrated circuit for driving an LCD (Liquid Crystal Display) panel, and in particular, a semiconductor incorporating a common potential generation circuit for generating a common potential supplied to a common electrode of the LCD panel. The present invention relates to an integrated circuit.

  In an active matrix LCD panel, a first transparent substrate on which a plurality of individual electrodes and a plurality of thin film transistors (TFTs) connected thereto are formed, and a second electrode on which one common electrode is formed. The transparent substrate is disposed to face the transparent substrate, and liquid crystal is sealed between the first transparent substrate and the second transparent substrate.

  By activating the scanning signal supplied to the gate of the TFT connected to each individual electrode, the TFT is turned on, and the image signal supplied to the source of the TFT is supplied to the individual electrode. On the other hand, a common potential is applied to a common electrode facing a plurality of individual electrodes. The brightness of the screen in the LCD panel is determined by the potential difference between the potential of the image signal supplied to the individual electrode and the common potential applied to the common electrode.

  Further, since the characteristics deteriorate when a DC voltage is continuously applied to the LCD panel, the voltage applied to the LCD panel is inverted at a predetermined cycle. In general, a frame inversion method in which an applied voltage is inverted every frame (or one field), a line inversion method in which an applied voltage is inverted every line, and an applied voltage is inverted every dot. One of the line inversion methods is used. Further, in order to prevent the increase in the amplitude of the image signal due to the inversion of the applied voltage, in the frame inversion method or the line inversion method, the common inversion drive that inverts the common potential applied to the common electrode in synchronization with the inversion timing of the image signal. Is used.

  In the common inversion driving of the line inversion method, since the cycle in which the common potential is inverted is short, it is necessary to shorten the time required for stabilizing the common potential by making the common potential rise and fall sharply. In particular, one set of DAC (Digital to Analog Converter) and operational amplifier is shared for three RGB dots that are continuous on one line, and three dots of RGB image signals are time-divided in one horizontal synchronization period. In the driving method (also referred to as “de-multi-driving method”), the time required for stabilizing the common potential needs to be shortened to about ３ that of the normal driving method.

  Further, the stabilization time of the common potential is affected by the capacitive load of the LCD panel. That is, the larger the capacitive load of the LCD panel, the longer it takes to stabilize the common potential. With the recent increase in LCD panel size and resolution, the capacitive load on the LCD panel is increasing. In a semiconductor integrated circuit (liquid crystal driver IC) for driving the LCD panel, the common potential stabilization time is increased. Is required to be shortened.

  As a related technique, Japanese Patent Application Laid-Open No. 2004-151620 discloses that the common electrode of the liquid crystal panel that is switched by line inversion driving and frame inversion driving performs polarity inversion for each polarity inversion of line inversion driving and frame inversion driving. A common electrode driving circuit capable of supplying a common voltage and preventing flicker is disclosed.

This common electrode driving circuit has a common voltage first regulating means for regulating the cycle and amplitude of the common voltage, an output from the common voltage first regulating means at one end side, and a common voltage from the other end side. The coupling capacitor, the common voltage second regulating means for regulating the center voltage of the common voltage, and the output from the common voltage second regulating means are input to the input terminal, and during line inversion driving, a signal is output from the first output terminal. In the case of frame inversion driving, a selector that selectively outputs a signal from the first output end and from the second output end after a predetermined period, and an output signal from the first output end of the selector are input to one end side. The first resistor that is output from the other end side to the other end side of the coupling capacitor and regulates the slope of the rising and falling waveforms of the common voltage, and the second output end of the selector Force signal is input to one end, is output from the other end to the other end of the coupling capacitor, and a second resistor and the resistance value than the first resistance is large. However, Patent Document 1 does not particularly disclose shortening the stabilization time of the common potential.
JP 2004-258274 A (pages 1 and 2, FIG. 1)

  Accordingly, in view of the above points, the present invention reduces the time required for stabilizing the common potential by making the common potential rise and fall sharply in a semiconductor integrated circuit for common inversion driving of an LCD panel. With the goal.

  In order to solve the above problem, a semiconductor integrated circuit according to one aspect of the present invention includes a liquid crystal display having a plurality of individual electrodes to which drains of a plurality of thin film transistors are respectively connected, and a common electrode facing the plurality of individual electrodes. A semiconductor integrated circuit for driving a panel, and an image signal generation circuit for generating a plurality of analog image signals respectively supplied to sources of a plurality of thin film transistors based on a series of image data, and an external supply Based on the plurality of power supply potentials, a first power supply potential higher than the analog image signal and a second power supply potential lower than the analog image signal are generated, and further, the first power supply potential higher than the analog image signal is generated. A third power supply potential lower than the second power supply potential and a fourth power supply potential lower than the analog image signal and higher than the second power supply potential. And a common potential generation circuit that generates a common potential supplied to the common electrode at the output node based on the control signal, and the third power supply potential is applied to the output node while the control signal has the first level. And a first driver circuit that supplies a fourth power supply potential to the output node while the control signal has the second level, and a first power supply while the potential of the output node rises to the third power supply potential. The potential is supplied to the output node to accelerate the rise of the common potential, and the second power supply potential is supplied to the output node while the output node potential falls to the fourth power supply potential to accelerate the fall of the common potential. And a common potential generation circuit including a second driving circuit.

  The semiconductor integrated circuit may further include a scanning signal generation circuit that sequentially activates a plurality of scanning signals respectively supplied to the gates of the thin film transistors in a plurality of rows. In the above, the first drive circuit is connected between the P channel MOS transistor having the source / drain connected between the third power supply potential and the output node, and between the fourth power supply potential and the output node. The gate potential of the P-channel MOS transistor is generated so that the N-channel MOS transistor having the source / drain and the P-channel MOS transistor are turned on while the control signal has the first level. And a gate potential generation circuit for generating a gate potential of the N channel MOS transistor so as to turn on the N channel MOS transistor while having the level of.

  Here, the second drive circuit includes a second P-channel MOS transistor having a source / drain connected between the first power supply potential and the output node, and between the second power supply potential and the output node. A second N-channel MOS transistor having a source / drain connected to the second P-channel when the potential of the output node is lower than the third power supply potential while the control signal has the first level. While the second gate potential generation circuit generates the gate potential of the second P-channel MOS transistor so as to turn on the MOS transistor and the control signal has the second level, the potential of the output node is the fourth level. The third gate generating the gate potential of the second N-channel MOS transistor so as to turn on the second N-channel MOS transistor when the power supply potential is higher than the power supply potential of the second N-channel MOS transistor. It may include a preparative potential generating circuit.

  Alternatively, the second driving circuit includes a second P-channel MOS transistor having a source / drain connected between the first power supply potential and the output node, and the second power supply potential between the second power supply potential and the output node. The second P-channel MOS transistor having the connected source / drain and the second P-channel MOS transistor are turned on for a predetermined period while the control signal has the first level. The gate potential of the second N-channel MOS transistor is generated so that the second N-channel MOS transistor is turned on for a predetermined period while the gate potential of the channel MOS transistor is generated and the control signal has the second level. A second gate potential generation circuit to be generated may be included.

  According to the present invention, while the potential of the output node rises to the third power supply potential, the first power supply potential higher than the third power supply potential is supplied to the output node to accelerate the rise of the common potential. Since the second power supply potential lower than the fourth power supply potential is supplied to the output node while the potential of the common potential falls to the fourth power supply potential, the falling of the common potential is accelerated. In addition, the time required for stabilizing the common potential can be shortened by making the falling edge steep. As a result, it is possible to provide a semiconductor integrated circuit suitable for driving an LCD panel having a large capacitive load and demulti-drive.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a diagram showing a partial configuration of a semiconductor integrated circuit (liquid crystal driver IC) and an LCD panel according to the first embodiment of the present invention. In the LCD panel 100, for example, the same number of TFTs 111, 112, 113, ..., 121, 122, 123, ... are arranged in a two-dimensional matrix corresponding to 720 x 132 dots.

  The drains of these TFTs are respectively connected to a plurality of individual electrodes of the LCD panel 100, and the sources of the TFTs in each column are connected to the source lines S1, S2, S3,. The gates of the TFTs are connected to the gate lines G1, G2,.

  When the high level scanning signal is supplied to the gate and turned on, the TFT outputs the image signal supplied to the source from the drain and supplies the image signal to the corresponding individual electrode of the LCD panel 100. In the LCD panel 100, a common electrode is provided to face a plurality of individual electrodes, and capacitances formed between the plurality of individual electrodes and the common electrode are capacitors C11, C12, C13,. It is represented.

  The liquid crystal driver IC includes a RAM 10 that temporarily stores red (R), green (G), and blue (B) image data input from an external MPU (microprocessor) or the like, and each line that is sequentially read from the RAM 10. .., Which respectively convert the image data into a plurality of analog image signals, and a plurality of image signals output from the DACs 21, 22, 23,... Are supplied to the source lines S 1, S 2, S 3,..., And a control circuit 40 that controls the reading operation of image data from the RAM 10 by supplying addresses to the RAM 10. Have.

The liquid crystal driver IC, a common potential generation circuit 50 for generating a common potential _{V COM} applied to the common electrode of the LCD panel 100, the gate lines G1, G2, a plurality of scan signals respectively supplied to ... Based on a scanning signal generation circuit 60 that is sequentially activated, and a power supply potential V _DD and a power supply potential V _SS supplied from the outside via a power supply terminal (in this embodiment, a ground potential) It further includes power supply circuits 71 and 72 that generate various power supply potentials by applying pressure.

The power supply circuit 71 generates a plurality of power supply potentials necessary for generating an image signal, and the power supply circuit 72 generates a plurality of power supply potentials required for generating a common potential and a scanning signal. In order to generate the common potential, four types of power supply potentials V _OUT , V _COMH , V _COML , and V _OUTM are supplied to the common potential generation circuit 50. Further, in order to generate the scanning signal, two kinds of power supply potentials V _HH and V _LL are supplied to the scanning signal generation circuit 60.

  The image data read from the RAM 10 is converted into a plurality of analog image signals by the DACs 21, 22, 23,. Here, the DACs 21, 22, 23,... Are resistance network type DACs using a plurality of resistors, and by setting the values of these resistors to values having the characteristics of γ correction, the DACs 21, 22, 23,. The processed image data can be converted into an image signal subjected to γ correction.

  The analog image signals output from the DACs 21, 22, 23,... Are input to the operational amplifiers 31, 32, 33,. Image signals output from the operational amplifiers 31, 32, 33,... Are supplied to the source lines S1, S2, S3,.

  The image signal supplied to the source line S1 is applied to the sources of the TFTs 111, 121,... In the first column, and the image signal supplied to the source line S2 is applied to the TFTs 112, 122,. The image signal applied to the source and supplied to the source line S3 is applied to the sources of the TFTs 113, 123,.

The common potential generation circuit 50 generates a common potential V _COM that is inverted every one line or one frame (or one field) in accordance with a control signal supplied from the control circuit 40 and supplies the common potential V _COM to the common electrode of the LCD panel 100. .

  The scanning signal generation circuit 60 generates a plurality of scanning signals respectively supplied to the gate lines G1, G2,... According to the control signal supplied from the control circuit 40, and the LCD panel 100 to which the image signal is supplied. A plurality of scanning signals are sequentially activated to a high level corresponding to the line.

  As a result, among the plurality of TFTs connected to each source line, the TFT whose gate line is at a high level is turned on, and an image signal is applied to the individual electrode connected to the drain of the TFT. Supplied. In this way, an image is displayed on the LCD panel 100.

  Here, the DACs 21, 22, 23,... And the operational amplifiers 31, 32, 33,... Receive a plurality of analog image signals respectively supplied to the sources of the plurality of TFTs based on a series of image data. This corresponds to an image signal generation circuit to be generated. In the demulti-drive method, in order to reduce the number of channels in the image signal generation circuit, as shown in FIG. 2, by sharing one set of DAC 20 and operational amplifier 30 for three consecutive RGB dots on one line, In one horizontal synchronization period (1H), RGB image signals are supplied to 3 dots by time division.

  As shown in FIG. 2, the demulti-drive type liquid crystal driver IC includes switch circuits 81 to 83 that sequentially select image data of a plurality of channels read from the RAM 10 and output them to the DAC 20 in a time division manner, and a plurality of output terminals. Switch circuits 91 to 93 for distributing analog image signals buffered by the operational amplifier 30 to a plurality of output terminals in a time-sharing manner.

  Under the control of the control circuit 40, the switch circuits 81 to 83 sequentially select the image data of the three RGB channels read from the RAM 10 in one horizontal synchronization period (1H). The image data selected by the switch circuits 81 to 83 is converted into an analog image signal by the DAC 20, and the analog image signal output from the DAC 20 is input to the operational amplifier 30. The analog image signals output from the operational amplifier 30 are sequentially output to the source lines S1 to S3 of the liquid crystal display device via the plurality of output terminals by the switch circuits 91 to 93. The switching timing of the switch circuits 91 to 93 is controlled by the control circuit 40 so as to be synchronized with the switching timing of the switches 81 to 83.

FIG. 3 is a diagram showing a detailed configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 3, a part of the power supply circuit 72 and the common potential generation circuit 50 are shown. The power supply circuit 72 includes a power supply potential generation circuit 721 and a plurality of amplifiers 722 and 723. The power supply potential generation circuit 721 has a power supply potential _VOUT higher than the analog image signal generated by the image signal generation circuit and a power supply lower than the analog image signal based on the power supply potentials V _DD and V _SS supplied from the outside. A plurality of power supply potentials including the potential V _OUTM are generated.

Based on these supply potential, generating amplifier 722 generates a power supply potential _{V COMH} defining a high-level common potential _{V COM,} amplifier 723, a power supply potential _{V COML} defining a low-level common potential _{V COM} To do. The power supply potential V _COMH is higher than the analog image signal and lower than the power supply potential _VOUT . Further, the power supply potential V _COML is lower than the analog image signal and higher than the power supply potential V _OUTM .

The common potential generation circuit 50 includes a first drive circuit 51 and a second drive circuit 52, and is supplied to the common electrode of the LCD panel based on the control signal POL supplied from the control circuit 40 shown in FIG. generating an output node N1 of the common potential _{V COM} to be. The resistors R0 to R4 are equivalently representing resistance components due to wirings, the capacitor C0 is equivalently representing the capacitance component of the LCD panel, and the capacitors C1 to C4 are for smoothing. Capacitor. Capacity of LCD panel C0, since a load of the common potential generation circuit 50 becomes a factor dampening the rise and fall of the common potential V _COM.

The first drive circuit 51 is connected between a power supply potential V _COML and an output node N1 and a P channel MOS transistor QP1 having a source / drain connected between the power supply potential V _COMH and the output node N1. An N channel MOS transistor QN1 having a source and a drain and a gate potential generation circuit 511 for generating gate potentials of the transistors QP1 and QN1 based on a control signal POL are included.

The gate potential generation circuit 511 generates the gate potential of the transistor QP1 so that the transistor QP1 is turned on while the control signal POL has a first level (for example, low level), and the control signal POL is set to the second level. The gate potential of the transistor QN1 is generated so that the transistor QN1 is turned on while the level is (eg, high level). Thus, the first drive circuit 51 supplies the power supply potential V _COMH to the output node N1 while the control signal POL has the first level, and the power supply potential V _COMH while the control signal POL has the second level. The potential V _COML is supplied to the output node N1.

Second driving circuit 52 includes a P-channel MOS transistor QP2 having connected source-drain between power supply potential _{V OUT} and the output node N1, which is connected between the power supply potential _{V OUTM} output node N1 It includes an N-channel MOS transistor QN2 having a source / drain, a comparison circuit 521 that generates the gate potential of the transistor QP2, and a comparison circuit 522 that generates the gate potential of the transistor QN1.

While the control signal POL has the first level, the comparison circuit 521 compares the potential of the output node N1 with the power supply potential V _COMH, and when the potential of the output node N1 is lower than the power supply potential V _COMH , A low level gate potential is generated to turn on the transistor QP2. On the other hand, while the control signal POL has the second level, the comparison circuit 521 generates a high-level gate potential to turn off the transistor QP2.

While the control signal POL has the second level, the comparison circuit 522 compares the potential of the output node N1 with the power supply potential V _COML and when the potential of the output node N1 is higher than the power supply potential V _COML , A high level gate potential is generated to turn on the transistor QN2. On the other hand, while the control signal POL has the first level, the comparison circuit 522 generates a low-level gate potential to turn off the transistor QN2.

Accordingly, the second drive circuit 52 supplies the power supply potential _VOUT higher than the power supply potential V _COMH to the output node N1 while the potential of the output node N1 rises to the power supply potential V _COMH , so that the common potential V _COM is set. accelerating the rise, the potential of the output node N1 between falls to the power supply potential _{V COML,} to accelerate the fall of the common potential _{V COM} supplies the low power supply potential _{V OUTM} than the power supply potential _{V COML} to the output node N1 be able to.

  FIG. 4 is a diagram illustrating how the rising and falling of the common potential are improved by the second driving circuit. In FIG. 4, the solid line represents the common potential, the broken line represents the source potential (analog image signal) of the TFT in the demulti drive system, and the alternate long and short dash line represents the gate potential (scanning signal) of the TFT (for two lines). 4A shows the waveform when only the first drive circuit is used, and FIG. 4B shows the waveform when the second drive circuit is added.

  As shown in FIG. 4A, when only the first drive circuit is used, the rise and fall of the common potential are dull, and in particular, the rise and fall of the red (R) image signal in the demulti drive method. Since it lags behind the falling edge, it adversely affects charging of charges between the individual electrode and the common electrode. On the other hand, as shown in FIG. 4B, when the second drive circuit is added, the common potential rises and falls sharply and charges are charged between the individual electrode and the common electrode. It is possible to reduce the adverse effects when doing so.

  FIG. 5 is a diagram showing a detailed configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 5, a part of the power supply circuit 72 and the common potential generation circuit 50 are shown. The power supply circuit 72 is the same as that shown in FIG.

The common potential generation circuit 50 includes a first drive circuit 51 and a second drive circuit 52, and is supplied to the common electrode of the LCD panel based on the control signal POL supplied from the control circuit 40 shown in FIG. generating an output node N1 of the common potential _{V COM} to be.

The first drive circuit 51 is connected between a power supply potential V _COML and an output node N1 and a P channel MOS transistor QP1 having a source / drain connected between the power supply potential V _COMH and the output node N1. An N channel MOS transistor QN1 having a source and a drain and a gate potential generation circuit 511 for generating gate potentials of the transistors QP1 and QN1 based on a control signal POL are included.

The gate potential generation circuit 511 generates the gate potential of the transistor QP1 so that the transistor QP1 is turned on while the control signal POL has a first level (for example, low level), and the control signal POL is set to the second level. The gate potential of the transistor QN1 is generated so that the transistor QN1 is turned on while the level is (eg, high level). Thus, the first drive circuit 51 supplies the power supply potential V _COMH to the output node N1 while the control signal POL has the first level, and the power supply potential V _COMH while the control signal POL has the second level. The potential V _COML is supplied to the output node N1.

Second driving circuit 52 includes a P-channel MOS transistor QP2 having connected source-drain between power supply potential _{V OUT} and the output node N1, which is connected between the power supply potential _{V OUTM} output node N1 An N channel MOS transistor QN2 having a source and a drain and a gate potential generation circuit 523 for generating gate potentials of the transistors QP2 and QN2 based on a control signal POL are included.

Gate potential generating circuit 523, the control signal POL is between having a first level, the transistor QP2 generates gate potential of the transistor QP2 to the ON state only a predetermined time period T _A, the control signal POL is the second level while having a, generates a gate potential of the transistor QN2 to the transistor QN2 only turned on a predetermined period T _B. These periods T _A and T _B can be set according to the output levels and output impedances of the drive circuits 51 and 52 and the capacitance C0 of the LCD panel.

For example, based on a time constant T = Z · C0 determined by the combined output impedance Z of the drive circuits 51 and 52 and the capacitance C0 of the LCD panel, the periods T _A and T _B are set to about T _A = T _B = T to 4T. You may set so that it becomes. Here, when the combined output impedance Z of the drive circuits 51 and 52 is 2Ω and the capacitance C0 of the LCD panel is 250 pF, the time constant T is 500 psec, and T _A = T _B = 500 psec to 2 μsec. can do.

Accordingly, the second drive circuit 52 supplies the power supply potential _VOUT higher than the power supply potential V _COMH to the output node N1 while the potential of the output node N1 rises to the power supply potential V _COMH , so that the common potential V _COM is set. accelerating the rise, the potential of the output node N1 between falls to the power supply potential _{V COML,} to accelerate the fall of the common potential _{V COM} supplies the low power supply potential _{V OUTM} than the power supply potential _{V COML} to the output node N1 be able to.

1 is a diagram showing a semiconductor integrated circuit and an LCD panel according to one embodiment of the present invention. The figure which shows the semiconductor integrated circuit and LCD panel of a demulti drive system. 1 is a diagram showing a detailed configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. The figure which shows a mode that the rise of a common electric potential is improved by the 2nd drive circuit. The figure which shows the detailed structure of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  10 RAM, 20-23 DAC, 30-33 operational amplifier, 40 control circuit, 50 common potential generation circuit, 60 scanning signal generation circuit, 71, 72 power supply circuit, 81-93 switch circuit, 511, 523 gate potential generation circuit, 521 522 comparison circuit, 721 power supply voltage generation circuit, 722, 723 amplifier, 100 LCD panel, 111-123 TFT, S1-S3 source line, G1, G2 gate line, R0-R4 resistance, C0-C4 capacitance, QP1, QP2 P-channel transistor, QN1, QN2 N-channel transistor

Claims (5)

A semiconductor integrated circuit for driving a liquid crystal display panel having a plurality of individual electrodes to which drains of a plurality of thin film transistors are respectively connected, and a common electrode facing the plurality of individual electrodes,
An image signal generation circuit that generates a plurality of analog image signals respectively supplied to the sources of the plurality of thin film transistors based on a series of image data;
Based on a plurality of power supply potentials supplied from the outside, a first power supply potential higher than the analog image signal and a second power supply potential lower than the analog image signal are generated, and the analog image signal A power supply circuit that generates a third power supply potential that is higher than the first power supply potential and lower than the first power supply potential, and a fourth power supply potential that is lower than the analog image signal and higher than the second power supply potential;
A common potential generation circuit for generating a common potential supplied to the common electrode at an output node based on a control signal, wherein a third power supply potential is applied to the output node while the control signal has a first level. And a first driving circuit for supplying a fourth power supply potential to the output node while the control signal has the second level, and a first drive while the output node rises to the third power supply potential. Is supplied to the output node to accelerate the rise of the common potential, and the second power supply potential is supplied to the output node while the potential of the output node falls to the fourth power supply potential. The common potential generation circuit including a second drive circuit for accelerating the fall of
A semiconductor integrated circuit comprising:   2. The semiconductor integrated circuit according to claim 1, further comprising a scanning signal generation circuit for sequentially activating a plurality of scanning signals respectively supplied to the gates of the thin film transistors in a plurality of rows. The first driving circuit comprises:
A P-channel MOS transistor having a source / drain connected between a third power supply potential and the output node;
An N-channel MOS transistor having a source / drain connected between a fourth power supply potential and the output node;
A gate potential of the P-channel MOS transistor is generated so as to turn on the P-channel MOS transistor while the control signal has the first level, and the N-channel MOS while the control signal has the second level. A gate potential generating circuit for generating a gate potential of the N-channel MOS transistor so as to turn on the transistor;
The semiconductor integrated circuit according to claim 1, comprising: The second drive circuit comprises:
A second P-channel MOS transistor having a source / drain connected between a first power supply potential and the output node;
A second N-channel MOS transistor having a source / drain connected between a second power supply potential and the output node;
While the control signal has the first level, the second P-channel MOS transistor turns on the second P-channel MOS transistor when the potential of the output node is lower than the third power supply potential. A second gate potential generation circuit for generating a gate potential of the transistor;
While the control signal has the second level, the second N-channel MOS is set to turn on the second N-channel MOS transistor when the potential of the output node is higher than the fourth power supply potential. A third gate potential generation circuit for generating a gate potential of the transistor;
The semiconductor integrated circuit according to claim 3, comprising: The second drive circuit comprises:
A second P-channel MOS transistor having a source / drain connected between a first power supply potential and the output node;
A second N-channel MOS transistor having a source / drain connected between a second power supply potential and the output node;
While the control signal has the first level, the gate potential of the second P-channel MOS transistor is generated so as to turn on the second P-channel MOS transistor for a predetermined period. A second gate potential generation circuit for generating a gate potential of the second N-channel MOS transistor so as to keep the second N-channel MOS transistor on for a predetermined period while
The semiconductor integrated circuit according to claim 3, comprising:

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