JP2008207856A - Tray for semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tray for a semiconductor apparatus which prevents erroneous storage of the semiconductor apparatus and mixture of different kinds among a plurality of trays from occurring by a simple constitution. <P>SOLUTION: The tray for the semiconductor apparatus has the outer peripheral frame and a semiconductor storing part surrounded by the outer peripheral frame and divided into a latticed shape. The outlines of respective trays are unified and a plurality of kinds of the semiconductor apparatus are respectively carried. A mark which enables discrimination from the trays on which the other kinds of semiconductor apparatus are carried is provided on the tray on which a kind of the semiconductor apparatus is carried. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique that is effective when applied to a semiconductor device tray. For example, the present invention is effective when applied to a semiconductor device tray on which a plurality of types of semiconductor devices are mounted with a uniform outer shape so as to conform to a specific standard. It is about technology.

The tray for a semiconductor device has a semiconductor device storage section partitioned in a lattice shape by ribs provided on the outer peripheral frame. A semiconductor device adapted to the semiconductor device storage unit is mounted in the semiconductor device storage unit, and is used when the semiconductor device is shipped and transported. With regard to such a tray, there are, for example, Japanese Patent Application Laid-Open Nos. 11-349087 and 2005-067693. In addition, there is a JEDEC standard as a tray design standard.
Japanese Patent Laid-Open No. 11-349087 JP 2005-067693 A

  The JEDEC (Joint Electron Device Engineering Council) standard, which is a tray design standard, only determines the size of each part in detail. Standards relating to packages of various sizes and forms are prepared for semiconductor devices. For example, packages having different sizes such as BGA, LGA, SOP, or QFP exist with the same size, and may be stored in a different tray by mistake and shipped. Furthermore, QFP packages are available in several different packages (QFP, LQFP, and TQFP) such that only the thickness is 2.7 mm, 1.4 mm, and 1.0 mm. You need to be careful. In addition, even if each semiconductor device is stored in the correct tray, different shipments in which different trays are mixed when a plurality of semiconductor devices are stacked, or another semiconductor device is stored when mounted on a mounting machine. There is a problem that incorrect mounting is performed by erroneously mounting the tray. Therefore, the inventors of the present application have developed a tray for a semiconductor device that facilitates the discovery of mixing of different varieties.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device tray that prevents erroneous storage of semiconductor devices and mixing of different products among a plurality of trays with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An embodiment of the invention disclosed in the present application will be briefly described as follows. That is, the tray for a semiconductor device has an outer peripheral frame and a semiconductor device storage section surrounded by the outer peripheral frame and partitioned in a lattice shape, and the outer shape is unified and a plurality of types of semiconductor devices are mounted. A tray on which one type of semiconductor device is mounted is provided with a mark that enables discrimination from a tray on which another type of semiconductor device is mounted.

  With the above mark, it is possible to prevent erroneous storage of the semiconductor device and mixing of different types of products among a plurality of trays.

  FIG. 1 shows a plan view of an embodiment of a tray for a semiconductor device according to the present invention. The tray for a semiconductor device has a rectangular outer wall portion 1, a grip portion 2 provided on both sides of the short side, and a plurality of concave portions (notches) 3 as tray identification marks. The outer wall 1 is formed so as to conform to the JEDEC standard, which is a tray design standard. The outer wall portion 1 is also referred to as a leg portion or a skirt portion, and ribs are provided on the inner side of the outer wall portion 1 to form a housing portion for a semiconductor device. The storage unit includes a storage unit that stores individual semiconductor devices by ribs (not shown) formed in a lattice shape corresponding to the size of the semiconductor device to be stored.

  FIG. 2 shows a plan view and a side view of an embodiment of a tray for a semiconductor device according to the present invention. In the side view, the side surface in the longitudinal direction and the side surface in the lateral direction are shown. A housing portion of one semiconductor device is divided into 4 × 10 by ribs provided by the outer wall portion 1. The outer wall portion 1 is divided into a lower outer wall portion 11 and an upper outer wall portion 12. The outer periphery of the upper outer wall portion 12 is made smaller than the inner periphery of the lower outer peripheral wall 11, and the lower outer peripheral wall 11 of another similar semiconductor device tray can be fitted and stacked. That is, the lower outer wall portion 11 of the upper tray is fitted into the upper outer wall portion 12 of the lower tray and can be stacked in multiple stages. The plurality of concave portions 3 provided in the vertical direction are provided in a part of the lower outer peripheral wall 11 of the outer peripheral wall 1 while satisfying such a condition that they can be stacked.

  In this embodiment, as shown in the figure, a maximum of five concave portions 3 are provided on the left and right with respect to the midpoint of the lower outer wall portion 11, and a total of ten concave portions are provided for specific tray identification. Among the recesses, a plurality of marks are added depending on the combination of the number provided and the positions thereof. For example, even if only one recess 3 is used, it is possible to form marks that can be identified in 10 ways by changing the positions where the recesses are provided, and in the combination using two recesses, 9 + 8 + 7 +. Thus, marks that can be identified in 45 ways can be formed. In this way, by managing the number and positions of the concave portions provided in the side surface portion of the tray, it is possible to avoid the same code as a bar code and form a uniform tray.

  In the JEDEC standard, the outer shape is the same regardless of the shape difference of the mounted semiconductor device (package). For example, six locations marked with * in the storage section such as 4 × 10 are considered to have no holes (6 positions without holes). Also, as shown in the partially enlarged view of FIG. 3, a tray index is provided at one corner of the tray. The tray direction is determined based on the tray index. Based on the tray index, the position of the IC index of the semiconductor device stored in the storage unit is determined. That is, one pin of the semiconductor device (IC) is arranged and stored in the same direction (lower left in FIG. 3) with respect to the tray index (lower right in FIG. 2, lower left in FIG. 3). And as a countermeasure against static electricity, most of the molding materials are kneaded with carbon, and because the color tone is black and the same, if different types of trays are mistakenly stacked without the above-mentioned mark However, it is difficult to distinguish this. However, the discovery is facilitated by attaching the mark as described above.

  FIG. 4 is an explanatory view of an embodiment of a partially enlarged recess of the semiconductor device tray according to the present invention. In this embodiment, the lower outer wall portion 11 where the mark (concave portion) 3 as the mark is provided is the lower outer wall portion 11 where the tray index is provided on the left side. In other words, the lower outer wall portion 11 in the longitudinal direction is determined such that a maximum of five concave portions are provided at specific positions on the left and right with the central concave portion as shown in FIG. 1 as described above. .

  FIG. 5 is a schematic explanatory view of one embodiment of a mounting machine to which the semiconductor device tray according to the present invention is mounted. The mounting machine (mounter) has a component storage unit. As shown in the figure as an enlarged perspective view, the component storage section includes a plurality of trays in which semiconductor devices are stored and stacked as described above (the outer wall 1 is shown as a representative of the tray). Is stored (mounted). The trays 1 are cut out one by one from the lower part (or upper part) of the tray bundle thus mounted, placed on the slide jig 4 and moved horizontally to be moved into the apparatus. The slide jig 4 is a metal part such as aluminum. In this way, since a plurality of trays are stacked and mounted, it is possible to easily find a mixture of different types of trays using the mark.

  FIG. 6 shows a side view of an example of a state in which semiconductor device trays according to the present invention are stacked. In this embodiment, the mark is made of satin instead of the convex portion as described above. That is, since the surface of the tray is smooth, a textured surface with fine unevenness is provided on the tray so as to have a vertical belt shape equivalent to the concave portion. When trays with different patterns, i.e., patterns with different numbers and positions, are mixed, they can be easily found by visual inspection without the uniform pattern. In this way, trays of different model numbers (= different patterns) can easily find mixed different types of products by visually observing the side surface specified by the tray index.

  FIG. 7 shows an explanatory view of the shipping packaging of the semiconductor device using the semiconductor tray according to the present invention. The plurality of trays in which the semiconductor devices are stored are stacked and collected by bands provided on both sides of the long side. A desiccant and a humidity indicator are placed on the top and placed in a moisture-proof bag. An interior label is affixed to the top surface of the moisture-proof bag. Then it is put in an interior box and sealed with tape. At this time, when the tray according to the present invention is used, erroneous mixing of different trays can be easily distinguished as shown in FIG.

  The semiconductor tray according to the present invention can facilitate the sorting operation when the reuse tray is operated, leading to reduction of erroneous delivery of different products. A reuse tray is a tray that a semiconductor manufacturer has once mounted and delivered to a customer (mounting manufacturer). The tray is sorted and washed so that it can be collected and reused by a specialist, and then delivered again to the semiconductor manufacturer. This is a system for effective use of resources. In such cleaning and the like, the mark by the concave portion or the satin can ensure durability and does not become an obstacle to cleaning.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Not too long. For example, the concave portion as an identification mark provided on the tray may be a convex portion. As described above, the identification mark can take various embodiments. The shape of the concave portion provided in the tray can take various embodiments such as a semicircular shape and a rectangular shape in addition to the triangular shape. The present invention may be anything as long as the outer wall is divided into an upper part and a lower part and can be fitted in the same manner as described above, in addition to the one that conforms to the JEDEC standard, as in the JEDEC standard. The present invention can be widely used for a tray for a semiconductor device.

It is a top view which shows one Example of the tray for semiconductor devices which concerns on this invention. It is the top view and side view of one Example of the tray for semiconductor devices which concern on this invention. FIG. 3 is a partially enlarged view of the tray of FIG. 2. It is explanatory drawing of the recessed part to which the partial expansion of the tray for semiconductor devices which concerns on this invention was carried out. It is a schematic explanatory drawing which shows one Example of the mounting machine with which the tray for semiconductor devices which concerns on this invention is mounted | worn. It is a side view showing an example of the state where the tray for semiconductor devices concerning this invention was piled up. It is explanatory drawing of the shipping packaging of the semiconductor device using the tray for semiconductors concerning this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Outer wall part, 11 ... Lower outer wall part, 12 ... Upper outer wall part, 13 ... Top surface, 2 ... Grip, 3 ... Mark (recessed part, satin)

Claims (5)

An outer wall,
A semiconductor device housing portion surrounded by the outer peripheral frame and partitioned in a lattice shape;
A semiconductor device tray in which a plurality of types of semiconductor devices are mounted with a uniform outer shape,
The tray on which one type of semiconductor device is mounted is a tray for a semiconductor device having a mark that enables discrimination from a tray on which another type of semiconductor device is mounted. In claim 1,
The outer peripheral wall is
It is divided into an upper outer peripheral wall and a lower outer peripheral wall,
The outer periphery of the upper outer peripheral wall is made smaller than the inner periphery of the lower outer peripheral wall, and can be stacked by fitting the lower outer peripheral wall of another semiconductor device tray,
The tray for semiconductor devices which has the said mark in the same location outside the said outer peripheral wall. In claim 2,
The mark is a tray for a semiconductor device that is a combination of the number, position, and interval of a plurality of protrusions or grooves provided in the vertical direction on the outer peripheral wall surface. In claim 2,
The mark is a tray for a semiconductor device, which is a combination of the number, position, and interval of a plurality of belt-like satin finishes provided in the vertical direction on the outer peripheral wall surface. In claim 3 or 4,
The semiconductor device tray is a semiconductor device tray that has the same color tone by kneading carbon into the molding material and conforms to the JEDEC standard.

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