JP2008205749A - Pulse signal output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a "pulse signal output circuit" which can prevent the generation of a harmonic component which leads EMC (Electro Magnetic Compatibility) interference from a wiring pattern or a signal line of the pulse signal output circuit or succeeding circuits using a simple circuit composition. <P>SOLUTION: For example, a 3-signal summing system of the invention multiplies a first weighting factor (0.2) by an input pulse, forms a first variance pulse which is compressed in a height direction, performs a first delay (τ1) processing to the pulse, multiplies a second weighting factor (0.6) which forms the necessary wave form height in order to establish a threshold value in a succeeding circuit, forms a second variance pulse which is compressed in the height direction, performs a second delay (τ2) processing to the pulse, multiplies a third weighting factor (0.2), then forms a third variance pulse which is compressed in the height direction. An adder forms a waveform for establishing the threshold value in an intermediate part of the height direction of the waveform, and a waveform with a step difference in its upper and lower sides by adding these signals. Arbitrary waveforms can be formed by the similar method, such as a 5-signal summing system, etc. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pulse signal output circuit that prevents EMC interference caused by a digital signal, and in particular, can reduce the emission of harmonic components that cause EMC interference without degrading the original characteristics of the pulse signal. The present invention relates to a pal signal output circuit.

  In recent years, with the widespread use of electronic devices, the number of devices that generate electromagnetic waves has increased, and the effects of the electromagnetic waves on the devices themselves and the effects on other peripheral devices have become problems. This problem has attracted attention as an EMC (Electromagnetic Compatibility) problem as well as a problem that each device is affected by these electromagnetic waves. In order to deal with this EMC problem, laws and regulations have been established in each country, including Japan, to prevent products that do not conform to the standard from entering the market.

  As countermeasures for EMC as described above, countermeasures against electromagnetic waves generated from digital devices are particularly important due to the rapid spread of digital devices, the strength of generated electromagnetic waves, and the strength of the impact of increasing the speed of digital signals. ing. In a digital device, the use of a pulse signal can prevent a signal change that occurs in the signal transmission process. This pulse signal has a rectangular shape of a normal pulse output waveform as shown in FIG. When it is a wave, a harmonic corresponding to the magnitude of the signal fluctuation is generated at each corner of the signal waveform, and for example, a strong and wide-range harmonic as shown in FIG. Since this harmonic has a strong influence on the surrounding circuits and devices from the wiring pattern and signal line in the subsequent stage after the pulse signal output circuit, it is important to reduce this as much as possible.

  As a countermeasure, it is conceivable to use a waveform consisting of a smooth curve without corners of the output waveform. In this case, for example, it is conceivable to use a sine wave as shown in FIG. However, such a sine wave is not suitable for a digital circuit because a temporal fluctuation (jitter) occurs in a subsequent IC circuit in which the signal is used because of a relationship between a threshold value and noise. That is, as shown in the figure, when performing signal processing for transmitting the signal by a sine wave and forming the next signal waveform by cutting at a predetermined threshold in the subsequent IC circuit as in the case of a normal digital circuit, as shown in the figure. In this case, the point at which the sine wave is cut changes due to threshold fluctuation or noise superposition, thereby causing jitter as a response time shift, and an accurate signal cannot be transmitted.

  Therefore, it is ideal that the rise is steep as much as possible within the threshold variation range of the subsequent IC, but there is ideally a smooth round outside the threshold range. For example, a waveform as shown in FIG. 7D is preferable. That is, when transmitting and receiving the normal pulse output waveform shown in FIG. 7 (a), the receiving side takes into account some deformation of the received signal and considers the lowest and highest parts of the signal within the total height of the pulse. In many cases, a threshold is set to 20 to 80% between the sections, and the received signal is shaped and used at the point where the threshold is cut. Therefore, a vertical waveform with little deformation during transmission is preferable in this range, and on the other hand, the other 0 to 20% and 80 to 100% portions have smooth curves as shown in FIG. Is desirable from the viewpoint of preventing the generation of harmonics.

Japanese Patent Publication No. 6-28329 (Patent Document 1) discloses a technique in which a harmonic component generated from a pulse signal in a facsimile apparatus or the like is shaped into a sine wave component using a delay circuit and a comparison circuit. Japanese Laid-Open Patent Publication No. 5-152908 (Patent Document 2) discloses a technique for shifting a clock signal that is likely to generate a harmonic component by using a multistage delay circuit.
Japanese Examined Patent Publication No. 6-28329 JP-A-5-152908

  As described above, when outputting pulse signals, harmonics are generated especially by the corners of the pulse, and the waveforms at the corners are as small as possible to prevent other circuits in the equipment and other equipment from being affected. In addition, since it is preferable that the portion where the threshold value is set so that the signal can be transmitted accurately has a vertical waveform, it is preferable to have a waveform as shown in FIG. However, in order to wave-form only the 0 to 20% and 80 to 100% portions between the lowest and highest portions of the signal into a smooth curve, a complicated circuit is required, which must be expensive. It is difficult to use widely in digital devices that are widely used in large quantities.

  Therefore, the present invention can prevent the generation of harmonic components that cause EMC interference from the wiring patterns and signal lines after the pulse signal output circuit with a simple circuit configuration, and at the subsequent stage of the pulse signal output circuit. An object of the present invention is to obtain a pulse signal output circuit capable of obtaining an accurate signal when a received signal is used by setting a threshold in a circuit using this pulse.

  In order to solve the above-described problem, the pulse signal output circuit according to the present invention multiplies an input pulse by a first weighting factor to form a first modified pulse forming means that forms a first modified pulse compressed in the height direction. And a second deformation that is compressed in the height direction by performing a first delay process on the pulse and multiplying by a second weighting factor that forms a waveform height necessary for setting a threshold value in a circuit in the subsequent stage. Second deformed pulse forming means for forming a pulse, and a third deformed pulse compressed in the height direction by performing a second delay process larger than the first delay time and multiplying the pulse by a third weighting factor. A third modified pulse forming unit for forming the first modified pulse and an adding unit for adding the first to third modified pulses, and the modified unit outputs a modified pulse signal having steps on the upper and lower portions of the second modified pulse. It is characterized by doing.

  Another pulse signal output circuit according to the present invention is the pulse signal output circuit, wherein at least one of the first modified pulse and the third modified pulse has a delay and a weighting factor with respect to the input pulse. A modified pulse forming means for forming another modified pulse by performing multiplication is added, all the modified pulses are added by an adder, and a pulse signal in which steps are further formed at the upper and lower portions of the second modified pulse is output. It is characterized by that.

  Further, another pulse signal output circuit according to the present invention is in the pulse signal output circuit, and the weighting factor is selected so that heights of all the transformed pulses after the addition coincide with the original pulses. It is characterized by.

  Another pulse signal output circuit according to the present invention is the pulse signal output circuit, wherein the second weighting factor of the second modified pulse forming means is set to 20 to 80% of the input pulse. And

  Further, another pulse signal output circuit according to the present invention is the pulse signal output circuit, wherein the total delay amount by the delay processing is set in a range in which the modified pulse signal after the addition does not change with the height of the input pulse. It is characterized by that.

  Since the present invention is configured as described above, it is possible to prevent generation of harmonic components that cause EMC interference from wiring patterns and signal lines after the pulse signal output circuit with a simple circuit configuration, and the pulse In a circuit that uses this pulse in the subsequent stage of the signal output circuit, an accurate signal can be obtained when the received signal is used by setting the threshold.

  The present invention aims to prevent the generation of harmonic components that cause EMC interference from wiring patterns and signal lines after the pulse signal output circuit with a simple circuit configuration. A first modified pulse forming means for multiplying and forming a first modified pulse compressed in the height direction, and a waveform height necessary for performing a first delay process on the pulse and setting a threshold value in a subsequent circuit A second deformation pulse forming means for forming a second deformation pulse compressed in the height direction by multiplying by a second weighting factor for forming a height, and a second delay greater than the first delay time in the same pulse A third modified pulse forming means for performing processing and multiplying by a third weighting coefficient to form a third modified pulse compressed in the height direction; and an adding means for adding the first to third modified pulses. , The second change from the adding means. It was realized by outputting the modified pulse signals having a level difference in the vertical portion of the pulse.

  Embodiments of the present invention will be described with reference to the drawings. In the pulse signal output circuit according to the present invention, for example, a rectangular pulse used for a conventional clock pulse or the like as shown in FIG. When the IC circuit is, for example, a C-MOS circuit, an input threshold range of 20% to 80% is guaranteed. Accordingly, a vertical waveform is obtained in the range of 20 to 80% of the pulse waveform height. 3 signal addition waveform that forms one step up and down as shown in FIG. 2B in the lower 0-20% portion and the upper 80-100% portion with the above-mentioned Or, as shown in Fig. 5 (c), a 5-signal sum waveform that forms two steps above and below, etc. Large harmonic generation by It is obtained so as to prevent the occurrence of.

  The waveform shown in FIG. 1B can be formed by, for example, a pulse signal output circuit shown in FIG. That is, in the figure, the waveform V of the rectangular input pulse signal P is directly multiplied by 20% (0.2) as the first weighting factor in the first weighting factor (gain) multiplier G1 and compressed in the pulse height direction. The first waveform V1 is input to the adder A. The waveform V of the same input pulse signal P is passed through a first delay unit B1 that delays by τ1, and the signal is compressed by multiplying the second weighting factor multiplier G2 by 60% (0.6) as a second weighting factor. The second waveform V2 is input to the adder A. Further, the signal waveform after passing through the first delay unit D1 is passed through the second delay unit B2 that delays the signal waveform by τ2, and the signal is set to 20% (0.2) as the third weighting factor in the third weighting factor multiplier G3. Multiply and compress, and input to the adder A as the third waveform V3.

  By the three-waveform addition circuit configuration using the two delay circuits and the three weighting factor multipliers as described above, the rising edge of the pulse rises by 20% from the adder A as shown in the lower part of FIG. A stepped rising portion U is formed by one rising portion U1, a second rising portion U2 that rises 60% after the delay time τ1, and a third rising portion U3 that rises 20% after the delay time τ2, and as a whole An added signal output having the same height as the pulse of the input signal is obtained.

  In the above example, the third waveform is delayed by the second delay unit B2 to which the output of the first delay unit B1 is input. However, for example, the third waveform is directly transmitted without going through the first delay unit B1. It can also be implemented by introducing an input pulse and making it a second delay unit that delays at least the delay amount of the first delay unit B1. The same applies to the 5-signal addition method described later.

  Further, since the first waveform V1 disappears from the time when the pulse width T of the input waveform is reduced by (τ1 + τ2), the first falling portion D1 that falls by 20% is formed. Similarly, the second falling portion D2 falling by 60% is formed when the second waveform V2 disappears after the subsequent delay time τ1, and the third waveform V3 disappears after the subsequent delay time τ2. A third falling portion D3 that falls by 20% is formed, thereby forming a stepped falling portion D as a whole. As a result, the rising and falling parts as shown in FIG. 2B form a stepped waveform as a whole, and a pulse having the same pulse width T as the input pulse can be formed in the threshold setting part.

  In the above example, the operation of the shaping of the positive rectangular wave as the first rising waveform in the shaping of the pulse waveform has been described, but the same applies to the shaping of the negative rectangular wave as the first falling waveform. In this case, the first falling part is formed with a waveform processed by the first weighting factor multiplier G1 without delaying, and the second falling part is delayed by the first delay unit B1 and then second. The waveform may be formed by the waveform processed by the weighting factor multiplier G2, and the portion that falls next may be further delayed by the second delay unit B2, and then processed by the third weighting factor multiplier G3. By such processing, similar steps are formed at the rising portion as described above.

  In the above example, a step of 20% is formed across 60% of the central portion in the height direction of the rectangular pulse wave, but a threshold is set as shown in FIG. 1 (c). By forming two steps of 10% on the top and bottom across 60% of the central portion, a pulse with less generation of harmonics can be output.

  The waveform shown in FIG. 1C can be formed by a pulse signal output circuit similar to that shown in FIG. 2 shown in FIG. 3, for example. That is, in the pulse signal output circuit shown in FIG. 3, a third delay unit B3 that is delayed by a delay time τ3 and a fourth delay unit B4 that is delayed by a delay time τ4 are added to the circuit similar to FIG. After the signal passed through the unit is multiplied by the weighting factor by the fourth weighting factor multiplier G4 and the fifth weighting factor multiplier G5, all are added by the adder A. In this circuit, the first, second, fourth, and fifth weighting factors are set to 10%, and they are multiplied by 0.1 and compressed in the height direction of the waveform.

  With such a five-waveform addition circuit configuration using four delay circuits and five weighting factor multipliers, 10% across 60% of the central portion in the height direction of the rectangular pulse wave as shown in the lower part of FIG. Each step can be formed, changes more smoothly than the waveform formed by the circuit of FIG. 2, and can approach the ideal output waveform shown in FIG. By using the same method, it is possible to form more multi-level steps in the upper and lower sides of the 60% portion of the center where the threshold is set, resulting in a smoother waveform. It is arbitrarily set according to the necessity according to the effect. In addition, as described above, a step can be formed only on one side, in addition to forming a step of 10% on both sides of the center portion.

  Note that if the delay time τ is too large, the minimum value portion and the maximum value portion of the input pulse may not remain. Therefore, the delay time setting is appropriately adjusted to leave the minimum value portion and the maximum value portion of the input pulse. It is preferable to set so. Further, when setting the weighting factor as described above, it is preferable to set so that the total waveform height after addition is the same as the original waveform. However, as long as there is no large change in waveform height as a whole, it does not necessarily have to be exactly the same as the original waveform.

  By performing such waveform shaping according to the present invention, for example, as shown in FIG. 4, the normal pulse output of FIG. Even with the three-signal addition pulse, which is the minimum aspect of the present invention as shown in FIG. 4B, the effect of reducing harmonic generation as shown in FIG. This effect can provide a more effective harmonic generation prevention effect by adding more signals such as the 5-signal addition pulse.

  When the pulse signal output circuit according to the present invention as described above is used, in the subsequent IC circuit or the like using this circuit, the time is shifted from the input signal in the portion where the threshold value is set. However, the clock signal of the subsequent IC circuit can be matched by using the same circuit as described above.

  The present invention can obtain a smoothing effect by reducing the level difference of the signal except for the central portion of the waveform that requires setting the threshold as described above, and can output a pulse with less generation of harmonic components. However, when ground noise occurs in the output pulse, the response time shift is less than that of the conventional rectangular wave that is simply subjected to CR smoothing to reduce the generation of harmonic signals. The effect of eliminating jitter can be obtained.

  That is, for example, in the case of the waveform smoothing method using the conventional CR of FIG. 5, when there is no ground noise as shown in FIG. When the waveform is blunted with CR and the waveform is smoothed as shown in (a) and (ii) to reduce the generation of harmonics, the same is applied to the pulse utilization circuit in the subsequent stage of this pulse generation circuit. If this pulse is used with a subsequent threshold set as shown in the figure, there is a problem that the duty ratio slightly changes depending on the threshold, but in many cases it does not cause a serious problem as in (a) (iii). Waveforms can be formed.

  However, when ground noise is mixed as shown in FIG. 5B, the same source waveform is used as shown in (b) and (i), and this is the same as described above as shown in (b) and (ii). When outputting an annealed waveform that has been dulled, a waveform distorted by ground noise is transmitted. When a post-threshold value similar to the above is set for such a distorted waveform, the H / L time relationship on the receiving side is distorted due to noise as shown in (b) and (iii), and jitter is generated. Can be a big problem. As described above, in the case of a digital signal, the time relationship of H / L transition is particularly important in the case of a clock signal, and this jitter needs to be sufficiently considered.

On the other hand, in the present invention in which the waveform processing as described above is performed, it is possible to sufficiently cope with this problem as shown in the action for ground noise according to the present invention in FIG. That is, in the example of the three-signal addition waveform obtained by the present invention shown in FIG. 11 (i), the waveform becomes distorted as shown in the figure when ground noise is generated as shown in FIG. The rising and falling vertical waveform parts in the generated waveform are not affected by the ground noise and are not deformed.Therefore, there is no change in the threshold setting part set in the subsequent circuit using this pulse, and the threshold setting range is somewhat In the setting range that is normally used although it is narrowed, it is possible to form a waveform that is not affected by ground noise as shown in FIG. Thereby, even if the threshold value changes due to temperature drift or the like, if it is within the range shown in the figure, there is an effect that there is no particular problem. In this case, the action is further ensured by appropriately setting the weighting coefficient used in waveform creation in consideration of the action.

  With respect to the present invention as described above, a circuit was actually created and its operation and effect were confirmed. In this case, an AND gate CMOS was used, the input voltage PIN was a digital output waveform point from a conventional IC, and an output waveform was obtained by synthesizing five signals. TC74HC08 was used as the delay element. Gain can be set by resistance division, and the adder circuit can be set by simple analog addition.

It is a figure which shows the example of the waveform obtained by this invention. It is a figure which shows the example of the pulse signal output circuit which forms the 3 signal addition waveform by this invention. It is a figure which shows the example of the pulse signal output circuit which forms the 5-signal addition waveform by this invention. It is a figure which shows the state of the harmonic generation of the 3 signal addition waveform obtained by this invention, and the conventional pulse waveform. It is a figure explaining the effect | action that the pulse obtained by the conventional CR waveform annealing method is influenced by the ground noise. It is a figure explaining the effect | action which the pulse waveform obtained by this invention is hard to be influenced by ground noise. It is a figure explaining a pulse waveform and harmonic generation.

Claims (5)

First deformed pulse forming means for multiplying the input pulse by a first weighting factor to form a first deformed pulse compressed in the height direction;
A second modified pulse compressed in the height direction is obtained by performing a first delay process on the pulse and multiplying by a second weighting factor that forms a waveform height necessary for setting a threshold value in a subsequent circuit. Second deformation pulse forming means to be formed;
A third modified pulse forming means for performing a second delay process larger than the first delay time on the same pulse and multiplying by a third weighting factor to form a third modified pulse compressed in the height direction;
Adding means for adding the first to third deformation pulses;
A pulse signal output circuit that outputs a deformed pulse signal having steps on the upper and lower portions of the second deformed pulse from the adding means.   At least one of the first modified pulse and the third modified pulse includes modified pulse forming means for forming another modified pulse by multiplying an input pulse by a delay and a weighting factor, and all 2. The pulse signal output circuit according to claim 1, wherein the modified pulses are added by an adder, and a pulse signal in which a step is further formed in the upper and lower portions of the second modified pulse is output.   2. The pulse signal output circuit according to claim 1, wherein the weighting factor is selected so that heights of all the transformed pulses after the addition coincide with the original pulses.   2. The pulse signal output circuit according to claim 1, wherein the second weighting factor of the second modified pulse forming means is set to 20 to 80% of the input pulse.   2. The pulse signal output circuit according to claim 1, wherein the total delay amount by the delay processing is set in a range in which the transformed pulse signal after the addition does not change with the height of the input pulse.

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