CN110350917B

CN110350917B - Electronic device and compensation method of zero cross-over distortion

Info

Publication number: CN110350917B
Application number: CN201810419488.XA
Authority: CN
Inventors: 孙积永
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2018-04-02
Filing date: 2018-05-04
Publication date: 2022-12-30
Anticipated expiration: 2038-05-04
Also published as: CN110350917A; TW201943206A; TWI638518B

Abstract

The invention provides an electronic device and a compensation method of zero cross-over distortion. The electronic device comprises a pre-offset circuit, a control circuit, a driving stage circuit and a load circuit. The control circuit receives and compares the pre-offset input signal generated by the pre-offset circuit and the reference signal to generate at least two control signals. The control circuit delays one of the control signals so that the start-up periods between the at least two control signals do not overlap. The driving stage circuit comprises at least two driving switches, and the driving switches determine the conducting state of the driving switches according to at least two control signals respectively so as to drive the load circuit. The pre-offset circuit adjusts the input signal according to the polarity of the input signal and a preset offset value to generate a pre-offset input signal. The preset offset value is related to at least two time periods that the control signals do not overlap with each other.

Description

Electronic device and compensation method of zero cross-over distortion

Technical Field

The present invention relates to pulse width modulation and pulse code modulation, and more particularly, to an electronic device and a method for compensating for zero cross-over distortion by pre-compensating an input signal.

Background

Pulse Width Modulation (PWM) and/or Pulse-code modulation (PCM) is a technology for converting an analog signal into a digital signal or digitizing the analog signal, and is commonly used in electronic devices such as audio devices (e.g., speakers) and motors that require fine signal control.

Electronic devices using PCM or PWM techniques often compare an analog signal (e.g., a PCM signal or a PWM signal) with a reference waveform signal to generate a control signal for a driver stage circuit. The driver stage circuit is typically implemented by two driver switches. In order to avoid that the two driving switches are turned on or off at the same time, the driving circuit of the electronic device usually makes the control signals of the two driving switches not be turned on at the same time. However, since the analog signal is usually a continuous signal, if the driving switches are not turned on simultaneously, energy of part of the signals is inevitably lost, and Zero cross-over Distortion (Zero cross Distortion) is generated. In the case of requiring signal pair to perform fine control processing, zero cross distortion will cause some abnormalities to the electronic equipment, such as audio discontinuity, noise generation, and motor running irregularity. In the related art (e.g., audio equipment, electronic equipment with a small motor) requiring smooth signals without being affected by noise, the influence of zero-cross distortion will cause poor operation feeling for the user.

Therefore, in an electronic device using PCM or PWM technology, it is an important issue to compensate an electronic device that may have zero cross-talk distortion so as to eliminate the influence of the zero cross-talk distortion as much as possible.

Disclosure of Invention

The invention provides an electronic device using pulse width modulation and a compensation method of zero cross-over distortion.

The electronic device comprises a pre-offset circuit, a control circuit, a driving stage circuit and a load circuit. A pre-offset circuit obtains an input signal to generate a pre-offset input signal. The control circuit is coupled with the pre-offset circuit. The control circuit receives and compares the pre-offset input signal and a reference signal to generate at least two control signals. The control circuit delays one of the at least two control signals such that the activation periods between the at least two control signals do not overlap. The driving stage circuit is coupled with the control circuit. The driving stage circuit comprises at least two driving switches, and the at least two driving switches determine the conducting state of the driving switches according to at least two control signals respectively. The load circuit is coupled with at least two driving switches of the driving stage circuit. The load circuit is driven in dependence on said conductive state of the at least two drive switches. The pre-offset circuit adjusts the input signal according to the polarity of the input signal and a preset offset value to generate a pre-offset input signal, wherein the preset offset value is related to a time period when at least two control signals are not overlapped with each other in starting.

The compensation method of zero cross-over distortion is suitable for the electronic device comprising the load circuit. The compensation method comprises the following steps: adjusting the input signal according to the polarity of the input signal and a preset offset value to generate a preset offset input signal; comparing a pre-offset input signal and a reference signal to generate at least two control signals, wherein one of the at least two control signals is delayed so that start-up periods between the at least two control signals do not overlap with each other; and driving the load circuit according to the conducting states of the at least two driving switches. The preset offset value is related to a time period that the at least two control signals do not overlap each other when being started.

In view of the above, the electronic device and the compensation method of zero-cross distortion described in the present invention first utilize the pre-offset circuit to increase or decrease the voltage of the input signal by the pre-offset value according to the polarity (e.g., the positive signal and the negative signal) of the input signal, so as to generate the pre-offset input signal, where the pre-offset value is related to the non-overlapping time period (this time period may be referred to as an alert area) of the two control signals generated by the control circuit when the two control signals are activated. Then, when the pre-offset input signal passes through the control circuit to generate the control signal of the driving stage circuit, since the control circuit delays one of the at least two control signals so that the start periods of the at least two control signals do not overlap with each other, the pre-offset operation of the input signal can compensate the influence of zero-cross distortion generated by the control circuit delaying the control signal, and increase the signal-to-noise ratio (SNR) of the electronic device near the zero point (i.e., the time point when the input signal switches polarity).

Drawings

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a block diagram of an electronic device according to an embodiment of the invention.

FIG. 2 is a timing diagram of the signals involved in the positive control timing generator and the negative control timing generator shown in FIG. 1.

Fig. 3A is a circuit diagram and timing diagram of the driving non-overlap control circuit shown in fig. 1.

Fig. 3B is a circuit diagram and timing diagram of the driving non-overlap control circuit shown in fig. 1.

Fig. 4 is a signal-to-noise ratio diagram of a load circuit of an electronic device.

Fig. 5 is a block diagram of an electronic device according to an embodiment of the invention.

FIG. 6 is a block diagram of the pre-offset circuit of FIG. 5.

FIG. 7 is a diagram illustrating a comparison between the value VPS of the pre-shifted input signal PS and the value VSPCM of the input signal SPCM according to an embodiment of the present invention.

Description of the symbols:

100. 500: electronic device with a detachable cover

110: control circuit

112: forward control sequence generator

114: negative control sequence generator

116. 118: drive non-overlapping control circuit/circuit

120: driving stage circuit

122: forward driving stage circuit

124: negative driving stage circuit

130: load circuit

140: reference signal generator

500: electronic device

560: pre-offset circuit

570: feedback circuit

610: signal polarity analyzer

620: input signal adjusting circuit

622: multiplier and method for generating a digital signal

624: sign change-over switch

626: adder

630: signal saturation clipping device

SPCM: input signal

Sref: reference signal

Inverted reference signal

PBV: presetting an offset value

PS: pre-offset input signal

CLK: clock signal

SCP, SCN: signal

OR: OR gate

And (3) Delay: delay device

SCP1, SCP2, SCN1, SCN2: control signal

TP1, TP2, TN1, TN2: point in time

GZP: time period of warning zone

MP1, MP2, MN1, MN2: transistor with a metal gate electrode

L1, L2, L3, L4: thread

VSPCM: value of input signal

P: power gained by the load circuit

Pi: power of

VPS: pre-offsetting values of input signals

VSPCM: value of input signal

Detailed Description

Fig. 1 is a block diagram of an electronic device 100. Referring to fig. 1, an electronic device 100 mainly includes a control circuit 110, a driving stage circuit 120, and a load circuit 130. The electronic device 100 of the present embodiment is mainly for digital audio applications, and the load circuit 130 in the electronic device 100 is a speaker as an example. Of course, the electronic device 100 shown in fig. 1 can be applied to other fields, such as motor driving requiring fine control, image processing, etc. The electronic device 100 may also include a reference signal generator 140. The reference signal generator 140 is used for generating a reference signal Sref. The type of the reference signal Sref of the present embodiment is a triangular waveform (triangular waveform) signal or a saw-tooth waveform (sawtooth waveform) signal.

The control circuit 100 is configured to receive the input signal SPCM and the reference signal Sref, and compare the input signal SPCM and the reference signal Sref to generate at least two control signals (e.g., control signals SCP1 and SCP2, and SCN1 and SCN 2). The driving stage circuit 120 determines the conduction states of at least two driving switches according to at least two control signals (e.g., control signals SCP1 and SCP2, control signals SCN1 and SCN 2). In detail, the driving stage circuit 120 includes a positive driving stage circuit 122 and a negative driving stage circuit 124. The forward driving stage circuit 122 includes two driving switches, and is implemented by a P-type transistor MP1 and an N-type transistor MN1, respectively; the negative driving stage circuit 124 includes two driving switches, and is implemented by a P-type transistor MP2 and an N-type transistor MN2, respectively. The load circuit 130 is driven according to the on states of the driving switches (transistors MP1, MP2, MN1, and MN 2). The load circuit 130 may include a speaker, motor, or other load element.

The control circuit 110 of the present embodiment may include control timing generators (e.g., positive (positive) control timing generator 112 and negative (negative) control timing generator 112) and drive non-overlap control circuits (e.g., circuits 116 and 118). In other words, the present embodiment utilizes the forward control timing generator 112, the driving non-overlap control circuit 116 and the forward driving stage circuit 122 to detect the signal change condition when the polarity of the input signal SPCM is positive; the negative control timing generator 114, the driving non-overlap control circuit 118 and the negative driving stage circuit 124 are used to detect the signal change when the polarity of the input signal SPCM is negative. In this embodiment, the positive driving stage circuit 122/the negative driving stage circuit 124, the driving non-overlap control circuits 116/118, and the positive driving stage circuit 122/the negative driving stage circuit 124 are used together to obtain the signal change condition of the input signal SPCM at the positive and negative polarities. Depending on the requirement, the present embodiment can use only the positive control timing generator 112, the driving non-overlap control circuit 116 and the positive driving stage circuit 122 to obtain the signal change condition of the input signal SPCM at the positive polarity, or use the negative control timing generator 114, the driving non-overlap control circuit 118 and the negative driving stage circuit 124 to obtain the signal change condition of the input signal SPCM at the negative polarity. The positive control timing generator 112 and the negative control timing generator 112 receive the clock signal CLK.

FIG. 2 is a timing diagram of the relevant signals in the positive control timing generator 112 and the negative control timing generator 112 of FIG. 1. Inverted reference signal in fig. 2

Is the inverse of reference signal Sref. The forward control timing generator 112 generates a signal SCP by the reference signal Sref and the input signal SPCM; the negative control timing generator 114 passes the negative reference signal

And the input signal SPCM generates the signal SCN. This exampleThe signal SCP and the signal SCN both conform to the pulse width modulation type. When the reference signal is inverted, as shown by the period T1 in FIG. 2

When greater than the input signal SPCM, the signal SCN is logic "0"; when the reference signal is reversed

When the input signal SPCM is not more than the predetermined value, the signal SCN is logic "1". The longer the period of time when the signal SCN is logic "0", the larger the voltage amplitude of the input signal SPCM indicating the negative polarity (i.e., the absolute value of the voltage value of the input signal SPCM) is. As shown in a period T2 in fig. 2, when the reference signal Sref is greater than the input signal SPCM, the signal SCP is logic "1"; when the reference signal Sref is smaller than the input signal SPCM, the signal SCP is logic "0". The longer the period of time when the signal SCP is logic "0", the larger the voltage amplitude of the input signal SPCM indicating a positive polarity. Based on the related art of pwm, the present embodiment can obtain the signal change and amplitude of the input signal SPCM at the positive and negative poles by controlling the timing generator 112 positively and negatively.

Since the driving stage circuit 120 of fig. 1 usually employs transistors (e.g., MP1, MP2, MN1, MN 2) to implement the driving switches, the inherent characteristics of the transistors cannot be turned on or off instantly. If the transistors MP1 and MN1 are turned on simultaneously, electromagnetic interference (EMI), burning of the driving stage circuit 120 and/or the load circuit 130, and other related problems affecting the system stability of the electronic device 100 may be caused. Therefore, the present embodiment can prevent the transistors MP1 and MN1 in the positive driving stage circuit 122 from being turned on simultaneously or the transistors MP2 and MN2 in the negative driving stage circuit 122 from being turned on simultaneously by driving the

non-overlapping control circuits

116 and 118 to make the start-up periods of the control signals (e.g., SCP1 and SCP2, SCN1 and SCN 2) not overlap with each other.

Fig. 3A is a circuit diagram and a timing diagram of the driving non-overlap control circuit 116 of fig. 1. Fig. 3B is a circuit diagram and timing diagram of the driving non-overlap control circuit 118 of fig. 1. The driving non-overlap control circuit 116 and the driving non-overlap control circuit 118 of the present embodiment are both composed of two OR gates and two Delay elements. However, the present embodiment should be able to utilize other different circuit structures to further implement the driving of the

non-overlapping control circuits

116 and 118, and should not be limited to the disclosure of fig. 3A and 3B. The control signal SCP1 and the control signal SCP2 respectively control the conduction states of the P-type transistor MP1 and the N-type transistor MN1 in the forward driving stage circuit 122; the control signals SCN1 and SCN2 control the conduction states of the P-type transistor MP2 and the N-type transistor MN2 in the negative driving stage circuit 124, respectively.

Referring to fig. 3A, the activation period (i.e., the period of logic "0") of the control signal SCP1 and the activation period (i.e., the period of logic "1") of the control signal SCP2 in the right waveform diagram do not overlap with each other. The non-overlapping control circuit 116 of fig. 3A delays by an alert zone period GZP at a time point TP1 when the control signal SCP1 is converted from the off period (period of logic "1") to the on period (period of logic "0") and also delays by an alert zone period GZP at a time point TP2 when the control signal SCP2 is converted from the off period (period of logic "0") to the on period (period of logic "1"). The guard zone period GZP is also referred to as a period in which the two control signals SCP1 and SCP2 do not overlap each other when activated.

Referring to fig. 3B, the activation period of the control signal SCN1 (i.e., the period of logic "0") and the activation period of the control signal SCN2 (i.e., the period of logic "1") in the right waveform diagram do not overlap with each other. The non-overlap control circuit 118 of fig. 3B delays by one guard zone period GZP at a time point TN1 when the control signal SCN1 is switched from the off period (period of logic "1") to the on period (period of logic "0") and also delays by one guard zone period GZP at a time point TN2 when the control signal SCN2 is switched from the off period (period of logic "0") to the on period (period of logic "1"). The guard zone time period GZP is also referred to as a time period in which the two control signals SCP1 and SCP2 do not overlap each other at the time of activation.

In other words, the action of delaying one of the two control signals SCP1 and SCP2 by one guard zone period GZP is realized by the drive non-overlapping control circuit 116 in the control circuit 110; the action of delaying one of the two control signals SCN1 and SCN2 by one guard zone period GZP is realized by the drive non-overlapping control circuit 118 in the control circuit 110. The guard period GZP can be obtained by empirical rule, circuit simulation, etc., and the guard period GZP is set by two cycles of the clock signal CLK.

Returning to fig. 1, the driving

non-overlap control circuits

116 and 118, while avoiding the problem of simultaneous conduction of the driving switches in the driving stage circuit 120, reduce the signal-to-noise ratio (SNR) of the load circuit 130 near the zero point (i.e., the point in time when the input signal is switched in polarity). Fig. 4 is a signal-to-noise ratio diagram of the load circuit 130 of the electronic device 100. The horizontal axis of fig. 4 represents the value vsplcm of the input signal SPCM, and the horizontal axis of fig. 4 represents the power P obtained by the load circuit. Ideally, the snr of the load circuit 130 should be the same as the line L1 without power consumption. However, since the control circuit 110 in fig. 1 delays one of the two control signals, the actual signal-to-noise ratio appears as shown by line L2. In other words, as the value VSPCM of the input signal SPCM approaches 0, the power Pi is dissipated due to the delayed guard band period GZP, which is referred to as zero-cross distortion. If the electronic device 100 is applied to an audio device or a motor driving device requiring fine operation, the low-amplitude input signal cannot be applied to the load circuit 130, thereby losing the effect of the fine operation.

Therefore, in order to compensate for the above-mentioned zero-cross distortion, the embodiment of the present invention first uses a pre-offset circuit to increase or decrease the voltage of the input signal by a predetermined offset value according to the polarity (e.g., positive signal and negative signal) of the input signal to generate the pre-offset input signal. The predetermined offset value is associated with a time period (i.e., the guard zone time period GZP) during which two control signals generated by the control circuit are not overlapped with each other during the activation. Then, when the pre-offset input signal passes through the control circuit to generate the control signal of the driving stage circuit, the control circuit delays one of the at least two control signals so that the starting time periods of the at least two control signals do not overlap with each other, so that the pre-offset operation of the input signal can compensate the influence of zero-cross distortion generated by the control circuit delaying the control signal, and the signal-to-noise ratio (SNR) of the electronic device near the zero point is increased. On the other hand, although the voltage of the input signal is increased or decreased in advance, since the effect exhibited by the input signal at the maximum positive voltage value/the minimum negative voltage value does not have a large difference in the requirement of fine operation (e.g., maximum audio output, maximum power motor operation), the voltage input range of the input signal SPCM is not actually impaired by the embodiment of the present invention.

Fig. 5 is a block diagram of an electronic device 500 according to an embodiment of the invention. The main difference between fig. 1 and fig. 5 is that fig. 5 mainly adds a pre-offset circuit 560 additionally. The pre-skew circuit 560 takes the input signal SPCM to generate the pre-skew input signal PS. In detail, the pre-offset circuit 560 adjusts the input signal SPCM according to a polarity of the input signal SPCM (e.g., a positive signal with a positive sign bit or a negative signal with a negative sign bit) and a pre-offset value PBV to generate the pre-offset input signal PS. When the input signal SPCM is a positive value, increasing the voltage of the input signal SPCM by a preset offset value PBV to generate a pre-offset input signal PS; when the input signal SPCM is negative, the voltage of the input signal SPCM is decreased by the preset offset value PBV to generate the pre-offset input signal PS.

The predetermined offset value PBV is associated with the control signals (SCP 1 and SCP2, SCN1 and SCN 2) during the non-overlapping time periods (i.e., the guard zone time period GZP) at the time of activation. The embodiment of the present invention can obtain the predetermined offset value PBV in various ways, and three are listed below. In a first manner similar to the obtaining manner of the guard zone time period GZP, the preset offset value PBV in the embodiment can be obtained by an empirical rule, a circuit simulation, and the like, and is set for the electronic device 500 before factory shipment. When the time period GZP of the warning area is longer, the voltage value of the preset deviation value PBV is larger; when the time period GZP of the alert zone is shorter, the voltage value of the preset offset value PBV becomes smaller. A second way to obtain the preset offset value PBV is to interpret the length of the guard zone time period GZP by the feedback circuit 570 in advance through the signal SCP and the control signal SCP1 (or the control signal SCP 2) when the electronic device 500 performs the initialization operation, and calculate the required preset offset value PBV by using the interpreted guard zone time period GZP, so as to provide the preset offset value PBV for the pre-offset circuit 560. The feedback circuit 570 can also interpret the length of the alert zone period GZP by the signal SCN and the control signal SCN1 (or the control signal SCN 2). A third way to obtain the preset offset value PBV is that the feedback circuit 570 can dynamically interpret the length of the guard zone time period GZP through the signal SCP and the control signal SCP1 (or the control signal SCP 2), and calculate the required preset offset value PBV by using the interpreted guard zone time period GZP, so as to provide the preset offset value PBV to the pre-offset circuit 560 for use.

FIG. 6 is a block diagram of the pre-shifting circuit 560 of FIG. 5. Referring to fig. 6, the pre-shift circuit 560 mainly includes a signal polarity analyzer 610 and an input signal adjusting circuit 620. The signal polarity parser 610 is used for analyzing the polarity of the input signal SPCM to obtain the sign bit signal SB. For example, when the input signal SPCM is positive, the polarity of the input signal SPCM is positive, and the sign bit signal SB is represented as positive; when the input signal SPCM is negative, the polarity of the input signal SPCM is negative, and the sign signal SB is expressed as negative. The input signal adjusting circuit 620 is coupled to the signal polarity parser 610, and the input signal adjusting circuit 620 adjusts the input signal SPCM according to the sign bit signal SB. When the sign bit signal SB indicates that the input signal SPCM is a positive value, the input signal adjusting circuit 620 increases the voltage of the input signal SPCM by the preset offset value PBV. When the sign bit signal SB indicates that the input signal SPCM is negative, the input signal adjusting circuit 620 decreases the voltage of the input signal SPCM by the preset offset value PBV.

The input signal adjustment circuit 620 may include a multiplier 622, a sign switch 624, and an adder 626. The multiplier 622 generates a negative default offset value according to the default offset value PBV

That is, the multiplier 622 multiplies the preset offset value PBV by the value "-1" to obtain the preset offset value

The sign switch 624 is coupled to the signal polarity parser 610 and the multiplier 622. A first input terminal of the sign switch 624 receives the predetermined offset value PBV, and a second input terminal of the sign switch 624 receives the negative predetermined offset value PBV

The sign switch 624 selectively couples the first input terminal or the second input terminal thereof to the output terminal of the sign switch 624 according to the sign bit signal SB. A first input of adder 626 receives input signal SPCM, a second input of adder 626 is coupled to the output of sign switch 624, and adder 626 adds input signal SPCM to the output voltage of the output of sign switch 624 to generate pre-offset input signal PS. When the sign bit signal SB indicates that the input signal SPCM is positive, the sign switch 624 couples the first input terminal thereof to the output terminal of the sign switch 624, so that the voltage of the input signal SPCM is increased by the preset offset value PBV. The sign switch 624 couples its second input terminal to the sign switch when the sign bit signal SB indicates that the input signal SPCM is negative

The output terminal of the switch 624 is turned on to increase the voltage of the input signal SPCM by a predetermined negative offset value

(i.e., reducing the preset offset value PBV).

The pre-offset circuit 560 may also include a signal saturation clipper 630. The signal saturation clipper 630 is coupled to the output terminal of the input signal adjusting circuit 620. The signal saturation clipper 630 is used to avoid the pre-offset input signal PS from exceeding/falling below the preset maximum voltage value/the preset minimum voltage value of the control circuit 110 due to the excessive/insufficient voltage. When the voltage of the pre-biased input signal PS is greater than the predetermined maximum voltage value, the signal saturation clipper 630 adjusts the voltage of the pre-biased input signal PS to be equal to the predetermined maximum voltage value, thereby preventing the voltage of the pre-biased input signal PS from being too large. In contrast, when the voltage of the pre-shift input signal PS is smaller than the predetermined minimum voltage value, the signal saturation clipper 630 adjusts the voltage of the pre-shift input signal PS to be equal to the predetermined minimum voltage value, so as to prevent the voltage of the pre-shift input signal PS from being too small.

FIG. 7 is a diagram illustrating a comparison between the value VPS of the pre-shifted input signal PS and the value VSPCM of the input signal SPCM according to an embodiment of the present invention. The horizontal axis of fig. 7 represents the value vsplcm of the input signal SPCM; the vertical axis of fig. 7 represents the value VPS of the pre-shifted input signal PS. Line L3 represents the transition between the VSPCM and VPS values, and line L4 is the same reference line for both VSPCM and VPS values. As can be seen from fig. 7, when the value VSPCM of the input signal SPCM is a positive value, the value VPS of the pre-offset input signal PS is higher than the value VSPCM of the input signal SPCM by the preset offset value PBV; when the value VSPCM of the input signal SPCM is negative, the value VPS of the pre-offset input signal PS is lower than the value VSPCM of the input signal SPCM by the preset offset value PBV. In this way, the snr of the load circuit 130 of the electronic device 500 can be returned from the line L2 in fig. 4 to the line L1 through the compensation of the embodiment of the invention.

In summary, the electronic device and the compensation method of zero-cross distortion described in the present invention first utilize the pre-offset circuit to increase or decrease the voltage of the input signal by a pre-offset value according to the polarity (e.g., positive signal and negative signal) of the input signal to generate the pre-offset input signal, where the pre-offset value is related to a non-overlap period (this period may be referred to as an alert region) when the two control signals generated by the control circuit are activated. Then, when the pre-offset input signal passes through the control circuit to generate the control signal of the driving stage circuit, since the control circuit delays one of the at least two control signals so that the start periods of the at least two control signals do not overlap with each other, the pre-offset operation of the input signal can compensate the influence of zero-cross distortion generated by the control circuit delaying the control signal, and increase the signal-to-noise ratio (SNR) of the electronic device near the zero point (i.e., the time point when the input signal switches polarity).

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device, comprising:

a pre-offset circuit obtaining an input signal to generate a pre-offset input signal;

a control circuit, coupled to the pre-shift circuit, for receiving and comparing the pre-shift input signal and a reference signal to generate at least two control signals, wherein the control circuit delays one of the at least two control signals such that start-up periods between the at least two control signals do not overlap with each other;

the driving stage circuit is coupled with the control circuit and comprises at least two driving switches, and the at least two driving switches determine the conducting states of the at least two driving switches according to the at least two control signals respectively; and

a load circuit coupled to the at least two driving switches of the driving stage circuit and driven according to the conducting states of the at least two driving switches,

the pre-offset circuit adjusts the input signal according to the polarity of the input signal and a preset offset value to generate the pre-offset input signal, wherein the preset offset value is related to a time period when the at least two control signals are not overlapped with each other in starting.

2. The electronic device of claim 1, wherein the pre-offset circuit comprises:

a signal polarity parser for analyzing a polarity of the input signal to obtain a sign bit signal; and

an input signal adjusting circuit for adjusting the input signal according to the sign bit signal,

wherein the input signal adjusting circuit increases the voltage of the input signal by the preset offset value when the sign bit signal indicates that the input signal is a positive value,

when the sign bit signal indicates that the input signal is a negative value, the input signal adjusting circuit reduces the voltage of the input signal by the preset offset value.

3. The electronic device of claim 2, wherein the input signal conditioning circuit comprises:

a multiplier for generating a negative preset offset value according to the preset offset value;

a sign switch coupled to the signal polarity parser and the multiplier, a first input of the sign switch receiving the preset offset value, a second input of the sign switch receiving the negative preset offset value, the sign switch selectively coupling the first input or the second input to an output of the sign switch according to the sign bit signal; and

an adder having a first input receiving the input signal, a second input coupled to the output of the sign switch, the adder adding the input signal and an output voltage of the output of the sign switch to produce the pre-offset input signal,

wherein the sign switch couples the first input thereof to the output of the sign switch when the sign bit signal indicates that the input signal is positive, the adder adding the input signal by the pre-determined offset value to generate the pre-offset input signal,

when the sign bit signal indicates that the input signal is a negative value, the sign switch couples the second input terminal thereof to the output terminal of the sign switch, and the adder reduces the input signal by the negative preset offset value to generate the pre-offset input signal.

4. The electronic device of claim 3, wherein the input signal conditioning circuit further comprises:

a signal saturation clipper coupled to the output end of the input signal adjusting circuit,

when the voltage of the pre-excursion input signal is larger than a preset maximum voltage value, the signal saturation clipper adjusts the voltage of the pre-excursion input signal to be equal to the preset maximum voltage value,

when the voltage of the pre-excursion input signal is smaller than a preset minimum voltage value, the signal saturation clipper adjusts the voltage of the pre-excursion input signal to be equal to the preset minimum voltage value.

5. The electronic device of claim 1, further comprising:

the feedback circuit is coupled with the output end of the control circuit, judges the time intervals of the at least two control signals which are not overlapped with each other when being started according to the at least two control signals, and sets the preset deviation value according to the time intervals.

6. The electronic device of claim 1, wherein the preset offset value is set before the electronic device is shipped.

7. The electronic device of claim 1, wherein the input signal corresponds to pulse code modulation, the at least two control signals correspond to pulse width modulation, and the reference signal is a triangular waveform signal or a sawtooth waveform signal.

8. A method for compensating for zero-cross-over distortion, the method being suitable for an electronic device including a load circuit, the method comprising:

adjusting the input signal according to the polarity of the input signal and a preset offset value to generate a preset offset input signal;

comparing the pre-offset input signal and a reference signal to generate at least two control signals, wherein one of the at least two control signals is delayed so that the start-up periods between the at least two control signals do not overlap with each other; and

driving the load circuit in dependence on the conductive state of at least two drive switches of the load circuit,

wherein the preset offset value is related to a time period when the at least two control signals are not overlapped with each other in starting.

9. The compensation method as claimed in claim 8, wherein adjusting the input signal according to the polarity of the input signal and the predetermined offset value to generate the pre-offset input signal comprises:

analyzing the polarity of the input signal to obtain a sign bit signal;

when the sign bit signal indicates that the input signal is a positive value, increasing the voltage of the input signal by the preset offset value; and

and when the sign bit signal indicates that the input signal is a negative value, reducing the voltage of the input signal by the preset offset value.

10. The compensation method as claimed in claim 9, wherein adjusting the input signal according to the polarity of the input signal and the predetermined offset value to generate the pre-offset input signal further comprises:

when the voltage of the pre-deviation input signal is larger than a preset maximum voltage value, adjusting the voltage of the pre-deviation input signal to be equal to the preset maximum voltage value; and

when the voltage of the pre-excursion input signal is smaller than a preset minimum voltage value, the voltage of the pre-excursion input signal is adjusted to be equal to the preset minimum voltage value.

11. The compensation method of claim 8, further comprising:

and judging the time intervals of the at least two control signals which are not overlapped with each other when the at least two control signals are started according to the at least two control signals, and setting the preset deviation value according to the time intervals.

12. The compensation method of claim 8, wherein the input signal corresponds to pulse code modulation, the at least two control signals correspond to pulse width modulation, and the reference signal is a triangular waveform signal or a sawtooth waveform signal.