JP2008205420A - Flat panel display wiring and electrode using tft transistor that scarcely generates thermal defect and is excellent in surface state, and sputtering target for forming the same - Google Patents
Flat panel display wiring and electrode using tft transistor that scarcely generates thermal defect and is excellent in surface state, and sputtering target for forming the same Download PDFInfo
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- 230000007547 defect Effects 0.000 title claims abstract description 18
- 238000005477 sputtering target Methods 0.000 title claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 51
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims abstract description 21
- 239000000203 mixture Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052709 silver Inorganic materials 0.000 abstract description 5
- 229910052791 calcium Inorganic materials 0.000 abstract description 4
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 abstract 1
- 239000011575 calcium Substances 0.000 abstract 1
- 239000004332 silver Substances 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 12
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000003746 surface roughness Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000005098 hot rolling Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005097 cold rolling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
Description
この発明は、ヒロックおよびボイドなどの熱欠陥の発生がなくかつ表面状態の良好な銅合金薄膜からなるＴＦＴトランジスターを用いたフラットパネルディスプレイ用配線および電極、並びにそれらを形成するためのスパッタリングターゲットに関するものである。 The present invention relates to a flat panel display wiring and electrodes using a TFT transistor made of a copper alloy thin film having a good surface state without generation of thermal defects such as hillocks and voids, and a sputtering target for forming them. It is.
アクティブマトリックス方式で駆動するＴＦＴトランジスターを用いたフラットパネルディスプレイとして、液晶ディスプレイ、プラズマディスプレイ、有機ＥＬディスプレイ、無機ＥＬディスプレイなどが知られている。これらＴＦＴトランジスターを用いたフラットパネルディスプレイにはガラス基板表面に格子状に金属薄膜からなる配線が密着して形成されており、この金属薄膜からなる格子状配線の交差点にＴＦＴトランジスターが設けられていて、このＴＦＴトランジスターのゲート電極も金属薄膜で形成されている。
これらＴＦＴトランジスターを用いたフラットパネルディスプレイを製造する際に、アモルファスシリコンや窒化珪素等をＰＥＣＶＤで成膜する工程を通過するが、その際にガラス基板表面に形成された金属薄膜からなる配線および電極は熱履歴を受ける。
前記金属薄膜からなる配線および電極が純銅薄膜で構成されていると、前記熱履歴を受ける工程で純銅薄膜で構成されている配線および電極は高温に曝されてヒロックおよびボイドなどの熱欠陥が発生する。これを解決するために、近年、ＴＦＴトランジスターを用いたフラットパネルディスプレイの配線および電極に銅合金薄膜が使用されるようになり、この銅合金薄膜の一つとしてＣａ：０．１〜３０原子％を含有し、残部がＣｕからなる銅合金薄膜が使用されている（特許文献１参照）。
When manufacturing a flat panel display using these TFT transistors, a process of forming a film of amorphous silicon, silicon nitride or the like by PECVD is performed. At that time, wiring and electrodes made of a metal thin film formed on the surface of the glass substrate Receives a heat history.
When the wiring and electrodes made of the metal thin film are made of pure copper thin film, the wiring and the electrode made of the pure copper thin film are exposed to high temperatures in the process of receiving the thermal history, and thermal defects such as hillocks and voids are generated. To do. In order to solve this, in recent years, copper alloy thin films have been used for wiring and electrodes of flat panel displays using TFT transistors. As one of these copper alloy thin films, Ca: 0.1 to 30 atomic% A copper alloy thin film containing Cu and the balance being Cu is used (see Patent Document 1).
前記Ｃａ：０．１〜３０原子％を含有し、残部がＣｕからなる銅合金薄膜は、確かにＴＦＴトランジスターを用いたフラットパネルディスプレイ製造中の熱履歴を受ける工程で高温に曝されてもヒロックおよびボイドなどの熱欠陥の発生が阻止される。しかし、Ｃａを０．１〜３０原子％含有する銅合金薄膜は比抵抗値が上昇しその表面が荒れるという欠点があった。かかる比抵抗値が上昇した表面が荒れた銅合金薄膜を５０インチ以上の大型液晶パネルなどの配線として使用すると、ガラス基板表面に形成されている配線が従来よりも益々長くかつ細くなってきていることから大型液晶パネル全体の配線を形成する工程で切断部分が発生しやすく、さらに大型液晶パネル全体の配線の電気抵抗が上昇するようになるので好ましくない。 The copper alloy thin film containing Ca: 0.1 to 30 atomic% and the balance being Cu is certainly hillock even if it is exposed to high temperature in the process of receiving a thermal history during the manufacture of flat panel displays using TFT transistors. And generation of thermal defects such as voids are prevented. However, a copper alloy thin film containing 0.1 to 30 atomic% of Ca has a drawback that the specific resistance value increases and the surface becomes rough. When such a copper alloy thin film with a rough surface with an increased specific resistance value is used as a wiring for a large liquid crystal panel of 50 inches or more, the wiring formed on the surface of the glass substrate is becoming longer and thinner than before. For this reason, a cut portion is likely to be generated in the process of forming the wiring of the entire large liquid crystal panel, and the electric resistance of the wiring of the entire large liquid crystal panel is increased, which is not preferable.
そこで、本発明者等は、比抵抗値が低く、さらに高温に曝されてもヒロックおよびボイドなどの熱欠陥の発生が極めて少なくかつ表面状態の良好な銅合金薄膜を開発し、これをＴＦＴトランジスターを用いたフラットパネルディスプレイにおける配線および電極に適用すべく研究を行った。その結果、
（イ）純銅（特に純度：９９．９９％以上の無酸素銅）に含まれるＣａ量を少なくしてＣａ：０．００１〜０．５原子％となるようにし、さらにＡｇを０．００２〜１．０原子％を含有した成分組成を有する銅合金薄膜は、従来のＣａ：０．１〜３０原子％を単独で含有する銅合金薄膜に比べて、比抵抗値が一層低く、高温に曝されてもヒロックおよびボイドの熱欠陥が発生することが一層少なく、さらに表面荒れが一層少なくなる、
（ロ）前記（イ）記載の銅合金薄膜は、前記銅合金薄膜よりも多くのＣａおよびＡｇを含む組成を有するターゲットを用いてスパッタリングすることにより形成することができ、ターゲットに含まれるＣａおよびＡｇは、Ｃａ：０．０１〜３原子％、Ａｇ：０．０１〜４原子％であることが好ましい、などの研究結果が得られたのである。
Therefore, the present inventors have developed a copper alloy thin film having a low specific resistance value, a very low occurrence of thermal defects such as hillocks and voids even when exposed to high temperatures, and a good surface state. The research was conducted to apply to wiring and electrodes in flat panel displays using the LCD. as a result,
(A) The amount of Ca contained in pure copper (especially purity: 99.99% or more oxygen-free copper) is reduced so as to be Ca: 0.001 to 0.5 atomic%, and further Ag is 0.002 to 0.002. The copper alloy thin film having a component composition containing 1.0 atomic% has a lower specific resistance value than that of a conventional copper alloy thin film containing Ca: 0.1 to 30 atomic% alone, and is exposed to a high temperature. Hillock and void thermal defects are less likely to occur, and surface roughness is further reduced.
(B) The copper alloy thin film described in (a) can be formed by sputtering using a target having a composition containing more Ca and Ag than the copper alloy thin film, and the Ca and Research results such as Ag being preferably Ca: 0.01 to 3 atomic% and Ag: 0.01 to 4 atomic% were obtained.
この発明は、かかる研究結果に基づいてなされたものであって、
（１）Ｃａ：０．００１〜０．５原子％を含有し、さらにＡｇ：０．００２〜１．０原子％を含有し、残部がＣｕおよび不可避不純物からなる組成を有する銅合金薄膜からなる熱欠陥発生がなくかつ表面状態の良好なＴＦＴトランジスターを用いたフラットパネルディスプレイ用配線、
（２）Ｃａ：０．００１〜０．５原子％を含有し、さらにＡｇ：０．００２〜１．０原子％を含有し、残部がＣｕおよび不可避不純物からなる組成を有する銅合金薄膜からなる熱欠陥発生がなくかつ表面状態の良好なＴＦＴトランジスターを用いたフラットパネルディスプレイ用電極、
（３）Ｃａ：０．０１〜３原子％を含有し、さらにＡｇ：０．０１〜４原子％を含有し、残部がＣｕおよび不可避不純物からなる組成を有する熱欠陥発生がなくかつ表面状態の良好なＴＦＴトランジスターを用いたフラットパネルディスプレイ用配線または電極を形成するためのスパッタリングターゲット、に特徴を有するものである。
The present invention has been made based on the results of such research,
(1) Ca: 0.001 to 0.5 atomic%, further Ag: 0.002 to 1.0 atomic%, with the balance being a copper alloy thin film having a composition consisting of Cu and inevitable impurities Flat panel display wiring using TFT transistors with good surface condition and no thermal defects
(2) Ca: 0.001 to 0.5 atomic%, further Ag: 0.002 to 1.0 atomic%, with the balance being a copper alloy thin film having a composition consisting of Cu and inevitable impurities Flat panel display electrode using TFT transistors with good surface condition and no thermal defects,
(3) Ca: 0.01 to 3 atomic%, further Ag: 0.01 to 4 atomic%, with the balance being composed of Cu and unavoidable impurities, no generation of thermal defects and surface condition It is characterized by a sputtering target for forming a wiring or electrode for a flat panel display using a good TFT transistor.
この発明のＴＦＴトランジスターを用いたフラットパネルディスプレイの配線および電極を構成する銅合金薄膜は、ターゲットを用いてスパッタリングすることにより作製する。このターゲットは、まず純度：９９．９９％以上の無酸素銅を、不活性ガス雰囲気中、高純度グラファイトモールド内で高周波溶解し、得られた溶湯にＣａを０．０１〜３原子％を添加し、さらにＡｇを０．０１〜４原子％を添加して溶解し、得られた溶湯を不活性ガス雰囲気中で鋳造し急冷凝固させたのち、さらに熱間圧延し、最後に歪取り焼鈍を施すことにより作製する。このようにして得られたターゲットをバッキングプレートに接合し、通常の条件でスパッタリングすることによりこの発明のＴＦＴトランジスターを用いたフラットパネルディスプレイにおける配線および電極用銅合金薄膜を形成することができる。 The copper alloy thin film which comprises the wiring and electrode of a flat panel display using the TFT transistor of this invention is produced by sputtering using a target. In this target, oxygen-free copper having a purity of 99.99% or higher is first melted in a high-purity graphite mold in an inert gas atmosphere, and 0.01 to 3 atomic% of Ca is added to the resulting molten metal. Further, 0.01 to 4 atomic% of Ag is added and melted, and the resulting molten metal is cast in an inert gas atmosphere and rapidly solidified, then further hot-rolled and finally subjected to strain relief annealing. It is produced by applying. By bonding the target thus obtained to a backing plate and sputtering under normal conditions, it is possible to form a copper alloy thin film for wiring and electrodes in a flat panel display using the TFT transistor of the present invention.
次に、この発明のＴＦＴトランジスターを用いたフラットパネルディスプレイにおける配線および電極を構成する銅合金薄膜およびターゲットの成分組成の限定理由を説明する。 Next, the reasons for limiting the component composition of the copper alloy thin film and the target constituting the wiring and electrodes in the flat panel display using the TFT transistor of the present invention will be described.
（ａ）銅合金薄膜の成分組成
Ｃａ：
Ｃａはガラスやシリコンとの密着性を改善する作用を有するが、その含有量が０．００１原子％未満では十分な密着性改善効果が得られないので好ましくなく、一方、０．５原子％を越えて含むと、比抵抗値が上昇しさらに表面荒れが発生するようになるので好ましくない。したがって、Ｃａ含有量を０．００１〜０．５原子％に定めた。
Ａｇ：
ＡｇはＣａと共に添加することにより比抵抗値の上昇を抑制すると共にＣａのヒロックおよびボイドなどの熱欠陥発生防止効果を一層強化しかつ表面状態が荒れるのを抑制する効果があるが、その含有量が０．００２原子％未満では十分な比抵抗上昇阻止効果および熱欠陥発生防止効果を強化することができずさらに表面荒れを防止することができない。一方、Ａｇを１．０原子％を越えて含有してもヒロックおよびボイドなどの熱欠陥発生防止効果は強化せず、コストアップを招くので好ましくない。したがって、Ａｇの含有量を０．００２〜１．０原子％に定めた。
(A) Component composition Ca of the copper alloy thin film:
Ca has the effect of improving the adhesion to glass and silicon, but if its content is less than 0.001 atomic%, it is not preferable because a sufficient adhesion improving effect cannot be obtained. If it is included in excess, the specific resistance value increases and surface roughness occurs, which is not preferable. Therefore, the Ca content is set to 0.001 to 0.5 atomic%.
Ag:
Addition of Ag together with Ca suppresses an increase in specific resistance and further enhances the effect of preventing the occurrence of thermal defects such as hillocks and voids of Ca and suppresses the roughening of the surface state. However, if it is less than 0.002 atomic%, it is not possible to enhance the effect of preventing the increase in specific resistance and the effect of preventing the occurrence of thermal defects, and further it is impossible to prevent surface roughness. On the other hand, if Ag is contained in excess of 1.0 atomic%, the effect of preventing the occurrence of thermal defects such as hillocks and voids is not enhanced, leading to an increase in cost. Therefore, the content of Ag is set to 0.002 to 1.0 atomic%.
（ｂ）ターゲットの成分組成
スパッタリングすることにより成膜して得られる銅合金薄膜のＣａ量を０．００１〜０．５原子％とするためには、ターゲットに含まれるＣａ量を０．０１〜３原子％とすることが必要であるからである。また、スパッタリングすることにより成膜して得られる銅合金薄膜のＡｇ量を０．００２〜１．０原子％とするためには、ターゲットに含まれるＡｇ量を０．０１〜４原子％とすることが必要であるからであり、さらにＡｇを４原子％より多く含むとターゲットの熱間圧延加工中に割れが発生するので好ましくないからである。
(B) Component composition of target In order to set the Ca content of a copper alloy thin film obtained by sputtering to 0.001 to 0.5 atomic%, the amount of Ca contained in the target is set to 0.01 to It is because it is necessary to set it as 3 atomic%. Moreover, in order to make Ag amount of the copper alloy thin film obtained by film-forming by sputtering 0.002-1.0 atomic%, the amount of Ag contained in the target is 0.01-4 atomic%. This is because it is not preferable to contain more than 4 atomic% of Ag because cracking occurs during hot rolling of the target.
この発明のＴＦＴトランジスターを用いたフラットパネルディスプレイにおける配線および電極は、製造中に高温に曝されてもヒロックおよびボイドなどの熱欠陥の発生がなくまた表面荒れを抑制し、さらに電気抵抗が低いことから高精細化し大型化したＴＦＴトランジスターを用いたフラットパネルディスプレイの配線および電極に使用しても消費電力を少なくすることができるなど優れた効果を奏するものである。 Wiring and electrodes in a flat panel display using the TFT transistor of the present invention have no generation of thermal defects such as hillocks and voids even when exposed to high temperatures during production, and suppress surface roughness and have low electrical resistance. Even if it is used for wiring and electrodes of a flat panel display using a TFT transistor with high definition and increased size, excellent effects such as reduction in power consumption can be obtained.
純度：９９．９９質量％の無酸素銅を用意し、この無酸素銅をＡｒガス雰囲気中、高純度グラファイトモールド内で高周波溶解し、得られた溶湯にＣａおよびＡｇを添加し溶解して表１に示される成分組成を有する溶湯となるように成分調整し、得られた溶湯を冷却されたカーボン鋳型に鋳造し、さらに冷間圧延と焼鈍を繰り返したのち最終的に歪取り焼鈍し、得られた圧延体の表面を旋盤加工して外径：２００mm×厚さ：１０mmの寸法を有し、表１に示される成分組成を有する本発明銅合金スパッタリングターゲット（以下、本発明ターゲットという）１〜１５、比較銅合金スパッタリングターゲット（以下、比較ターゲットという）１〜２および従来スパッタリングターゲット（以下、従来ターゲットという）１〜２を作製した。
さらに、無酸素銅製バッキングプレートを用意し、この無酸素銅製バッキングプレートに前記本発明ターゲット１〜１５、比較ターゲット１〜２および従来ターゲット１〜２を重ね合わせ、温度：２００℃でインジウムはんだ付けすることにより本発明ターゲット１〜２０、比較ターゲット１〜２および従来ターゲット１〜２を無酸素銅製バッキングプレートに接合してバッキングプレート付きターゲットを作製した。
Purity: 99.99 mass% oxygen-free copper was prepared, this oxygen-free copper was melted at high frequency in an Ar gas atmosphere in a high-purity graphite mold, and Ca and Ag were added to the resulting molten metal and dissolved. Ingredient adjustment was performed to obtain a molten metal having the component composition shown in 1 and the obtained molten metal was cast into a cooled carbon mold, and after further cold rolling and annealing, finally subjected to strain relief annealing, A copper alloy sputtering target of the present invention (hereinafter referred to as the present invention target) 1 having a size of outer diameter: 200 mm × thickness: 10 mm and having the component composition shown in Table 1 by lathing the surface of the obtained rolled body -15, comparative copper alloy sputtering targets (hereinafter referred to as comparative targets) 1-2 and conventional sputtering targets (hereinafter referred to as conventional targets) 1-2 were prepared.
Furthermore, an oxygen-free copper backing plate is prepared, and the present invention targets 1 to 15, the comparative targets 1 to 2 and the conventional targets 1 to 2 are superposed on the oxygen-free copper backing plate, and indium soldered at a temperature of 200 ° C. Thus, the inventive targets 1 to 20, the comparative targets 1 and 2, and the conventional targets 1 to 2 were joined to an oxygen-free copper backing plate to prepare a target with a backing plate.
本発明ターゲット１〜１５、比較ターゲット１〜２および従来ターゲット１〜２を無酸素銅製バッキングプレートにはんだ付けして得られたバッキングプレート付きターゲットを、ターゲットとガラス基板（縦：５０ｍｍ、横：５０ｍｍ、厚さ：０．７ｍｍの寸法を有するコーニング社製１７３７のガラス基板）との距離：７０mmとなるようにセットし、
電源：直流方式、
スパッタパワー：６００Ｗ、
到達真空度：５×１０−５Ｐａ、
雰囲気ガス組成：Ａｒ、
Ａｒガス圧：０．６７Ｐａ、
ガラス基板加熱温度：１５０℃、
の条件でガラス基板の表面に、厚さ：３００ｎｍを有し、表２に示される成分組成を有する本発明銅合金配線用薄膜（以下、本発明配線用薄膜という）１〜１５および比較銅合金配線用薄膜（以下、比較配線用薄膜という）１〜２および従来銅合金配線用薄膜(以下、従来配線用薄膜という)１〜２を形成した。
A target with a backing plate obtained by soldering the present invention targets 1-15, comparative targets 1-2, and conventional targets 1-2 to an oxygen-free copper backing plate, a target and a glass substrate (length: 50 mm, width: 50 mm) , Thickness: 0.77 mm Corning 1737 glass substrate) and distance: 70 mm,
Power supply: DC method,
Sputter power: 600W
Ultimate vacuum: 5 × 10 −5 Pa,
Atmospheric gas composition: Ar,
Ar gas pressure: 0.67 Pa,
Glass substrate heating temperature: 150 ° C.
The present invention copper alloy wiring thin film (hereinafter referred to as the present invention thin film) 1-15 and comparative copper alloy having a thickness of 300 nm on the surface of the glass substrate and the component composition shown in Table 2 Thin films for wiring (hereinafter referred to as comparative wiring thin films) 1 and 2 and conventional copper alloy wiring thin films (hereinafter referred to as conventional wiring thin films) 1 and 2 were formed.
得られた本発明配線用薄膜１〜１５、比較配線用薄膜１〜２および従来配線用薄膜１〜２をそれぞれ赤外線加熱炉に装入し、到達真空度：４×１０−４Ｐａの真空雰囲気中、昇温速度：５℃／ｍｉｎ、最高温度：３５０℃、３０分間保持の熱処理を施した。これら熱処理を施した本発明配線用薄膜１〜１５、比較配線用薄膜１〜２および従来配線用薄膜１〜２の表面を１０００倍の光学顕微鏡で５個所の膜表面を観察し、発生したヒロックおよびボイドの個数を測定し、その結果を表２〜３に示した。
さらに、得られた本発明配線用薄膜１〜１５、比較配線用薄膜１〜２および従来配線用薄膜１〜２における５点の比抵抗を四探針法により測定し、その平均値を求め、それらの結果を表２〜３に示した。
さらに、ＡＦＭ（原子間力顕微鏡）で表面粗さを測定し、その結果を表２〜３に示し、熱処理による膜の表面荒れを評価した。
The obtained thin films 1 to 15 for the present invention, thin films 1 to 2 for comparative wiring, and thin films 1 to 2 for conventional wiring were respectively charged in an infrared heating furnace, and a vacuum atmosphere of 4 × 10 −4 Pa was reached. Medium, the temperature rising rate: 5 ° C./min, the maximum temperature: 350 ° C., and a heat treatment for 30 minutes were performed. The surface of the thin films for wiring 1 to 15 of the present invention, the thin films for comparative wiring 1 to 2 and the conventional thin films for wiring 1 to 2 subjected to these heat treatments were observed on five film surfaces with a 1000 × optical microscope, and hillocks were generated. The number of voids was measured, and the results are shown in Tables 2-3.
Furthermore, the specific resistance of 5 points in the obtained thin films for wiring 1 to 15 of the present invention, the thin films for comparative wiring 1 and 2 and the thin films for conventional wiring 1 and 2 was measured by the four-probe method, and the average value was obtained. The results are shown in Tables 2-3.
Furthermore, the surface roughness was measured with an AFM (Atomic Force Microscope), and the results are shown in Tables 2 to 3 to evaluate the surface roughness of the film by heat treatment.
表１〜３に示される結果から以下の事項が分かる。
（ｉ）Ｃａを単独で含む従来配線用薄膜１〜２に比べてＣａおよびＡｇを共に含む本発明配線用薄膜１〜１５はヒロックおよびボイドの発生が一層少なく、さらに比抵抗値が一層小さく、さらに熱処理によって表面状態の荒れが少ないことがわかる。
（ii）しかし、この発明の条件から外れて少ないＡｇを含む比較配線用薄膜１はヒロックおよびボイドの発生を阻止する効果が弱く、一方、Ａｇをこの発明の条件から外れて多く含む比較配線用薄膜２はターゲット製造工程の熱間圧延時に割れが発生してターゲットを作製することができないことが分かる。
The following items are understood from the results shown in Tables 1 to 3.
(I) Compared to the conventional thin films for wiring 1 and 2 containing Ca alone, the wiring thin films 1 to 15 of the present invention containing both Ca and Ag have less generation of hillocks and voids, and further have a smaller specific resistance value. Further, it can be seen that the heat treatment causes less surface roughness.
(Ii) However, the comparative wiring thin film 1 containing a small amount of Ag deviating from the conditions of the present invention has a weak effect of preventing the generation of hillocks and voids, whereas the comparative wiring thin film 1 containing a large amount of Ag deviating from the conditions of the present invention. It can be seen that the thin film 2 is cracked during hot rolling in the target manufacturing process, and the target cannot be produced.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010035463A1 (en) * | 2008-09-26 | 2010-04-01 | 三菱マテリアル株式会社 | Thin-film transistor and intermediate of thin-film transistor |
| WO2010047326A1 (en) * | 2008-10-24 | 2010-04-29 | 三菱マテリアル株式会社 | Method for manufacturing thin film transistor and thin film transistor |
| WO2010047040A1 (en) * | 2008-10-24 | 2010-04-29 | 三菱マテリアル株式会社 | Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films |
| WO2010103587A1 (en) * | 2009-03-11 | 2010-09-16 | 三菱マテリアル株式会社 | THIN FILM TRANSISTOR HAVING A BARRIER LAYER AS A CONSTITUTING LAYER AND Cu-ALLOY SPUTTERING TARGET USED FOR SPUTTER FILM FORMATION OF THE BARRIER LAYER |
| US20120119269A1 (en) * | 2009-06-12 | 2012-05-17 | Ulvac, Inc. | Method for producing electronic device, electronic device, semiconductor device, and transistor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003243325A (en) * | 2002-02-20 | 2003-08-29 | Mitsubishi Materials Corp | Sputtering target for forming copper alloy wiring film and copper alloy wiring film little affected by heat and formed by using the same |
| JP2003529206A (en) * | 1999-11-24 | 2003-09-30 | ハネウェル・インターナショナル・インコーポレーテッド | Physical vapor deposition targets, conductive integrated circuit metal alloy interconnects, electroplated anodes, metal alloys for use as conductive interconnects in integrated circuits |
| JP2004076080A (en) * | 2002-08-14 | 2004-03-11 | Tosoh Corp | Thin film for wiring and sputtering target |
| JP2004076079A (en) * | 2002-08-14 | 2004-03-11 | Tosoh Corp | Thin film for wiring and sputtering target |
| JP2005510875A (en) * | 2001-11-26 | 2005-04-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Using ternary copper alloy to obtain low resistance, large grain size wiring |
| JP2005533187A (en) * | 2002-07-16 | 2005-11-04 | ハネウェル・インターナショナル・インコーポレーテッド | Copper sputtering target and method of forming copper sputtering target |
| WO2006005095A1 (en) * | 2004-07-15 | 2006-01-19 | Plansee Se | Material for conductor tracks made of copper alloy |
-
2007
- 2007-05-07 JP JP2007122263A patent/JP5234306B2/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003529206A (en) * | 1999-11-24 | 2003-09-30 | ハネウェル・インターナショナル・インコーポレーテッド | Physical vapor deposition targets, conductive integrated circuit metal alloy interconnects, electroplated anodes, metal alloys for use as conductive interconnects in integrated circuits |
| JP2005510875A (en) * | 2001-11-26 | 2005-04-21 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Using ternary copper alloy to obtain low resistance, large grain size wiring |
| JP2003243325A (en) * | 2002-02-20 | 2003-08-29 | Mitsubishi Materials Corp | Sputtering target for forming copper alloy wiring film and copper alloy wiring film little affected by heat and formed by using the same |
| JP2005533187A (en) * | 2002-07-16 | 2005-11-04 | ハネウェル・インターナショナル・インコーポレーテッド | Copper sputtering target and method of forming copper sputtering target |
| JP2004076080A (en) * | 2002-08-14 | 2004-03-11 | Tosoh Corp | Thin film for wiring and sputtering target |
| JP2004076079A (en) * | 2002-08-14 | 2004-03-11 | Tosoh Corp | Thin film for wiring and sputtering target |
| WO2006005095A1 (en) * | 2004-07-15 | 2006-01-19 | Plansee Se | Material for conductor tracks made of copper alloy |
| JP2008506040A (en) * | 2004-07-15 | 2008-02-28 | プランゼー エスエー | Materials for conductive wires made from copper alloys |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010035463A1 (en) * | 2008-09-26 | 2010-04-01 | 三菱マテリアル株式会社 | Thin-film transistor and intermediate of thin-film transistor |
| JP2010080681A (en) * | 2008-09-26 | 2010-04-08 | Mitsubishi Materials Corp | Thin film transistor |
| US8502285B2 (en) * | 2008-09-26 | 2013-08-06 | Mitsubishi Materials Corporation | Thin-film transistor and intermediate of thin-film transistor |
| US20110133190A1 (en) * | 2008-09-26 | 2011-06-09 | Mitsubishi Materials Corporation | Thin-film transistor and intermediate of thin-film transistor |
| KR101527626B1 (en) * | 2008-09-26 | 2015-06-09 | 미쓰비시 마테리알 가부시키가이샤 | Thin-film transistor and intermediate of thin-film transistor |
| WO2010047040A1 (en) * | 2008-10-24 | 2010-04-29 | 三菱マテリアル株式会社 | Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films |
| JP2010103324A (en) * | 2008-10-24 | 2010-05-06 | Mitsubishi Materials Corp | Thin film transistor having high adhesive strength between barrier film and drain electrode and source electrode films |
| US8470651B2 (en) | 2008-10-24 | 2013-06-25 | Mitsubishi Materials Corporation | Method for producing a thin film transistor, and a thin film transistor |
| CN102197488A (en) * | 2008-10-24 | 2011-09-21 | 三菱综合材料株式会社 | Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films |
| KR101527625B1 (en) * | 2008-10-24 | 2015-06-09 | 미쓰비시 마테리알 가부시키가이샤 | Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films |
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| WO2010103587A1 (en) * | 2009-03-11 | 2010-09-16 | 三菱マテリアル株式会社 | THIN FILM TRANSISTOR HAVING A BARRIER LAYER AS A CONSTITUTING LAYER AND Cu-ALLOY SPUTTERING TARGET USED FOR SPUTTER FILM FORMATION OF THE BARRIER LAYER |
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| US8658009B2 (en) | 2009-03-11 | 2014-02-25 | Mitsubishi Materials Corporation | Thin film transistor having a barrier layer as a constituting layer and Cu-alloy sputtering target used for sputter film formation of the barrier layer |
| CN102349157B (en) * | 2009-03-11 | 2014-09-10 | 三菱综合材料株式会社 | Thin film transistor having a barrier layer as a constituting layer and cu-alloy sputtering target used for sputter film formation of the barrier layer |
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