JP2008205055A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having a high degree of element integration while using the same trench isolation as that of a high power supply voltage circuit section even in a low power supply voltage circuit section, and imparting sufficient latchup resistance to the high power supply voltage circuit section without increasing the process. <P>SOLUTION: In the semiconductor device with a trench isolation structure, at least one well region and an MOS transistor are formed in the high power supply voltage circuit section, majority carrier capturing regions 401, 402 and minority carrier capturing regions 403, 404 for preventing latchup are provided in the vicinity of the end of the well region, and the potentials are set, respectively, at a level suitable for carrier suction. The carrier capturing region is made deeper than the trench isolation region, and the minority carrier capturing region, the majority carrier capturing region, and the MOS transistor are arranged sequentially from the well end. The majority carrier capturing region and the minority carrier capturing region are formed of the same diffusion layer as that in the source or drain region of the MOS transistor formed in the high power supply voltage circuit section. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench isolation structure such as a CMOS device having multiple power supply voltages using trench isolation as an element isolation structure.

  In a semiconductor device having a CMOS device that uses multiple power supply voltages, the integration of the low power supply voltage part constituting the internal circuit such as a logic circuit is improved, and the high power supply voltage part used in the input / output circuit is latched up. It is important to ensure resistance. For element isolation, a trench isolation method suitable for higher integration than the LOCOS method is often adopted. However, in a semiconductor device in which element isolation is performed by trench isolation, sufficient latch-up resistance is provided for a high power supply voltage circuit section. In order to increase the well depth, it is necessary to suppress the parasitic bipolar operation by increasing the depth of the well, and to suppress the leakage current between the NMOS transistor and the PMOS transistor and to ensure the breakdown voltage characteristics, the isolation width of the trench isolation portion It was necessary to take big. For this reason, even in the low power supply voltage circuit section, when the same trench isolation as that of the high power supply voltage circuit section is used, there is a problem that the degree of integration of elements in the low power supply voltage section that requires high integration is lowered.

As an improvement measure, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, or the isolation width of the trench isolation section of the high power supply voltage circuit section is reduced. An example of making it wider than the trench isolation width has also been proposed. (For example, refer to Patent Document 1.)
JP 2000-58673 A

  However, in the semiconductor device using the multiple power supply voltage separated by trench isolation as described above, the well bipolar circuit is formed by increasing the well depth in order to give the high power supply voltage circuit portion sufficient latch-up resistance. It is necessary to suppress the operation, and it is necessary to increase the isolation width of the trench isolation portion in order to suppress the leakage current between the NMOS transistor and the PMOS transistor and to ensure the breakdown voltage characteristics. For this reason, in the low power supply voltage circuit section, if the same trench isolation as that of the high power supply voltage circuit section is used, the integration of elements in the low power supply voltage circuit section requiring high integration is reduced.

  Also, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, and the isolation width of the trench isolation section of the high power supply voltage circuit section is wider than that of the low power supply voltage circuit section. However, there are problems such as an increase in manufacturing steps and an increase in separation width, leading to an increase in cost.

  In order to solve the above problems, the present invention is configured as follows.

  A high power supply voltage circuit portion and a low power supply voltage circuit portion, and a trench isolation structure in which each element in the high power supply voltage circuit portion and the low power supply voltage circuit portion is isolated by a trench isolation region, In a semiconductor device in which at least one well region and a MOS transistor are formed in the voltage circuit section, the voltage circuit portion has a majority carrier capture region and a minority carrier capture region for preventing latch-up near the end of the well region. The potential of the majority carrier trapping region is the same as the potential of the well or semiconductor substrate in which the majority carrier trapping region is disposed, and the potential of the minority carrier trapping region is opposite to that of the well or semiconductor substrate in which the minority carrier trapping region is disposed. The potential of the well region or the semiconductor substrate was the same. The minority carrier region is disposed closer to the end of the well region than the majority carrier capture region, and the majority carrier capture region and the minority carrier capture region are formed deeper than the trench isolation region. did.

  In addition, the carrier trapping region formed in the high power supply voltage circuit unit is formed by the same diffusion layer as the source or drain region of the MOS transistor formed in the high power supply voltage circuit unit.

  As explained above, the same trench isolation is used in the low power supply voltage circuit section as in the high power supply voltage circuit section while providing sufficient latch-up resistance to the high power supply voltage circuit section without increasing the number of processes. A semiconductor device having a high degree of element integration can be obtained.

  FIG. 1 is a schematic cross-sectional view showing a first embodiment in a high power supply voltage circuit section of a semiconductor device according to the present invention.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. A well region 202 is formed adjacently. An N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, is formed on the surface of the P-well region 201, and an N-well region 202 is also formed. A P-type high-concentration impurity region 502 which is a source or drain region of a P-type MOS transistor, for example, is formed on the surface, and a trench isolation region 301 for isolating those elements is formed.

  In the P well region 201 near the junction between the P well region 201 and the N well region 202, a position closer to the junction between the P well region 201 and the N well region 202 than the N-type high concentration impurity region 501 is located. A part of the trench isolation region 301 is removed to form a majority carrier trap region 401 composed of a P-type high-concentration impurity region having a deeper depth than the trench isolation region 301, and the potential thereof is the same as that of the P well region 201. It is fixed to be. Further, at a position closer to the junction between the P well region 201 and the N well region 202 than the majority carrier trap region 401 made of a P-type high concentration impurity region in the P well region 201, a depth deeper than that of the trench isolation region 301. A minority carrier trap region 403 made of an N-type high-concentration impurity region is formed, and its potential is fixed to be the same as that of the N-well region 202.

  On the other hand, the position in the N well region 202 near the junction between the P well region 201 and the N well region 202 is closer to the junction between the P well region 201 and the N well region 202 than the P type high concentration impurity region 502. A part of the trench isolation region 301 is removed to form a majority carrier trap region 402 made of an N-type high concentration impurity region having a depth deeper than that of the trench isolation region 301, and the potential is the N well region. 202 is fixed to be the same. Further, the depth closer to the junction between the P well region 201 and the N well region 202 than the majority carrier trap region 402 made of an N-type high concentration impurity region in the N well region 202 is deeper than the trench isolation region 301. A minority carrier trap region 404 formed of a P-type high-concentration impurity region having, is formed, and the potential thereof is fixed to be the same as that of the P well region 201.

  The P well region 201 in the vicinity of the junction between the P well region 201 and the N well region 202 is composed of an N-type high concentration impurity region from the side close to the junction between the P well region 201 and the N well region 202. A minority carrier trap region 403, a majority carrier trap region 401 composed of a P-type high-concentration impurity region, and an N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, are arranged. In contrast, the N-type well region 202 in the vicinity of the junction between the P-well region 201 and the N-well region 202 has a P-type high height from the side close to the junction between the P-well region 201 and the N-well region 202. A minority carrier trap region 404 formed of a concentration impurity region, a majority carrier trap region 402 formed of an N type high concentration impurity region, and a P type high concentration impurity region 502 which is a source or drain region of a P type MOS transistor, for example. Has been placed.

  Then, a minority carrier trap region 403 made of an N-type high concentration impurity region in the P well region 201, a majority carrier trap region 401 made of a P type high concentration impurity region, and a P type high concentration in the N well region 202. The minority carrier trap region 404 made of an impurity region and the majority carrier trap region 402 made of an N-type high concentration impurity region each have a deeper depth than the trench isolation region 301.

  The source of, for example, an N-type MOS transistor formed in the P-well region 201, the N-well region 202, and the P-well region 201 by providing the majority carrier and minority carrier capture regions in the above-described form. And an N-type high-concentration impurity region 501 that is a drain region and a P-type high-concentration impurity region 502 that is a source or drain region of a P-type MOS transistor formed in the N-well region 202, for example. Even when majority carriers or minority carriers flow out due to potential fluctuations caused by triggers such as external surges or potential fluctuations due to internal circuit operation, they are effectively captured to prevent diffusion Therefore, the latch-up phenomenon can be effectively prevented.

  Here, from the viewpoint of the latch-up operation and its prevention, the arrangement and positional relationship between the majority carrier capture region and the minority carrier capture region and the source and drain regions of the MOS transistor will be particularly described.

  It is important to dispose the source and drain regions of the MOS transistor that can be a latch-up operation target from the opposite well ends in order to increase the base width in the bipolar operation. For example, the N-type MOS transistor in the P-well region is as far away as possible from the N-well region.

  In order to prevent potential fluctuation in the well region in the vicinity of the source and drain regions of the MOS transistor, it is preferable to fix the potential by providing a high concentration impurity region having the same conductivity type as the well nearby. This becomes a majority carrier capture region, and when carriers (becomes majority carriers) flow in from the opposing well regions, they can be absorbed in this region before reaching the MOS transistor. Also, in the unlikely event that the well potential fluctuates and carriers (which become minority carriers) flow out from the source and drain regions of the MOS transistor, before the MOS transistor reaches the opposite well region, It is preferable to capture in the same well region that is installed. For this purpose, a minority carrier region is provided, and the potential is preferably fixed to the same potential as the opposing well so that minority carriers can be sucked easily. For these reasons, it is important to dispose the minority carrier trap region, the majority carrier trap region, and the source and drain regions of the MOS transistor from the side close to the well end (well junction).

  In the first embodiment shown in FIG. 1, for example, an N-type high concentration impurity region 501 which is a source or drain region of an N-type MOS transistor, or a source or drain region of a P-type MOS transistor, for example. Although the P-type high-concentration impurity region 502 is illustrated as having a relatively shallower depth than the trench isolation region 301, this is an example, and the present invention is not limited to this. A deep diffusion layer may be required depending on the purpose such as to achieve a high breakdown voltage structure. In that case, a minority carrier trap region 403 composed of an N-type high-concentration impurity region in the P-well region 201 and a P-type A majority carrier trap region 401 composed of a high concentration impurity region, a minority carrier trap region 404 composed of a P type high concentration impurity region and a majority carrier capture region 402 composed of an N type high concentration impurity region in the N well region 202. The P-type high concentration diffusion region or the source or drain region of the N-type MOS transistor in the P well region 201, or the N-type high concentration diffusion region or the P-type MOS transistor in the N well region 202. It can be formed by the same impurity diffusion layer as the source or drain region. , It is possible to form a special increase step without majority carriers and minority carrier capture region for easy latch-up prevention.

  In the example of FIG. 1, an example is shown in which a P-type silicon substrate is used as the first conductive semiconductor substrate, a P-well is used as the first well, and an N-well is used as the second well, but an N-type is used as the first conductive semiconductor substrate. The silicon substrate may be an N well as the first well and a P well as the second well.

  Although illustration is omitted, in the low power supply voltage circuit portion of the semiconductor device according to the present invention, since the operating voltage is low, parasitic bipolar operation and latch-up hardly occur. Therefore, since a carrier trap region having a depth deeper than that of the trench isolation region as described above is not necessary, high integration can be achieved.

  As described above, the present invention uses the same trench isolation in the low power supply voltage circuit section as in the high power supply voltage circuit section while providing sufficient latch-up resistance to the high power supply voltage circuit section without increasing the number of processes. However, a semiconductor device having a high degree of element integration can be obtained.

  FIG. 2 is a schematic cross-sectional view showing a second embodiment of the high power supply voltage circuit portion of the semiconductor device according to the present invention.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, an N-well region 202 made of an N-type low-concentration impurity region is formed as a second well, and the surface of the P-type silicon substrate 101 is formed. The N-type high-concentration impurity region 501 that is a source and drain region of an N-type MOS transistor, for example, is a source and drain region of a P-type MOS transistor on the surface of the N-well region 202, for example. A P-type high concentration impurity region 502 is formed, and a trench isolation region 301 for isolating those elements is formed.

  The junction between the P-type silicon substrate 101 and the N-well region 202 in the P-type silicon substrate 101 in the vicinity of the junction between the P-type silicon substrate 101 and the N-well region 202 rather than the N-type high concentration impurity region 501. A majority carrier trap region 401 composed of a P-type high-concentration impurity region having a depth deeper than that of the trench isolation region 301 is formed by removing a part of the trench isolation region 301 at a position close to the portion, and its potential is Is fixed at the same potential as the P-type silicon substrate 101. Further, in the P-type silicon substrate 101, the trench isolation region 301 is located closer to the junction between the P-type silicon substrate 101 and the N-well region 202 than the majority carrier trap region 401 composed of the P-type high concentration impurity region. A minority carrier trap region 403 made of an N-type high concentration impurity region having a deeper depth is formed, and the potential thereof is fixed to the same potential as that of the N well region 202.

  On the other hand, in the N-well region 202 in the vicinity of the junction between the P-type silicon substrate 101 and the N-well region 202, the junction between the P-well region 201 and the N-well region 202 is located more than the P-type high-concentration impurity region 502. Near the position, a majority carrier trap region 402 made of an N-type high concentration impurity region having a depth deeper than that of the trench isolation region 301 is formed by removing a part of the trench isolation region 301, and the potential is N It is fixed at the same potential as the well region 202. Further, in a position closer to the junction between the P-type silicon substrate 101 and the N-well region 202 than the majority carrier trap region 402 made of an N-type high-concentration impurity region in the N-well region 202, it is deeper than the trench isolation region 301. A minority carrier trap region 404 made of a P-type high-concentration impurity region having a depth is formed, and its potential is fixed to the same potential as that of the P-type silicon substrate 101.

  In the P-type silicon substrate 101 in the vicinity of the junction between the P-type silicon substrate 101 and the N-well region 202, an N-type is formed from the side close to the junction between the P-type silicon substrate 101 and the N-well region 202. Minority carrier trap region 403 made of a high concentration impurity region, majority carrier trap region 401 made of a P type high concentration impurity region, and an N type high concentration impurity region 501 that is a source or drain region of an N type MOS transistor, for example. Is arranged. In contrast, in the N-well region 202 in the vicinity of the junction between the P-type silicon substrate 101 and the N-well region 202, from the side close to the junction between the P-type silicon substrate 101 and the N-well region 202, Minority carrier trap region 404 composed of a P-type high-concentration impurity region, majority carrier trap region 402 composed of an N-type high-concentration impurity region, and P-type high-concentration that is a source or drain region of, for example, a P-type MOS transistor Impurity region 502 is arranged.

  Then, a minority carrier trap region 403 made of an N-type high concentration impurity region and a majority carrier trap region 401 made of a P-type high concentration impurity region in the P-type silicon substrate 101, and a P-type in the N-well region 202. The minority carrier trap region 404 made of a high concentration impurity region and the majority carrier trap region 402 made of an N-type high concentration impurity region each have a deeper depth than the trench isolation region 301.

  In the above-described form, for example, an N-type MOS formed in the P-type silicon substrate 101 and the N-well region 202 and the P-type silicon substrate 101 by installing the majority carrier and minority carrier capture regions. For example, a P-type high-concentration impurity region 502 that is a source or drain region of a P-type MOS transistor formed in an N-type high-concentration impurity region 501 that is a source or drain region of a p-type transistor and an N-well region 202. When majority carriers and minority carriers flow out due to potential fluctuations caused by triggers such as external surges and potential fluctuations caused by internal circuit operations, they are effectively captured. Diffusion can be prevented and a latch-up phenomenon can be effectively prevented.

  Since a supplementary explanation for latch-up and the effect of the present invention are the same as those in the first embodiment, a description thereof is omitted.

  In the second embodiment shown in FIG. 2, for example, an N-type high concentration impurity region 501 which is a source or drain region of an N-type MOS transistor, or a source or drain region of a P-type MOS transistor, for example. Although the P-type high-concentration impurity region 502 is illustrated as having a relatively shallower depth than the trench isolation region 301, this is an example, and the present invention is not limited to this. Depending on the purpose such as achieving a high breakdown voltage structure, a deep diffusion layer may be required. In this case, a minority carrier trap region 403 made of an N-type high concentration impurity region in the P-type silicon substrate 101 and A majority carrier trap region 401 composed of a P-type high concentration impurity region, a minority carrier trap region 404 composed of a P type high concentration impurity region in the N well region 202, and a majority carrier trap region composed of an N type high concentration impurity region. Reference numeral 402 denotes a P-type high concentration diffusion region in the P-type silicon substrate 101 or a source or drain region of an N-type MOS transistor, or an N-type high concentration diffusion region or P-type in the N well region 202. It can be formed by the same impurity diffusion layer as the source or drain region of a MOS transistor In it, which makes it possible to form a special increase step without majority carriers and minority carrier capture region for easy latch-up prevention.

  In the example of FIG. 2, an example in which a P-type silicon substrate is used as the first conductive semiconductor substrate and an N-well is used as the second well is shown. However, an N-type silicon substrate is used as the first conductive semiconductor substrate, and the second well is used. A P-well may be used.

  For other explanations and effects, the same reference numerals as those in FIG.

  As described above, the present invention provides sufficient latch-up resistance to the high power supply voltage circuit without increasing the number of processes, and also uses the same trench isolation as the high power supply voltage circuit in the low power supply voltage circuit. A semiconductor device having a high degree of element integration can be obtained.

1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device of the present invention. It is typical sectional drawing which shows the 2nd Example of the semiconductor device of this invention.

Explanation of symbols

101 P-type silicon substrate 201 P-well region 202 N-well region 301 Trench isolation region 401 Majority carrier trap region 402 made of P-type high-concentration impurity region Majority carrier trap region 403 made of N-type high-concentration impurity region Minority carrier trap region 404 composed of a high concentration impurity region 404 Minority carrier trap region 501 composed of a P type high concentration impurity region N type high concentration impurity region 502 P type high concentration impurity region

Claims (5)

  A trench isolation structure having a high power supply voltage circuit section and a low power supply voltage circuit section on the same semiconductor substrate, wherein each element in the high power supply voltage circuit section and the low power supply voltage circuit section is separated by a trench isolation region And the high power supply voltage circuit section is provided on a first conductive type semiconductor substrate, and includes a first MOS type transistor disposed in the first conductive type semiconductor substrate, and a second conductive type well. And a second MOS type transistor disposed in the well region, in the vicinity of the junction between the first conductive type semiconductor substrate and the well region, the first MOS type transistor. A majority carrier for preventing latch-up at a position closer to the end of the semiconductor substrate and closer to the end of the well region than the second MOS transistor. Each having a catch region and the minority carrier capture region, the minority carrier region being disposed closer to the junction in the semiconductor substrate and the second well region than the majority carrier capture region; The depth of the majority carrier capture region and the minority carrier capture region is formed deeper than the depth of the trench isolation region.   The potential of the majority carrier trap region disposed in the semiconductor substrate is fixed to the same potential as the semiconductor substrate, and the potential of the minority carrier trap region disposed in the semiconductor substrate is the same as that of the well. The potential of the majority carrier capture region disposed in the well is fixed at the same potential as the well, and the potential of the minority carrier capture region disposed in the well is 2. The semiconductor device according to claim 1, wherein the semiconductor device is fixed at the same potential as that of the semiconductor substrate.   A trench isolation structure having a high power supply voltage circuit section and a low power supply voltage circuit section on the same semiconductor substrate, wherein each element in the high power supply voltage circuit section and the low power supply voltage circuit section is separated by a trench isolation region And the high power supply voltage circuit section is provided on a first conductivity type semiconductor substrate, and includes a first conductivity type first well region and a first MOS type transistor disposed in the first well region. , A semiconductor device having a second conductivity type second well region and a second MOS transistor disposed in the second well region, and in the vicinity of a junction between the first well region and the second well region The latch circuit is positioned closer to the end of the first well region than the first MOS type transistor and closer to the end of the second well region than the second MOS type transistor. A minority carrier capture region and a minority carrier capture region for preventing the trapping, and the minority carrier region is closer to the end of the first or second well region than the majority carrier capture region. The semiconductor device is disposed at a position, and the depth of the majority carrier capture region and the minority carrier capture region is formed deeper than the depth of the trench isolation region.   The potential of the majority carrier capture region disposed in the first well is fixed to the same potential as the first well, and the potential of the minority carrier capture region disposed in the first well is the first potential. The potential of the majority carrier capturing region disposed in the second well is fixed at the same potential as that of the second well, and is fixed in the second well. 4. The semiconductor device according to claim 3, wherein the potential of the minority carrier trapping region is fixed to the same potential as that of the first well.   The majority carrier trapping region and the minority carrier trapping region formed in the high power supply voltage circuit unit are the source or drain region of the first MOS transistor and the second region arranged in the high power supply voltage circuit unit. 5. The semiconductor device according to claim 1, wherein the semiconductor device is formed of the same diffusion layer as the source or drain region of the MOS transistor.

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