JP2011071326A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a high degree of element integration using the same trench isolation with a high power supply voltage circuit part for a low power supply voltage circuit part while imparting satisfactory latch-up resistance to the high power supply voltage circuit part. <P>SOLUTION: The semiconductor device having a trench isolation structure is constituted by forming at least one well region and an MOS type transistor at the high power supply voltage circuit part, and a carrier capturing region composed of a silicon region whose crystallinity is broken by argon ion implantation of high energy or the like and a region into which heavy metal such as gold is implanted is formed and disposed at an end of a well region so as to prevent a latch-up. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench isolation structure such as a CMOS device having multiple power supply voltages using trench isolation as an element isolation structure.

  In a semiconductor device having a CMOS device that uses multiple power supply voltages, the integration of the low power supply voltage part constituting the internal circuit such as a logic circuit is improved, and the high power supply voltage part used in the input / output circuit is latched up. It is important to ensure resistance.

  For element isolation, a trench isolation method suitable for higher integration than the LOCOS method is often adopted. However, in a semiconductor device in which element isolation is performed by trench isolation, sufficient latch-up resistance is provided for a high power supply voltage circuit section. In order to increase the depth of the well, it is necessary to suppress the parasitic bipolar operation by increasing the depth of the well. Also, in order to suppress the leakage current between the NMOS transistor and the PMOS transistor and to ensure the breakdown voltage characteristic, the isolation width of the trench isolation portion It was necessary to take big. For this reason, even in the low power supply voltage circuit section, when the same trench isolation as that of the high power supply voltage circuit section is used, there is a problem that the degree of integration of elements in the low power supply voltage section that requires high integration is lowered.

  As an improvement measure, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, or the isolation width of the trench isolation section of the high power supply voltage circuit section is reduced. A method has been proposed in which the width is larger than the trench isolation width (see, for example, Patent Document 1).

JP 2000-58673 A

  However, in the semiconductor device using the multiple power supply voltage separated by the trench isolation as described above, the well bipolar circuit is formed by increasing the depth of the well in order to give the high power supply voltage circuit section sufficient latch-up resistance. It is necessary to suppress the operation, and it is necessary to increase the isolation width of the trench isolation portion in order to suppress the leakage current between the NMOS transistor and the PMOS transistor and to ensure the breakdown voltage characteristics. For this reason, in the low power supply voltage circuit section, if the same trench isolation as that of the high power supply voltage circuit section is used, the integration of elements in the low power supply voltage circuit section requiring high integration is reduced.

  Also, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, and the isolation width of the trench isolation section of the high power supply voltage circuit section is wider than that of the low power supply voltage circuit section. However, there have been problems such as an increase in manufacturing steps and an increase in separation width leading to an increase in cost.

  In order to solve the above problems, the present invention is configured as follows.

  A high power supply voltage circuit portion and a low power supply voltage circuit portion, and a trench isolation structure in which each element in the high power supply voltage circuit portion and the low power supply voltage circuit portion is isolated by a trench isolation region, In the semiconductor device in which at least one well region and a MOS transistor are formed in the voltage circuit portion, a semiconductor device having a carrier capture region for preventing latch-up at the junction of the well region is used.

  The carrier trapping region is formed of a silicon region whose crystallinity is destroyed.

  The carrier capture region is formed of a silicon region into which heavy metal is implanted.

  By these means, a semiconductor device having a high degree of element integration while using the same trench isolation as that of the high power supply voltage circuit section in the low power supply voltage circuit section while having sufficient latch-up resistance in the high power supply voltage circuit section. Can be obtained.

As described above, according to the present invention, the high power supply voltage circuit section and the low power supply voltage circuit section are provided, and each element in the high power supply voltage circuit section and the low power supply voltage circuit section is separated by the trench isolation region. In a semiconductor device having a trench isolation structure and at least one well region and a MOS transistor formed in a high power supply voltage circuit portion, a carrier trap region for preventing latch-up is provided at an end portion of the well region. I did it.
The carrier trapping region is formed of a silicon region whose crystallinity is destroyed.
The carrier capture region is formed of a silicon region into which heavy metal is implanted.

  By these means, a semiconductor device having a high degree of element integration while using the same trench isolation as that of the high power supply voltage circuit section in the low power supply voltage circuit section while having sufficient latch-up resistance in the high power supply voltage circuit section. Can be obtained.

1 is a schematic top view showing a first embodiment of a semiconductor device of the present invention. 1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device of the present invention. It is typical sectional drawing which shows the 2nd Example of the semiconductor device of this invention.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

  FIG. 1 is a schematic top view showing a first embodiment of the semiconductor device of the present invention.

  A high power supply voltage circuit unit 10 and a low power supply voltage circuit unit 20 are disposed on a P-type silicon substrate 101 serving as a first conductivity type semiconductor substrate. In the high power supply voltage circuit section 10, a P well region 201 made of a P-type low concentration impurity region and a N well region 202 made of an N type low concentration impurity region are formed adjacent to each other as a first well. In addition, a plurality of MOS transistors 11 are arranged on the surfaces thereof. Further, a trench isolation region 301 for element isolation is disposed around the periphery. At the junction between the P well region 201 and the N well region 202, a carrier trap region 401 made of a silicon region whose crystallinity is broken by high energy argon ion implantation or a region where heavy metal such as gold is implanted. Is provided.

  In the low power supply voltage circuit unit 20, the element 21 isolated by the trench isolation region 301 is disposed. This element may be a MOS transistor, and is not particularly limited here.

  FIG. 2 shows a high power supply voltage circuit portion of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view along a cutting line AA in FIG. 1.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. Well regions 202 are formed adjacent to each other, and a plurality of MOS transistors (not shown) are formed on the surfaces thereof, and trench isolation regions 301 for isolating those elements are formed. Yes. At the junction between the P well region 201 and the N well region 202, a carrier trap region 401 made of a silicon region whose crystallinity is broken by high energy argon ion implantation or a region where heavy metal such as gold is implanted. Is formed.

  At the junction between the P well region 201 and the N well region 202, a carrier trap region 401 is formed which is composed of a silicon region whose crystallinity is destroyed by high energy argon ion implantation or the like, or a silicon region into which heavy metal such as gold is implanted. As a result, the P well region 201, the N well region 202, the P type silicon substrate 101, and the source or drain region of the MOS transistor formed in the P well region 201 or the N well region 202 (not shown) In the meantime, carriers generated by triggers such as external surges and potential fluctuations due to internal circuit operations can be effectively captured, and latch-up caused by carrier generation can be effectively prevented.

  In the example of FIGS. 1 and 2, an example is shown in which a P-type silicon substrate is used as the first conductive semiconductor substrate, a P well is used as the first well, and an N well is used as the second well. An N-type silicon substrate, an N well as the first well, and a P well as the second well may be used.

  In addition, although the example in which the carrier capture region 401 is disposed so as to penetrate the trench isolation region 301 is shown, it may be formed on the lower surface of the trench isolation region 301.

  Although not shown, in the low power supply voltage circuit portion of the semiconductor device according to the present invention, since the operating voltage is low, parasitic bipolar operation and latch-up are unlikely to occur. Therefore, since a carrier trapping region is not necessary on the lower surface of the trench isolation region as described above, high integration can be achieved.

  As described above, according to the present invention, the high power supply voltage circuit unit has sufficient latch-up resistance, and the low power supply voltage circuit unit uses the same trench isolation as the high power supply voltage circuit unit and has a high element integration degree. Can be obtained.

  FIG. 3 is a schematic cross-sectional view showing a second embodiment of the high power supply voltage circuit portion of the semiconductor device of the present invention.

  On a P-type silicon substrate 101 serving as a first conductivity type semiconductor substrate, an N-well region 202 made of an N-type low-concentration impurity region is formed as a second well. Although not shown, a plurality of MOS transistors are formed, and a trench isolation region 301 for isolating those elements is formed. A carrier trap region 401 made of a P-type high concentration impurity region is formed on the lower surface of the trench isolation region 301 in the P-type silicon substrate 101 in the vicinity of the junction between the P-type silicon substrate 101 and the N-well region 202. In addition, at the junction between the P-type silicon substrate 101 and the N-well region 202, a carrier composed of a silicon region whose crystallinity has been destroyed by high-energy argon ion implantation or the like, or a region into which heavy metal such as gold has been implanted. A capture region 401 is formed.

  A carrier trap region 401 composed of a silicon region whose crystallinity is broken by high energy argon ion implantation or a silicon region into which heavy metal such as gold is implanted at the junction between the P-type silicon substrate 101 and the N well region 202. Is formed between the N well region 202 and the P type silicon substrate 101 and the source or drain region of the MOS transistor formed in the P type silicon substrate 101 or the N well region 202 (not shown). In the meantime, it is possible to effectively capture carriers generated by a trigger such as an external surge or potential fluctuation caused by internal circuit operation, and effectively prevent latch-up caused by carrier generation.

  In the example of FIG. 2, an example in which a P-type silicon substrate is used as the first conductive semiconductor substrate and an N-well is used as the second well is shown. However, an N-type silicon substrate is used as the first conductive semiconductor substrate, and the second well is used. A P-well may be used. In addition, although the example in which the carrier capture region 401 is disposed so as to penetrate the trench isolation region 301 is shown, it may be formed on the lower surface of the trench isolation region 301. Other explanations are replaced by the same reference numerals as those in FIG.

  As described above, according to the present invention, the high power supply voltage circuit unit has sufficient latch-up resistance, and the low power supply voltage circuit unit uses the same trench isolation as that of the high power supply voltage circuit unit to achieve high element integration. A semiconductor device can be obtained.

DESCRIPTION OF SYMBOLS 10 High power supply voltage circuit part 11 MOS type transistor 20 Low power supply voltage circuit part 21 Element 101 P type silicon substrate 201 P well region 202 N well region 301 Trench isolation region 401 Carrier trap region

Claims (5)

  A high power supply voltage circuit portion and a low power supply voltage circuit portion, and a trench isolation structure in which each element in the high power supply voltage circuit portion and the low power supply voltage circuit portion is isolated by a trench isolation region, A semiconductor device in which at least one well region and a MOS transistor are formed in a voltage circuit portion, and a semiconductor device having a carrier capture region for preventing latch-up at a junction of the well region.   The semiconductor device according to claim 1, wherein the carrier trap region is formed of a silicon region whose crystallinity is broken.   The semiconductor device according to claim 1, wherein the carrier trap region is formed of a silicon region into which heavy metal is implanted.   The high power supply voltage circuit unit includes a first conductive semiconductor substrate, a first well of a first conductivity type, and a second well of a second conductivity type, and the junction between the first well and the second well The semiconductor device according to claim 1, further comprising a carrier trap region.   The high power supply voltage circuit unit includes a first conductivity type semiconductor substrate and a second conductivity type second well, and has the carrier trapping region at a junction between the first conductivity type semiconductor substrate and the second well. 1. The semiconductor device according to 1.

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