JP2008204555A5

JP2008204555A5 -

Info

Publication number: JP2008204555A5
Application number: JP2007040111A
Authority: JP
Filing date: 2007-02-21
Publication date: 2010-03-18

Claims

A logic device and a semiconductor device in which a plurality of semiconductor memory devices are mixedly mounted in the same chip,
A memory selection circuit for outputting a second operation control signal and a memory selection signal in the second operation mode by external control;
The semiconductor memory device includes a memory array composed of a plurality of memory cell blocks, and
In the first operation mode , the first operation control signal from the logic unit is selected, and in the second operation mode , the memory selection signal and the second operation control signal are selected to control the memory array. outputs a control circuit section for outputting a second data output selection signal for switching the output selection signal and the second data output switching the input and output data by operating mode,
When the internal operation control signal is input, the first data is read from or written to an arbitrary memory cell in the first operation mode , and the second data having an arbitrary data width is input from the outside in the second operation mode. having said second data written by the writing collectively for all the bits of the memory cell block of the row address from said memory cell blocks and a data output circuit for controlling reading sequentially, a second operation In the mode , the semiconductor device is characterized in that all bits of the memory cell block having the same row address of all the semiconductor memory devices are collectively written.

A logic device and a semiconductor device in which a plurality of semiconductor memory devices are mixedly mounted in the same chip,
A memory selection circuit for outputting a second operation control signal and a memory selection signal in the second operation mode by external control;
The semiconductor memory device includes a memory array composed of a plurality of memory cell blocks, and
In the first operation mode , the first operation control signal from the logic unit is selected, and in the second operation mode , the memory selection signal and the second operation control signal are selected to control the memory array. outputs a control circuit section for outputting a second data output selection signal for switching the output selection signal and the second data output switching the input and output data by operating mode,
When the internal operation control signal is input, the first data is read from or written to an arbitrary memory cell in the first operation mode , and the second data having a specific data width is input from the outside in the second operation mode. A data input / output circuit for performing control to write the second data to the memory cell block and divide all the bit data of the memory cell block into a specific data width and read the data at once;
A coincidence detection circuit for outputting a coincidence detection signal when all the bit data of the memory cell block of the same row address read by the control of the data input / output circuit is read and compared for each specific data width; ,
A data compression circuit for outputting second data having a specific data width read from the memory cell block when the coincidence detection signal indicates coincidence, and outputting predetermined predetermined data when indicating coincidence; When the coincidence determination result indicating whether or not the second data read from all the semiconductor memory devices is coincident is coincident , the data output from the data compression circuit is not coincident Has a batch judgment circuit for outputting predetermined predetermined data to the outside, and in the second operation mode , all the bit data of the memory cell block of the same row address of all the semiconductor memory devices are read at once. A semiconductor device that outputs a result of coincidence determination of read data.

A logic device and a semiconductor device in which a plurality of semiconductor memory devices are mixedly mounted in the same chip,
A memory selection circuit for outputting a second operation control signal and a memory selection signal in the second operation mode by external control;
The semiconductor memory device includes a memory array composed of a plurality of memory cell blocks, and
In the first operation mode , the first operation control signal from the logic unit is selected, and in the second operation mode , the memory selection signal and the second operation control signal are selected to control the memory array. outputs a control circuit section for outputting a second data output selection signal for switching the output selection signal and the second data output switching the input and output data by operating mode,
When the internal operation control signal is input, the first data is read from or written to an arbitrary memory cell in the first operation mode , and the second data having a specific data width is input from the outside in the second operation mode. A data input / output circuit for performing a control to sequentially read out the second data written and written in a lump for all the bits of the memory cell block at the same row address;
A coincidence detection circuit for outputting a coincidence detection signal when all the bit data of the memory cell block of the same row address read by the control of the data input / output circuit is read and compared for each specific data width; ,
A data compression circuit for outputting second data having a specific data width read from the memory cell block when the coincidence detection signal indicates coincidence, and outputting predetermined predetermined data when indicating coincidence; Output a match determination result indicating whether or not the second data read from all the semiconductor memory devices match, and if they match, the data output from the data compression circuit does not match Has a batch judgment circuit for outputting predetermined predetermined data to the outside. In the second operation mode , all the bit data of the memory cell block of the same row address of all the semiconductor memory devices are read and written in batch. A semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein the control circuit can select whether or not batch writing is required for the memory cell blocks of all semiconductor memory devices in the second operation mode .

3. The semiconductor device according to claim 2 , wherein the control circuit can select whether or not batch reading from the memory cell block of all the semiconductor memory devices is necessary in the second operation mode .

4. The semiconductor device according to claim 3, wherein the control circuit can select whether or not batch reading / writing is required for the memory cell blocks of all semiconductor memory devices in the second operation mode .

7. The semiconductor device according to claim 6, wherein the coincidence determination result output from the collective determination circuit is assigned to the second data output terminal for output.

8. The semiconductor device according to claim 1, wherein the first operation mode is a normal operation, and the second operation mode is a test mode .

When inspecting the semiconductor memory device of the semiconductor device in which the logic unit and the plurality of semiconductor memory devices are mixedly mounted in the same chip,
A step of inputting test data having an arbitrary data width from the outside and writing all the bits of the memory cell block of the same row address of all the semiconductor memory devices in a lump;
And a step of reading out the written test data from the semiconductor memory device .

When inspecting the semiconductor memory device of the semiconductor device in which the logic unit and the plurality of semiconductor memory devices are mixedly mounted in the same chip,
Writing test data into the semiconductor memory device;
Dividing the test data into arbitrary data widths from memory cell blocks of the same row address of all the semiconductor memory devices and reading them in a batch;
A step of outputting a coincidence detection signal when the stored test data for each of the read semiconductor memory devices are compared with each other and coincide with each other;
When the coincidence detection signal indicates coincidence, the test data read from the semiconductor memory device is output. When the coincidence detection signal indicates inconsistency, predetermined predetermined data is output and the test is read from all the semiconductor memory devices. And a step of outputting a coincidence determination result indicating whether or not the data coincide with each other.

When inspecting the semiconductor memory device of the semiconductor device in which the logic unit and the plurality of semiconductor memory devices are mixedly mounted in the same chip,
A step of inputting test data having an arbitrary data width from the outside and writing all the bits of the memory cell block of the same row address of all the semiconductor memory devices in a lump;
Dividing the test data into arbitrary data widths from memory cell blocks of the same row address of all the semiconductor memory devices and reading them in a batch;
A step of outputting a coincidence detection signal when the stored test data for each of the read semiconductor memory devices are compared with each other and coincide with each other;
When the coincidence detection signal indicates coincidence, the test data read from the semiconductor memory device is output. When the coincidence detection signal indicates non-coincidence, predetermined predetermined data is output and the test is read from all the semiconductor memory devices. Outputting a match determination result indicating whether or not the data match; and
A method of inspecting a semiconductor device, characterized by have a.

10. The method for inspecting a semiconductor device according to claim 9 , wherein whether or not batch writing is required for all the semiconductor memory devices can be selected in a test mode.

11. The method of inspecting a semiconductor device according to claim 10 , wherein whether or not batch reading from all the semiconductor memory devices is necessary can be selected in a test mode.

12. The method for inspecting a semiconductor device according to claim 11, wherein whether or not batch reading / writing is required for all the semiconductor memory devices can be selected in a test mode.

12. The semiconductor device inspection method according to claim 11, wherein the output coincidence determination result is assigned to a test data output terminal for output.