JP2008204495A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with built-in BIST circuit, which can test also an I/F section between a memory and a system logic. <P>SOLUTION: An FF 122 at a final stage of the IF with the memory 110 is shared by the system logic section 120 and a test logic section 130 to eliminate the need of arranging a selector just before the memory. Thus, the IF section between the memory and the system logic is also tested. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a built-in functional circuit (hereinafter referred to as a BIST circuit) capable of performing a so-called built-in self-test for self-inspecting a semiconductor memory part inside a chip.

Today's deep submicron technology makes it possible to mount enormous amounts of memory on a single chip. A memory BIST (Built In Self Test) circuit mounted on the chip is used to perform a post-manufacturing test on a large number of memories arranged on the chip. FIG. 4 shows a basic structure of a memory BIST circuit 10 that is generally used.
When the memory BIST is executed in the memory BIST circuit 10, the memory 1 is accessed by switching the selector 2 provided in the previous stage of the memory 1 with the mode switching signal and the test access signal from the controller 11 accessing the memory 1. The data output value of the memory 1 for the access is compared with the expected value obtained from the controller 11 by the comparator 12, and the comparison result is output to the outside of the chip as a test output. The memory BIST circuit 10 is a system that performs such an operation.

  On the other hand, normally, when the system logic unit 20 accesses the memory 1, a system control signal sent from the memory access control logic 21 is stored in the flip-flop (FF) 22, and then passes through the selector 2 to the memory 1. to access.

Regarding such a memory BIST circuit, there are methods disclosed in Patent Document 1 and Patent Document 2 as a method of testing a memory at an original memory operating speed (at-speed) on the system.
Japanese translation of PCT publication No. 2004-512630 JP 2006-155682 A

  However, even in the test systems disclosed in Patent Document 1 and Patent Document 2, the basic structure is a structure in which the access to the memory at the normal time and at the time of the test is switched by the selector similarly to the structure shown in FIG. is there. Therefore, even when the memory BIST circuit 10 determines that the memory 1 is normal, the I / F portion between the system logic 20 and the memory 1, that is, the FF 22 which is the final stage of the system logic 20, to the selector 2 There is a problem that the memory BIST circuit 10 cannot perform a test on the path between the two.

  Further, in the conventional configuration shown in FIG. 4, by incorporating the memory BIST circuit 10 only for testing into the chip, the selector 2 must be provided after the FF 22 provided in the system logic 20, and the normal configuration other than the time of inspection Even in this memory access, the access signal to the memory 1 must pass through the selector 2 and the operation speed is deteriorated.

  Further, since the memory usually occupies a large area in the chip, it is difficult to flexibly change the arrangement according to the timing situation of the internal logic. In some cases, the arrangement positions of the system logic cell and the memory may be far from each other. In such a case, the characteristics of the cell immediately before the memory are remarkably deteriorated, and as a result, the memory cannot be accessed correctly. Therefore, a method for testing between the cell immediately before the memory and the memory is required.

  The present invention has been made to solve the above-described problems, and provides a semiconductor integrated circuit device that incorporates a BIST circuit and can also test an I / F portion between a semiconductor memory and system logic. The purpose is to do.

In order to achieve the above object, the present invention is configured as follows.
That is, the semiconductor integrated circuit device according to the first aspect of the present invention includes a semiconductor memory unit, a system logic unit that accesses the semiconductor memory unit in a normal operation mode, and an access to the semiconductor memory unit in a test mode of the semiconductor memory unit. In a semiconductor integrated circuit device having a built-in test logic unit,
A control signal selector for selecting and sending either a system control signal from the system logic unit or a test control signal from the test logic unit according to mode switching;
It is arranged at the last stage of the system logic unit and serves as an interface with the semiconductor memory unit. Either the system control signal or the test control signal is supplied from the control signal selector and sent as an access signal to the semiconductor memory unit. A flip-flop shared by the system logic unit and the test block unit;
It is provided with.

  Further, the test logic unit compares the data output value of the semiconductor memory according to the access signal with an expected value corresponding to the data output value, to the pipelined access to the semiconductor memory by the flip-flop. It is also possible to have a comparator that performs at a corresponding timing.

  Further, a plurality of the semiconductor memory units may be provided, and a plurality of the control signal selectors and the flip-flops may be provided correspondingly.

  When the access signal accesses the corresponding semiconductor memory unit from each of the flip-flops, any one of the plurality of flip-flops feeds back the access signal to the test logic unit. Also good.

  And a clock selector for supplying a plurality of different clocks, selecting one of the plurality of clocks in synchronization with the control signal selector according to the mode switching, and sending the selected clock to the flip-flop circuit. You may comprise as follows.

  According to the semiconductor integrated circuit device of the first aspect, the flip-flop provided at the final stage of the system logic unit and serving as an interface with the semiconductor memory unit is shared in the normal operation mode and the test mode. Therefore, no selector is provided immediately before the semiconductor memory unit, and the semiconductor memory unit is accessed through the flip-flop serving as the interface of the semiconductor memory unit in both the normal operation mode and the test mode. . Therefore, the I / F portion between the semiconductor memory and the system logic can also be tested.

  In addition, the control signal selector is provided not in front of the semiconductor memory unit but in the previous stage of the flip-flop, so that it is optimal for satisfying the desired timing constraints when synthesizing the system logic unit from the RTL or at the RTL design stage. It can be realized relatively easily. Therefore, it is possible to prevent deterioration in access timing to the semiconductor memory unit.

  In addition, by sharing the flip-flop as described above, access to the semiconductor memory unit is pipelined even in the case of a controller configuration in which the final stage of the controller in the test logic unit is not a flip-flop. In such a case, the test logic unit has a configuration including a comparator that compares the data output value of the semiconductor memory with the expected value at a timing corresponding to the pipelined access to the semiconductor memory. Therefore, an existing controller whose final stage is not a flip-flop can be embedded in a chip as it is.

  In the above-described configuration, a plurality of the semiconductor memory units can be provided, and a plurality of semiconductor memory units can be tested at the same time.

  In addition, since the clock selector is provided and one clock can be selected from a plurality of clocks, the BIST of the semiconductor memory unit can be executed with various clocks. Thus, for example, BIST can be executed at the same speed as the actual operation speed by the system logic unit.

  A semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals.

First embodiment:
FIG. 1 shows the configuration of the semiconductor integrated circuit device 101 of this embodiment. The semiconductor integrated circuit device 101 includes a semiconductor memory unit 110 (hereinafter sometimes simply referred to as a memory 110), a system logic unit 120 that accesses the semiconductor memory unit 110 in a normal operation mode, and a test mode of the semiconductor memory unit 110. The test logic unit 130 for accessing the semiconductor memory unit 110 and the control signal selector 140 are built in one chip. In the semiconductor integrated circuit device 101, the system logic unit 120 and the test logic unit 130 correspond to one memory 110.

  Normally, the last stage of the system logic for accessing the memory is configured by a flip-flop. In this embodiment, the system logic unit 120 also includes the control logic 121 for accessing the memory 110 and the system logic unit 120. The flip-flop 122 arranged at the last stage and serving as an interface with the memory 110 is further provided, and the control signal selector 140 is further provided. The control signal selector 140 is connected to the flip-flop 122. Note that the control signal selector 140 is not limited to the above-described configuration, and may be provided in a component other than the system logic unit 120 in the chip or independently in the chip.

  The test logic unit 130 has a conventional configuration including a memory BIST control logic 131 that executes a BIST of the memory 110 and a comparator 132.

  The control signal selector 140 is supplied with a system control signal 121a sent out by the control logic 121 in the normal operation mode and a test control signal 131a sent out by the memory BIST control logic 131 when the memory 110 performs BIST. According to the mode switching signal 141 for switching the mode with the test operation, either the system control signal 121a or the test control signal 131a is selected and sent to the flip-flop 122. Thus, in the present embodiment, the flip-flop 122 is shared by the system logic unit 120 and the test logic unit 130. Then, the flip-flop 122 sends either the system control signal 121a or the test control signal 131a to the memory 110 as the access signal 122a.

The operation of the semiconductor integrated circuit device 101 configured as described above will be described below.
By the mode switching signal 141, in the normal operation mode, the system control signal 121a passes through the control signal selector 140, is stored in the flip-flop 122, and accesses the memory 110 as the access signal 122a. When the memory BIST is executed, the test control signal 131a is stored in the flip-flop 122 instead of the system control signal 121a, and the memory 110 is accessed as the access signal 122a. In any case, feedback of the access signal 122 a sent from the flip-flop 122 to the memory 110 is necessary for the operation of the control logic 121 and 131.

  When the memory BIST is executed, the test control signal 131a passes through the control signal selector 140 by the mode switching signal 141, is stored in the flip-flop 122, and accesses the memory 110 as the access signal 122a. As a result, the data output value 111 read from the memory 110 is supplied to the comparator 132 of the test logic unit 130. On the other hand, the expected value 131 a corresponding to the access signal 122 a is supplied from the memory BIST control logic 131 to the comparator 132. The comparator 132 compares the data output value 111 with the expected value 131a to check the quality of the memory 110.

  As described above, in the semiconductor integrated circuit device 101 of this embodiment, the system control and the test control are switched by the mode switching signal 141, but the memory 110 is accessed in either case by the flip-flop on the system logic side. 122. That is, even when the memory BIST is executed, the flip-flop 122 accesses the memory 110, so that even if there is some failure in the path between the flip-flop 122 and the memory 110, the memory BIST can detect the failure. It is. That is, a failure of the interface between the system logic 120 and the memory 110 can be found, and a defective chip can be identified as a result.

  Although the control signal selector 140 is provided, since the control signal selector 140 is arranged at the preceding stage of the flip-flop 122, the system logic 120 is transferred from the RTL (Register Transfer Level), which is a level expressed by the flip-flop + combination logic circuit. It is relatively easy to optimize the system logic 120 so as to satisfy desired timing constraints at the time of logic synthesis or at the RTL design stage. Therefore, it is possible to prevent the deterioration of the operation speed due to the provision of the control signal selector 140.

  Further, according to the semiconductor integrated circuit device 101, even when the final stage of the memory BIST control logic 131 that accesses the memory 110 is a controller configuration that is not a flip-flop, access to the memory 110 is pipelined. Will do. Therefore, in such a case, the circuit can be easily realized by devising the circuit of the comparator 132, for example, by devising the circuit so that the comparison with the expected value 131a is performed at a timing considering pipelining. It is. Therefore, the existing memory BIST controller can be embedded in the chip as it is.

Second embodiment:
The semiconductor integrated circuit device 101 described above is configured to include one memory unit 110, but is not limited thereto, and may include a plurality of memory units 110. The second embodiment corresponds to an example of such a configuration, and as shown in FIG. 2, the semiconductor integrated circuit device 102 includes two memory units 110-1 and 110-2. Also, corresponding to the respective memory units 110-1 and 110-2, the flip-flops 122-1 and 122-2 functioning similarly to the above-described flip-flop 122 and the above-described control signal selector 140 function. Control signal selectors 140-1 and 140-2 are provided. Other configurations are the same as those of the semiconductor integrated circuit device 101, and a description thereof is omitted here.

  The semiconductor integrated circuit device 102 of the second embodiment configured as described above can achieve the same effect as that of the semiconductor integrated circuit device 101 described above, and can test a plurality of memory units simultaneously. it can.

  In addition, when accessing each of the memories 110-1 and 110-2 to be tested at the same time, if the address value and the data value are the same, the memory of the access signal 122a to the memories 110-1 and 110-2. As the feedback to the BIST control logic 131, any one of the plurality of access signals 122a supplied to the memories 110-1 and 110-2 to be tested at the same time may be fed back.

Third embodiment:
FIG. 3 shows the configuration of the semiconductor integrated circuit device 103 according to the third embodiment of the present invention. The semiconductor integrated circuit device 103 further includes a clock selector 142 as compared with the configuration of the semiconductor integrated circuit device 101 described above. Other configurations are the same as those of the semiconductor integrated circuit device 101, and a description thereof is omitted here.
The clock selector 142 is supplied with a plurality of different clocks. In this embodiment, two system clocks in the normal operation mode and a test clock in the BIST mode are supplied, but the number is not limited to two, and three or more clocks may be supplied. The clock selector 142 selects any one of the plurality of clocks in synchronization with the control signal selector 140 in accordance with the mode switching described above and sends the selected clock to the clock terminal of the flip-flop 122. In the present embodiment, as described above, the system clock 142a in the normal operation mode and the test clock 142b in the test mode are supplied to the clock selector 142, and the clock selector 142 receives the system switch in the normal operation mode by the mode switching signal 141. The clock 142a is selected and sent to the flip-flop 122. In the test mode, the test clock 142b is selected and sent to the flip-flop 122.

  Since the operation speed of the memory BIST can be made variable by providing the clock selector 142 in this way, a test at the same speed (at-speed) as the actual operation speed of the system logic 120B is possible according to the system request. It is also possible to use for analysis by testing with a test clock slower than the actual operation speed.

  The present invention can be applied to a semiconductor integrated circuit device including a BIST circuit for self-inspecting a semiconductor memory portion inside a chip.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor integrated circuit device in 2nd Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit device in 3rd Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit device incorporating the conventional BIST circuit.

Explanation of symbols

101-103 ... Semiconductor integrated circuit device, 110 ... Memory part,
120 ... System logic part, 122 ... Flip-flop,
130: Test logic unit, 132: Comparator, 140: Control signal selector,
142: Clock selector.

Claims (5)

In a semiconductor integrated circuit device including a semiconductor memory unit, a system logic unit that accesses the semiconductor memory unit in a normal operation mode, and a test logic unit that accesses the semiconductor memory unit in a test mode of the semiconductor memory unit,
A control signal selector for selecting and sending either a system control signal from the system logic unit or a test control signal from the test logic unit according to mode switching;
It is arranged at the last stage of the system logic unit and serves as an interface with the semiconductor memory unit. Either the system control signal or the test control signal is supplied from the control signal selector and sent as an access signal to the semiconductor memory unit. A flip-flop shared by the system logic unit and the test block unit;
A semiconductor integrated circuit device comprising:   The test logic unit corresponds to a pipelined access to the semiconductor memory by the flip-flop, comparing the data output value of the semiconductor memory by the access signal and an expected value corresponding to the data output value. The semiconductor integrated circuit device according to claim 1, further comprising a comparator that performs timing.   3. The semiconductor integrated circuit device according to claim 1, further comprising a plurality of the semiconductor memory units, and each of the plurality of the control signal selectors and the flip-flops correspondingly.   The one of the plurality of flip-flops feeds back the access signal to the test logic unit when the access signal accesses the corresponding semiconductor memory unit from each of the flip-flops. 4. The semiconductor integrated circuit device according to 3.   A plurality of different clocks are supplied, and further includes a clock selector that selects one of the plurality of clocks in synchronization with the control signal selector according to the mode switching and sends the selected clock to the flip-flop circuit. The semiconductor integrated circuit device according to claim 1.

Images