JP2008310923A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which replacement of a normal memory and a redundant memory can be performed without increasing wiring and a wiring property can be improved. <P>SOLUTION: The device is provided with: a test signal wiring 13 inputting a test signal to a RAM 4 and a redundant RAM 5 in a BIST mode; a normal signal wiring 12 inputting an input signal to the RAM 4 in a normal mode; and a 3 state buffer 61 connecting the normal signal wiring 12 and the test signal wiring 13 when the RAM 4 becomes defective. When the RAM 4 becomes defective, the input signal input to the RAM 4 is input to the redundant RAM 5 through the test signal wiring 13 connected to the normal signal wiring 12 by 3 state buffer 61. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test circuit and a redundant RAM for testing whether or not a RAM is defective.

  Conventionally, when a part of a memory is defective, a spare memory (hereinafter referred to as a redundant memory) is provided in the semiconductor device, and the defective memory is replaced with a redundant memory. As a result, the semiconductor device having a defective memory is relieved. Various methods for providing a redundant memory in a semiconductor device are known. For example, there is a method of providing a RAM (Random Access Memory) having redundant memory cells in advance. In this case, when a defective memory cell is generated in the RAM, the defective memory cell is replaced with a redundant memory cell. In addition, there is a method of providing a redundant RAM (for example, Patent Document 1). In this case, the defective RAM is replaced with a redundant RAM.

  Specifically, the semiconductor device described in Patent Document 1 has four SRAM macros for each memory block. The semiconductor device also includes a redundant dedicated SRAM macro, a switching control circuit, a bus switching circuit, and the like. The switching control circuit is connected to each SRAM macro via a signal line. The switching control circuit is connected to the bus switching circuit. The bus switching circuit is connected to the redundant dedicated RAM macro. The bus switching circuit is connected to each SRAM macro via a signal line. The switching control circuit controls the bus switching circuit so as to replace the defective SRAM macro and the redundant dedicated SRAM macro.

  Incidentally, some semiconductor devices have a BIST (Built In Self Test) circuit for testing a memory built in the semiconductor device. The BIST circuit has a test pattern generator and a comparator. The test pattern generator generates a test pattern and supplies the test pattern to a target circuit to be tested. The comparator compares the output pattern output from the target circuit with the expected output pattern and outputs a comparison result.

  Some semiconductor devices are called gate arrays or structured ASICs. A gate array or a structured ASIC is a circuit in which transistors and basic cells are previously mounted on a silicon wafer, and a circuit desired by a customer is formed on a base on which wiring is configured. By using a gate array or a structured ASIC, the manufacturing period is shortened compared to designing and manufacturing a semiconductor device from scratch. Therefore, in recent years, demand has increased.

A gate array or structured ASIC has a plurality of RAMs on the base. In this case, a BIST circuit is often formed in the underlying wiring layer of the base.
In addition, since a common base is prepared for various customers, an unused RAM may be generated on the base depending on the customer. If wiring is performed so that unused RAM can be used as redundant RAM, the unused RAM can be effectively used.
JP 2001-110197 A

However, depending on the customer, each RAM is often connected to a different circuit. Therefore, the adjacent RAMs are not always connected to the same bus as in Patent Document 1. In such a case, a redundant RAM is provided for each RAM, but this is not realistic.
Further, as in Patent Document 1, when a bus switching circuit is provided to replace each RAM and redundant RAM, a switching signal wiring for connecting the bus switching circuit and each RAM, a bus switching circuit and a redundant RAM are provided. Requires redundant signal wiring to connect. For this reason, as the number of RAMs increases, the number of switching signal wirings connected to the bus switching circuit increases, which is problematic in terms of wiring properties. When the BIST circuit is mounted, test signal wiring for connecting the BIST circuit and each RAM is required, and the number of wirings is further increased.

Hereinafter, the problems of the above-described prior art will be described in detail with reference to FIG. FIG. 5 shows a circuit diagram in the case where a BIST circuit is provided in the semiconductor device of Patent Document 1. A semiconductor device 200 illustrated in FIG. 5 includes a first logic circuit 201, a BIST circuit 202, a switching control circuit 203, a bus switching circuit 204, a RAM 205_1,... 205_X, a redundant RAM 206, a first selector 207_1,. , 209_X, and a second logic circuit 210. The second selector 208, the third selector 209_1,.
In the following description, the individual RAMs 205_1,... 205_X are simply described as RAM 205 unless otherwise distinguished. Similarly, the first selectors 207_1,... 207_X, the third selectors 209_1,... 209_X are simply referred to as the first selector 207 and the third selector 209, respectively, unless otherwise distinguished.

The first selectors 207_1,... 207_X are simply input when the first logic circuit 201 and the input signal wirings 211_1,... 211_X (hereinafter, the individual input signal wirings 211_1,. It is described as signal wiring 211.). The first selector 207 is connected to the BIST circuit 202 via the test signal wiring 212. The first selector 207 is connected to the RAM 205. The first selector 207 selects an input signal output from the first logic circuit 201 during normal operation and inputs the selected signal to the RAM 205. Further, the first selector 207 selects the test signal output from the BIST circuit 202 during the test operation and inputs it to the RAM 205.
The second selector 208 is connected to the BIST circuit 202 via the test signal wiring 212. The second selector 208 is connected to the bus switching circuit 204 through the redundant signal wiring 214.

  Further, the input signal wirings 211_1,... 211_X are simply referred to as switching signal wirings 213 unless the switching signal wirings 213_1,. .) Is connected to the bus switching circuit 204. The bus switching circuit 204 is connected to the redundant RAM 206 via the redundant signal wiring 214. The switching control circuit 203 is connected to the bus switching circuit 204 and the third selector 209. When one of the RAMs 205 becomes defective, the switching control circuit 203 causes the input signal output from the first logic circuit 201 to pass through the switching signal wiring 213, the bus switching circuit 204, and the redundant signal wiring 214. The bus switching circuit 204 is controlled to input to the redundant RAM 206.

  As shown in FIG. 5, the switching signal wirings 213 are connected to the bus switching circuit 204 by the number of RAMs 205. Further, the test signal wiring 212 is routed from the BIST circuit by the number of RAMs 205. In addition, the switching signal wiring 213 and the test signal wiring 212 include a plurality of address lines, a plurality of data lines, and a control signal line for designating memory cells in the RAM 205 (in FIG. 5, thick lines are drawn from a plurality of signal lines). The thin line represents one signal line.) For this reason, the number of wirings increases and the wiring property is poor.

A semiconductor device according to a first aspect of the present invention includes a test signal wiring that inputs a test signal to the normal memory and the redundant memory during a test operation, and a normal signal wiring that inputs an input signal to the normal memory during a normal operation. A connection portion that connects the normal signal wiring and the test signal wiring when the normal memory becomes defective, and an input that is input to the normal memory when the normal memory becomes defective A signal is input to the redundant memory via the test signal line connected to the normal signal line by the connection unit.
In the present invention, when the normal memory becomes defective, the normal signal wiring and the test signal wiring are connected, and the input signal input to the normal memory is input to the redundant memory via the test signal wiring. The Rukoto. That is, by using the test signal wiring for inspecting the defect of the normal memory and the redundant memory, the input signal that should be input to the defective normal memory can be input to the redundant memory. Normal memory and redundant memory can be replaced. Therefore, it is possible to test the defect of the normal memory without increasing the wiring, and to replace the normal memory and the redundant memory, thereby improving the wiring property.

  According to the present invention, the normal memory and the redundant memory can be replaced without increasing the wiring, and the wiring property can be improved.

  Hereinafter, embodiments to which the present invention can be applied will be described. Note that the present invention is not limited to the following embodiments.

A semiconductor device according to the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor device 100 according to the present invention.
As shown in FIG. 1, the semiconductor device 100 includes a first logic circuit 1, a BIST circuit 2 (test circuit), a control circuit 3 (control unit), a RAM 4_1,..., 4_X (X is an integer of 2 or more). , Redundant RAM 5 (redundant memory), signal switching circuit 6_1,..., 6_X (connection unit), first selector 7_1,..., 7_X, AND circuit 8_1,. ,..., 9_X, a second logic circuit 10, and an OR circuit 11.
The BIST circuit 2 includes a pattern generator 21, comparators 22_1, ..., 22_X, 23.
The RAMs 4_1 to 4_X function as normal memories.
In the following description, the individual RAMs 4_1,..., 4_X are simply referred to as RAM 4 unless otherwise distinguished. Similarly, signal switching circuits 6_1, ..., 6_X, first selectors 7_1, ..., 7_X, AND circuits 8_1, ..., 8_X, second selectors 9_1, ..., 9_X, comparators 22_1,..., 22_X are referred to as a signal switching circuit 6, a first selector 7, an AND circuit 8, a second selector 9, and a comparator 22, respectively, unless otherwise distinguished.

  The first logic circuit 1 is connected to the AND circuit 8 via the first selector 7. The RAM 4 is connected to the AND circuit 8. Then, an input signal from the first logic circuit 1 is input to the RAM 4 via the first selector 7 and the AND circuit 8. Here, the signal lines connecting the first logic circuit 1 and the first selectors 7_1,..., 7_X are the normal signal wirings 12_1,..., 12_X (hereinafter, particularly the individual normal signal wirings 12_1, .., 12_X is simply referred to as normal signal wiring 12). The normal signal wiring 12 includes an address line, a data line, and a control signal line. The address line transmits data specifying a memory cell in the RAM 4. The data line conveys data to be stored in the RAM 4. The control signal line transmits a signal for controlling the RAM 4. The number of address lines and data lines differs depending on the size of the RAM. For example, when the RAM 4 is 1 kword 9 bits, 10 address lines and 9 data lines are connected to the RAM 4. In FIGS. 1 and 2, a thick line indicates a wiring composed of a plurality of signal lines, and a thin line indicates one signal line.

  The first selector 7 is connected to the control circuit 3 by a test signal wiring 13. The test signal wiring 13 includes an address line, a data line, and a control signal line, like the normal signal wiring 12. The control circuit 3 is connected to the pattern generator 21. The test signal generated by the pattern generator 21 is input to the first selector 7 via the control circuit 3. That is, a test signal is input to the first selector 7 via the test signal wiring 13.

  The control circuit 3 is connected to the BIST circuit 2 via the BIST control signal line 14. The control circuit 3 controls the connection between the test signal wiring 13 and the pattern generator 21 based on a control signal input from the BIST circuit 2 via the BIST control signal line 14. Specifically, the control circuit 3 disconnects the test signal wiring 13 and the pattern generator 21 when a BIST control signal instructing the normal mode (during normal operation) is input from the BIST circuit 2. The control circuit 3 connects the test signal wiring 13 and the pattern generator 21 when a BIST control signal instructing the BIST mode (during test operation) is input from the BIST circuit 2. That is, the control circuit 3 performs control so that the test signal generated by the pattern generator 21 is input to the first selector 7 via the test signal wiring 13 in the BIST mode.

  The first selector 7 is connected to the BIST circuit 2 via the BIST control signal line 14. Then, based on the BIST control signal input from the BIST circuit 2, the first selector 7 selects either the input signal from the first logic circuit 1 to the RAM 4 or the test signal generated by the pattern generator 21. Select and input to the AND circuit 8. Specifically, the first selector 7 selects the input signal of the first logic circuit 1 to the AND circuit 8 when the BIST control signal instructing the normal mode is input from the BIST circuit 2. input. The first selector 7 selects the test signal generated by the pattern generator 21 and inputs it to the AND circuit 8 when the BIST control signal instructing the BIST mode is input from the BIST circuit 2.

  The AND circuits 8_1,..., 8_X are each provided with a switching control signal line 15_1,..., 15_X (hereinafter, when the individual switching control signal lines 15_1,. The control circuit 3 is connected via a line 15). The control circuit 3 is connected to the comparator 22. The inverted signal of the test result signal output from the comparator 22 is input to the AND circuit 8 via the control circuit 3 and the switching control signal line 15.

The signal switching circuit 6 is connected in parallel to the first selector 7. Specifically, the signal switching circuit 6 is connected between the normal signal wiring 12 and the test signal wiring 13. That is, the signal switching circuit 6 connects the normal signal wiring 12 and the test signal wiring 13.
The signal switching circuit 6 is connected to the control circuit 3 by a switching control signal line 15. The test result signal output from the comparator 22 is input to the signal switching circuit 6 via the control circuit 3 and the switching control signal line 15.

The signal switching circuit 6 is turned ON / OFF based on the test result signal output from the comparator 22. That is, the signal switching circuit 6 switches connection / disconnection between the normal signal wiring 12 and the test signal wiring 13 based on the test result signal input from the control circuit 3. Specifically, the signal switching circuit 6 is turned ON when a High test result signal is input from the comparator 22. Therefore, when a high test result signal is output from the comparator 22, the signal switching circuit 6 is turned ON, and the normal signal wiring 12 and the test signal wiring 13 are connected.
The redundant RAM 5 is connected to the test signal wiring 13. Therefore, when a high test result signal is output from the comparator 22, the signal switching circuit 6 is turned on, the normal signal wiring 12 and the test signal wiring 13 are connected, and the input signal of the first logic circuit 1 is The data is input to the redundant RAM 5 through the test signal wiring 13. As a result, the input signal from the first logic circuit 1 is input to one of the RAM 4 and the redundant RAM 5, and the RAM 4 and the redundant RAM 5 are replaced.

  In the present embodiment, as shown in FIG. 2, as the signal switching circuits 6_1,..., 6_X, for example, 3-state buffers 61_1,..., 61_X (hereinafter, individual 3-state buffers 61_1,. When not distinguishing 61_X, it is simply described as 3-state buffer 61). The switching control signal line 15 is connected to the EN terminal of the 3-state buffer 61. Therefore, when a high test result signal is input from the switching control signal line 15, the three-state buffer 61 is turned on.

The RAM 4 is connected to the second logic circuit 10 via the second selector 9. The redundant RAM 5 is connected to the second logic circuit 10 via the second selector 9. The second selector 9 is connected to the switching control signal line 15. Then, the second selector 9 selects either the output signal output from the RAM 4 or the output signal output from the redundant RAM 5 based on the test result signal input from the switching control signal line 15, Input to the second logic circuit 10.
Specifically, the second selector 9 selects an output signal output from the redundant RAM 5 and inputs it to the second logic circuit 10 when a High test result signal is input from the switching control signal line 15. To do. Therefore, when the High test result signal is output from the comparator 22, the second selector 9 selects the output signal output from the redundant RAM 5 and inputs it to the second logic circuit 10.

The RAM 4 is connected to the comparator 22. The comparator 22 is connected to the pattern generator 21. The comparator 22 compares the comparison signal output from the pattern generator 21 with the output signal output from the RAM 4, and outputs a test result signal. Specifically, when the comparator 22 compares the comparison signal output from the pattern generator 21 with the output signal output from the RAM 4 and determines that the result is normal, the test result signal becomes Low. On the other hand, when the comparator 22 determines that there is an abnormality, the test result signal becomes High. The test result signal output from the comparator 22 is input to the control circuit 3.
The comparator 22 is connected to the OR circuit 11. The test result signal output from the comparator 22 is input to the OR circuit 11.

The redundant RAM 5 is connected to the comparator 23. The comparator 23 is connected to the pattern generator 21. The comparator 23 compares the comparison signal output from the pattern generator 21 with the output signal output from the redundant RAM 5, and outputs a test result signal. Specifically, the comparator 23 compares the comparison signal output from the pattern generator 21 with the output signal output from the redundant RAM 5, and outputs a low test result signal when it is determined to be normal. . If the comparator 23 determines that there is an abnormality, it outputs a High test result signal.
The comparator 23 is connected to the control circuit 3 and the OR circuit 11. The test result signal output from the comparator 23 is input to the control circuit 3 and the OR circuit 11.

  The OR circuit 11 outputs a High result signal when a High test result signal is input from either of the comparators 22 and 23. Therefore, when the BIST circuit 2 determines that either the RAM 4 or the redundant RAM 5 is abnormal, a High result signal indicating the abnormality is output.

As shown in FIG. 3, the control circuit 3 includes a data holding device 16 (storage unit). Further, the data holding device 16 includes a data holding circuit 161 and a nonvolatile memory element 162.
The data holding circuit 161 controls the storage state of the nonvolatile storage element 162. Specifically, the data holding circuit 161 stores the test result signal output from the comparator 22 in the non-volatile storage element 162 in the BIST mode.
The nonvolatile memory element 162 stores a test result signal. Before the comparison process by the comparator 22, the nonvolatile memory element 162 stores a Low signal as a test result signal.
Then, when switching from the BIST mode to the normal mode, the control circuit 3 sends the test result signal stored in the nonvolatile memory element 162 via the switching control signal line 15 to the three-state buffer 61, the AND circuit 8, 2 to the selector 9. That is, the control circuit 3 controls the three-state buffer 61, the AND circuit 8, and the second selector 9 based on the test result signal, and replaces the defective RAM 4 with the redundant RAM 5.

Next, the operation of the semiconductor device 100 according to the embodiment of the present invention will be described.
First, the operation of the semiconductor device 100 in the BIST mode will be described. In the BIST mode, a BIST control signal for instructing the BIST mode is input to the control circuit 3 and the first selector 7 via the BIST control signal line 14.
Since the BIST control signal for instructing the BIST mode is input from the BIST circuit 2, the control circuit 3 connects the pattern generator 21 and the test signal wiring 13. Therefore, the test signal generated by the pattern generator 21 is input to the first selector 7 via the control circuit 3 and the test signal wiring 13.
The first selector 7 receives the BIST control signal for instructing the BIST mode from the BIST circuit 2, and therefore selects the test signal generated by the pattern generator 21 and inputs it to the AND circuit 8. Further, before the comparison process by the comparator 22, the nonvolatile memory element 162 stores a Low signal. Therefore, before the comparison processing by the comparator 22, the control circuit 3 outputs a Low signal as the test result signal. Then, an inverted signal of the Low signal is input to the AND circuit 8 via the switching signal line 15. That is, a high signal is input to the AND circuit 8. Therefore, the test signal generated by the pattern generator 21 is input to the RAM 4 as it is.

  Next, the output signal output from the RAM 4 is input to the comparator 22. The comparator 22 compares the output signal output from the RAM 4 with the comparison signal output from the pattern generator 21, and outputs a test result signal. Then, the test result signal is input to the control circuit 3. Then, the test result signal is stored by the data holding device 16.

Next, the operation of the semiconductor device 100 when switching from the BIST mode to the normal mode will be described.
Since the BIST mode is switched to the normal mode, a BIST control signal for instructing the normal mode is input to the control circuit 3 and the first selector 7 via the BIST control signal line 14.
Since the BIST control signal that instructs the normal mode is input from the BIST circuit 2, the control circuit 3 disconnects the pattern generator 21 from the test signal wiring 13. As a result, the test signal generated by the pattern generator 21 is not input to the first selector 7 via the control circuit 3 and the test signal wiring 13.
The first selector 7 receives the BIST control signal for instructing the normal mode from the BIST circuit 2, so selects the input signal input from the first logic circuit 1 to the RAM 4 and inputs it to the AND circuit 8. To do.

Further, the control circuit 3 inputs the test result signal stored in the nonvolatile memory element 162 to the three-state buffer 61, the AND circuit 8, and the second selector 9 via the switching control signal line 15.
At this time, if all the RAMs 4 are normal, it is determined that all the comparators 22 are normal. And the test result signal output from all the comparators 22 becomes Low. The three-state buffer 61 is turned OFF because the Low test result signal is input. For this reason, the normal signal wiring 12 and the test signal wiring 13 are not connected by the three-state buffer 61.
The AND circuit 8 receives an inverted signal of the low test result signal. That is, a high signal is input to the AND circuit 8. Further, the input signal of the first logic circuit 1 is input to the AND circuit 8 from the first selector 7. Therefore, the input signal of the first logic circuit 1 is input from the AND circuit 8 to the RAM 4 as it is.
Next, the output signal of the RAM 4 is input to the second selector 9. Here, a low test result signal is input to the second selector 9 via the switching control signal line 15. Therefore, the second selector 9 selects the output signal of the RAM 4 and outputs it to the second logic circuit 10.

On the other hand, if any one of the RAMs 4 becomes defective, any one of the comparators 22 determines that it is abnormal. Then, the test result signal of the comparator 22 becomes High. Here, for example, the case where the RAM 4_1 is defective will be described as an example. In this case, the test result signal output from the comparators 22_2,..., 22_X is Low. When a low test result signal is output from the comparators 22_2,..., 22_X, the description is omitted because it is the same as described above. On the other hand, the test result signal output from the comparator 22_1 is High. The three-state buffer 61_1 is turned on because a high test result signal is input. Therefore, the normal signal wiring 12_1 and the test signal wiring 13 are connected by the three-state buffer 61_1.
On the other hand, the input signal of the first logic circuit 1 is input to the AND circuit 8_1 from the first selector 7_1. However, an inverted signal of the High test result signal is input to the AND circuit 8_1. That is, a Low signal is input to the AND circuit 8_1. Therefore, the input from the AND circuit 8_1 to the RAM 4_1 is fixed to Low.
Thus, the RAM4_1 input signal is not input from the first logic circuit 1. Then, the input signal is input to the redundant RAM 5 via the test signal line 13 connected to the normal signal line 12_1 by the three-state buffer 61_1.

  Next, the output signal of the redundant RAM 5 is input to the second selector 9_1. Here, a high test result signal is input to the second selector 9_1 through the switching control signal line 15_1. Therefore, the second selector 9_1 selects the output signal of the redundant RAM 5 and outputs it to the second logic circuit 10. Thereby, the RAM 4_1 determined to be abnormal is replaced with the redundant RAM 5.

As described above, in the semiconductor device 100 according to the embodiment of the present invention, the test signal wiring 13 that inputs the test signal to the plurality of RAMs 4 and the redundant RAM 5 during the test operation, and the input signal to the plurality of RAMs 4 in the normal mode. When the normal signal wiring 12 to be input to the RAM 4 and the RAM 4 are defective, the three-state buffer 61 for connecting the normal signal wiring 12 and the test signal wiring 13 and the normal signal wiring 12 when the RAM 4 is defective. And a control circuit 3 for controlling the three-state buffer 61 so as to connect the test signal wiring 13 and the test signal wiring 13. When the RAM 4 becomes defective, an input signal input to the RAM 4 is input to the redundant RAM 5 via the test signal wiring 13 connected to the normal signal wiring 12 by the three-state buffer 61.
As a result, when the RAM 4 becomes defective, the normal signal wiring 12 and the test signal wiring 13 are connected, and an input signal input to the RAM 4 is input to the redundant RAM 5 via the test signal wiring 13. It will be. That is, the test signal wiring 13 for inspecting the failure of the RAM 4 and the redundant RAM 5 can be used to input the input signal that should be input to the defective RAM 4 to the redundant RAM 5. And the redundant RAM 5 can be replaced. Therefore, it is possible to test the failure of the RAM 4 without increasing the wiring, and to replace the RAM 4 and the redundant RAM 5, thereby improving the wiring property.
Specifically, in the semiconductor device 100 according to the embodiment of the present invention, the switching signal wiring 213 necessary for replacing the RAM 205 and the redundant RAM 206 in the prior art shown in FIG. The switching signal wiring 213 includes a plurality of address lines, a plurality of data lines, and a control signal line. In the prior art, the switching signal wirings 213 are required as many as the number of RAMs 205. In the semiconductor device 100 according to the present embodiment, since the switching signal wiring 213 is not required, the wiring can be greatly reduced as compared with the conventional case.

  Here, the gate array and the structured ASIC have a plurality of RAMs on a base on which transistors and basic cells are mounted in advance on a silicon wafer. In this case, the BIST circuit 2 is often formed in the upper wiring layer of the base. In addition, since a common base is prepared for various customers, an unused RAM is generated depending on the customer. Further, the individual RAMs are often connected to different circuits by customers. Therefore, adjacent RAMs are not always connected to the same bus as in the prior art. In such a case, it is not realistic to provide the redundant RAM 5 for each RAM. If the present invention is applied to a gate array or a structured ASIC, even if each RAM 4 is connected to a different circuit, test signal wirings 13 for testing the failure of each RAM 4 are connected to each RAM 4 and one redundant RAM 5. Can be used as wiring to replace Therefore, it is not necessary to adopt a RAM configuration having excessive redundancy. Further, since the wiring is not increased, the wiring property is good. Therefore, the present invention is particularly effective when applied to a gate array or a structured ASIC.

  In addition, a BIST circuit 22 is provided that generates a test signal and tests whether or not the RAM 4 is defective based on an output signal output from the RAM 4 to which the test signal is input. Thereby, it is possible to test the failure of the RAM 4 without connecting a test circuit or the like for newly testing the failure to the semiconductor device 100.

  Further, in the BIST mode for testing the failure of the RAM 4, the data holding device 16 for storing the test result by the BIST circuit 22 is provided, and the control circuit 3 is based on the test result stored in the data holding device 16. To control. As a result, when a failure is tested in the BIST mode, the defective RAM 4 is replaced with the redundant RAM 5 before the operation is started in the normal mode, so that an operation failure due to the defective RAM 4 can be prevented. .

  Further, the data holding device 16 includes a nonvolatile memory element 162, and the nonvolatile memory element 162 stores a test result. Thereby, the test result once obtained can be held regardless of whether the power is on or off. Therefore, the state in which the defective RAM 4 is replaced with the redundant RAM 5 can be maintained for a long time only by performing the test by one BIST circuit 22.

  Further, the BIST circuit 2 inputs a test signal to the redundant RAM 5 through the test signal wiring 13 and tests whether the redundant RAM 5 has a defect. Thereby, it can be checked whether the redundant RAM 5 is defective or not.

Modification 1
In the embodiment of the present invention, the data holding device 16 includes the nonvolatile memory element 162. However, a volatile memory element may be included. Modification 1 shows an example in which the data holding device 16 of the control circuit 3 is provided with a volatile memory element. In the first modification, an F / F (flip-flop) 163 will be described as an example of a volatile memory element. FIG. 4 shows an example of a schematic configuration of the control circuit 3 according to the first modification.
Since the F / F 163 is a volatile memory element, the semiconductor device 100 according to the first modification uses the BIST circuit 2 to test the RAM 4 every time the power is turned on. Therefore, even if a failure occurs in the RAM 4 after shipment, the defective RAM 4 can be replaced with the redundant RAM 5.

  In the data holding device 16 according to the first modification, since the data holding device 16 includes the F / F 163 that is a volatile storage element, the BIST circuit 2 tests the RAM 4 every time the power is turned on. As a result, even if a failure occurs in the RAM 4 after shipment of the semiconductor device 100, the defective RAM 4 and the redundant RAM 5 can be replaced.

In the present embodiment, the signal switching circuit 6 and the three-state buffer 61 are described as an example of the connection portion. However, when the RAM 4 becomes defective, the normal signal wiring 12 and the test signal wiring 13 are connected. Anything can be used.
The scope of the present invention is not limited to this embodiment, and any wiring structure can be used as long as it replaces the defective RAM 4 and redundant RAM 5 by using the test signal wiring 13. May be.

It is a circuit diagram which shows schematic structure of the semiconductor device concerning this invention. It is a circuit diagram which shows schematic structure of the semiconductor device concerning this invention. It is a block diagram which shows schematic structure of the control circuit concerning this invention. It is a block diagram which shows schematic structure of the control circuit concerning the modification 1 of this invention. It is a circuit diagram which shows schematic structure of the conventional semiconductor device.

Explanation of symbols

2 BIST circuit (test circuit)
3 Control circuit (control unit)
4_1, ..., 4_X RAM (normal memory)
5 Redundant RAM (redundant memory)
6_1,..., 6_X Signal switching circuit (connection part)
61_1,..., 61_X 3-state buffer (connection unit)
12_1,..., 12_X Normal signal wiring 13 Test signal wiring 16 Data holding device (storage unit)
162 Nonvolatile memory element

Claims (7)

A semiconductor device comprising a normal memory and a redundant memory,
Test signal wiring for inputting a test signal to the normal memory and the redundant memory during a test operation;
Normal signal wiring for inputting an input signal to the normal memory during normal operation;
A connection part for connecting the normal signal wiring and the test signal wiring when the normal memory becomes defective;
A semiconductor device in which, when the normal memory becomes defective, an input signal input to the normal memory is input to the redundancy memory via the test signal wiring connected to the normal signal wiring by the connection unit .   The semiconductor device according to claim 1, further comprising: a control unit that controls the connection unit so as to connect the normal signal line and the test signal line when the normal memory becomes defective.   The semiconductor device according to claim 1, comprising a plurality of the normal memories.   4. The test circuit according to claim 1, further comprising a test circuit that generates the test signal and tests whether the normal memory has a defect based on an output signal output from the normal memory to which the test signal is input. The semiconductor device according to any one of the above. A storage unit for storing a test result by the test circuit during a test operation;
The semiconductor device according to claim 4, wherein the control unit controls the connection unit based on a test result stored in the storage unit. The storage unit includes a nonvolatile storage element,
The semiconductor device according to claim 5, wherein the nonvolatile memory element stores the test result. The storage unit includes a volatile storage element,
The semiconductor device according to claim 5, wherein the volatile memory element stores the test result.

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