JP2008204129A - Data transfer apparatus and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for appropriately increasing the efficiency of data transfer by a serial interface. <P>SOLUTION: Serial communication speed is not increased, but data to be transferred is limited to necessaries. A reduction in unnecessary access processing also reduces wasted time for data transfer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer device and a data transfer method, and more particularly to a data transfer device and a data transfer method in serial communication.

  In today's information society, serial communication that realizes high-speed data transfer has become widespread. There is a demand for a technique that improves the transfer efficiency of data transfer in serial communication and shortens the processing time of data transmitted and received (see, for example, Patent Documents 1 to 5).

  In Patent Document 1 (Japanese Patent Laid-Open No. 11-308296), in a system in which parallel transmission data is compressed and serially transmitted, the transmission byte B is compared with the pattern data PD. A technique is described in which, when there is a mismatch, the comparison data representing non-compression and the transmission byte B are transmitted. Japanese Patent Application Laid-Open No. 2000-307948 discloses a technique for skipping data reading for items having no data in a system for serial transmission of video and audio.

  Japanese Patent Laid-Open No. 2006-244209 describes a technique for changing the communication amount of serial communication in a serial communication device of an image forming apparatus according to the state of the device (whether printing is in progress). ing. Further, in Patent Document 4 (Japanese Patent Laid-Open No. 09-319702), when accessing from a microprocessor, the address and communication information of the communication device are placed on the address bus, and the data to be communicated is placed on the data bus. Communication can be started with a single access, reducing the time required for serial communication, making the bit length of communication data variable, and reducing the communication time by having a communication bit length memory in the communication circuit. A technique related to a serial communication controller that enables serial communication is described.

  Patent Document 5 (Japanese Utility Model Laid-Open No. 04-103046) discloses a function for converting data received from a predetermined data communication line and converted into parallel data into a preset frame structure. The first means having a function for converting the code into a code or a part of these functions, and the parallel data converted by the first means are converted into serial data and transmitted to a predetermined data line. A communication control device including a second means is described.

JP-A-11-308296 JP 2000-307948 A JP 2006-244209 A JP 09-319702 A Japanese Utility Model Publication No. 04-103046

  When data transfer is performed using a serial interface, it is conceivable to shorten the data reception time by increasing the serial communication speed. However, if the communication speed is simply increased, the signal waveform may be disturbed, and the transfer efficiency of data transfer may not be improved appropriately. Further, it may be expensive to increase the communication speed.

  The problem to be solved by the present invention is to provide a technique for appropriately improving the transfer efficiency of data transfer in a serial interface.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In order to solve the above problems, a serial-parallel converter (3) that converts serial data received via a serial interface into parallel data and outputs the parallel data as a parallel request, and the serial-parallel converter A request control unit (4) for executing a parallel request supplied from (3), a registry group (5) for holding various types of LSI information read by a Read instruction specified by a command included in the serial data, Based on the address supplied from the request control unit (4), a selector (6) for selecting data from the registry group (5), and in response to the Read command, data is sent via the selector (6). And read the read data as reply data. Bytes of ALL “0” or ALL “1” are detected for each byte of the multibyte data supplied from the read control unit (7) and the read control unit (7), and the detection result A data check unit (8) that generates a multi-bit (for example, 8-bit) decoding signal indicating the transmission data, transmission reply data is generated based on the reply data and the multi-bit (for example, 8-bit) decoding signal A data transfer apparatus comprising a reply control unit (10), and a parallel-serial conversion unit (11) for generating serial data obtained by serially converting the transmission reply data and serially transferring the serial data via a serial interface Configure.

  In the data transfer device, the data check unit (8) generates a decode signal of the plurality of bits (for example, 8 bits) corresponding to Byte 7-0, and ALL “0” data or data in each Byte data, or When ALL “1” data is detected, it is preferable to have a function of setting a flag to the bit at the corresponding byte position (for example, setting the bit at that position to “0”).

  In the data transfer device, the data check unit (8) holds the detection condition of ALL “0” or ALL “1” in the storage device, and the detection condition held in the storage device is variable. Is preferred.

  Further, if the data transfer device has a function of executing data transfer in the burst mode, the data transfer device converts serial data received via the serial interface into parallel data, and converts the parallel data into Designated by a serial-parallel converter (3) that outputs as a parallel request, a request controller (4) that executes a parallel request supplied from the serial-parallel converter (3), and a command included in the serial data A selector group (5) for holding various information of the LSI read by the read instruction and a selector for selecting data from the registry group (5) based on the address supplied from the request control unit (4) 6) and the selector (6) in response to the Read command. A read control unit (7) for reading out the data via the network, and outputting the read data as reply data; in burst mode, the address for the Read instruction is checked, and the registry value of the registry group (5) is not substantial The address check unit (9) for generating a Skip count for skipping the address of the read-unnecessary area in the next access, the reply data, and the reply data for transmission based on the Skip count And a parallel-serial converter (11) for generating serial data obtained by serially converting the reply data for transmission and serially transferring the serial data via a serial interface. Like to be Arbitrariness.

  In the data transfer device, the reply control unit (10) preferably has a function of supplying the Skip count received from the address check unit (9) to the request control unit (4). Based on the Skip count, the request control unit (4) generates an address in which a Byte unnecessary for transfer included in the registry group (5) is skipped as an unnecessary area, and the selector (6) It is preferable to perform reading by skipping the unnecessary area.

  In the data transfer apparatus, the parallel request includes a valid signal, CMD, AD, and DT, and the request control unit (4) supplies an address to be read from the registry group (5) to the selector (6). The selector (6) may have a function of reading out the data in units of 8 bytes from the registry group (5).

  In the data transfer apparatus, the various information includes setting values or log information including a mode, the registry group (5) includes a register and a buffer, and the selector (6) includes the registry group ( 5) It is preferable to have a function of reading out Bytes that are not necessary for transfer included in 5) as ALL “0” or ALL “1”.

In order to solve the above problems,
[A] converting serial data received via the serial interface into parallel data and outputting the parallel data as a parallel request;
[B] executing the parallel request;
[C] selecting data from the registry group (5) holding various pieces of LSI information based on the address obtained by executing the parallel request;
[D] reading data from the registry group (5) in response to a Read command obtained by executing a parallel request, and outputting the read data as reply data;
[E] Bytes of ALL “0” or ALL “1” are detected for each Byte of the plurality of Byte data supplied as the reply data, and a plurality of Bits (for example, 8 Bit) indicating the detection result. Generating a decoded signal of
[F] generating reply data for transmission based on the reply data and a decoded signal of the plurality of bits (for example, 8 bits);
[G] Generate serial data obtained by serially converting the reply data for transmission, and execute data transfer using a data transfer method comprising the steps of serially transferring the serial data via a serial interface.

In the data transfer method,
The step [e] includes
Generating a decoding signal of the plurality of bits (for example, 8 bits) corresponding to Byte 7-0;
When ALL “0” data or ALL “1” data is detected in the data of each byte, the bit at the byte position corresponding to the detected ALL “0” data or ALL “1” data is set to “0”. Preferably, the method includes the steps of:

When performing data transfer in burst mode,
[A] converting serial data received via the serial interface into parallel data and outputting the parallel data as a parallel request;
[B] executing the parallel request;
[C] selecting data from the registry group (5) holding various pieces of LSI information based on the address obtained by executing the parallel request;
[D] reading data from the registry group (5) in response to a Read command obtained by executing a parallel request, and outputting the read data as reply data;
[E] In burst mode, the address for the Read instruction is checked, the area of the registry value of the registry group (5) is calculated as a read unnecessary area, and the address of the read unnecessary area is skipped in the next access. Generating a Skip count to cause;
[F] generating reply data for transmission based on the reply data and the Skip count;
[G] Data may be transferred by a data transfer method including the steps of generating serial data obtained by serially converting the transmission reply data and serially transferring the serial data via a serial interface.

In the data transfer method,
[H] Based on the Skip count, generating an address in which a Byte unnecessary for transfer included in the registry group (5) is skipped as an unnecessary area;
[I] It is preferable that the data transfer method includes a step of performing reading by skipping the unnecessary area based on the address.

  The present invention can limit the data to be transferred to what is necessary without increasing the serial communication speed.

  Further, according to the present invention, it is possible to reduce unnecessary time for data transfer and improve transfer efficiency by reducing unnecessary access processing.

  In other words, since the transfer length of the serial transfer becomes variable, transfer with a reduced number of bits becomes possible, so that the transfer time can be shortened. Further, since the access to the unnecessary area is skipped, the number of processes is reduced and the transfer time can be shortened.

[First Embodiment]
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating the configuration of the data transfer system of this embodiment. The data communication system 15 according to the present embodiment includes a first serial communication control device (master) 1 and a second serial communication control device (slave) 2. The first serial communication control device 1 and the second serial communication control device 2 are connected via a serial interface (first serial interface 12 and second serial interface 13). The first serial communication control device 1 transmits a request to the second serial communication control device 2 via the first serial interface 12. Further, the first serial communication control device 1 receives a reply from the second serial communication control device 2 for this request via the second serial interface 13. Similarly, the second serial communication control device 2 receives the request transmitted from the first serial communication control device 1 via the first serial interface 12. The second serial communication control device 2 transmits a reply to this request to the first serial communication control device 1 via the second serial interface 13.

  In the data communication system 15 of the present embodiment, it is preferable that the first serial communication control device 1 and the second serial communication control device 2 have the same configuration. Therefore, in the embodiment described below, it is assumed that the first serial communication control device 1 and the second serial communication control device 2 have the same internal configuration, and corresponding to the second serial communication control device 2 The internal configuration will be described.

  Referring to FIG. 1, the second serial communication control device 2 includes a serial-parallel conversion unit 3, a request control unit 4, a registry group 5, a selector 6, a read control unit 7, a data check unit 8, The address check unit 9, the reply control unit 10, and the parallel-serial conversion unit 11 are included.

  The serial-parallel conversion unit 3 converts serial data received from the first serial communication control device 1 via the first serial interface 12 into parallel data, and supplies the parallel data to the request control unit 4. This parallel request includes a valid signal, CMD, AD, and DT.

  The request control unit 4 executes the parallel request supplied from the serial-parallel conversion unit 3. Further, the request control unit 4 passes an address to be read from the registry group 5 (the description regarding the registry group 5 will be described later) to the selector 6 (the description regarding the selector 6 will be described later). Further, the request control unit 4 passes a Read command to the read control unit 7 (the description regarding the read control unit 7 will be described later).

  The registry group 5 is various pieces of LSI information (setting values including mode, log information, etc.) read by the Read instruction specified by the command from the first serial communication control device 1, and is composed of registers and buffers. Here, the configuration of the registry group 5 will be described. FIG. 2 is a diagram illustrating the configuration of the registry group 5. FIG. 2 shows mapping of various information as an example of the registry group 5. The blank part is a Byte that is unnecessary for transfer (hereinafter referred to as an unregistered Register value), and is read as ALL “0”.

  The selector 6 selects data from the registry group 5 based on the address from the request control unit 4, and passes the read data to the read control unit 7. Data is read in units of 8 bytes. The read control unit 7 executes a Read command from the request control unit 4. The read control unit 7 reads the data via the selector 6 and transmits a reply to the reply control unit 10 as reply data. Further, the read control unit 7 transmits a reply and passes the data to the data check unit 8.

  The data check unit 8 detects ALL “0” or ALL “1” for each byte of the 8-byte data received from the read control unit 7. The data check unit 8 generates the detection result as an 8-bit decode signal (Read Byte Enable) and passes it to the reply control unit 10. This 8-bit decode signal corresponds to Byte 7-0, and when ALL “0” or ALL “1” data is detected in the data of each Byte, the Bit at the corresponding Byte position is set to “0”. The detection condition of ALL “0” or ALL “1” in the data check unit 8 is programmable by firmware or the like.

  The address check unit 9 checks the address for the Read instruction, calculates the area of the register value that does not exist (unnecessary for reading) (the blank portion of the mapping information shown in FIG. 2), and skips the address of the unneeded area for reading in the next access Generate a count to

  The reply control unit 10 receives the reply data from the read control unit 7, the 8-bit decode signal (Read Byte Enable) from the data check unit 8, and the address Skip count from the address check unit 9 to generate a reply. And supplied to the parallel-serial converter 11. The address Skip count is also passed to the request control unit 4. The request control unit 4 generates an address by skipping an unnecessary area from the address Skip count, and performs reading by skipping the unnecessary area of the registry group 5.

  The parallel-serial conversion unit 11 serially converts the reply data received from the reply control unit 10 via the serial interface, and serially transfers the reply data to the first serial communication control device 1.

  The operation of this embodiment will be described below. FIG. 3 is a timing chart illustrating the serial transfer operation. In the serial interface according to the present embodiment, data is serially transferred from the first serial communication control device 1 and the second serial communication control device 2 using STB (Strobe), TXD (Data), and TXE (End) signals. The serially transferred contents are CMD (command), AD (address), and DT (data). When performing 8-byte read access using the serial interface, 64 bits are transferred from the second serial communication control device 2 to the first serial communication control device 1 in the data portion. In the following embodiment, it is assumed that it takes 185 ns to serially transfer 1-bit data.

  In order not to transfer the data read as ALL “0” as unnecessary data, the data check unit 8 sets ALL “0” or ALL “1” to each byte of the 8 bytes data received from the read control unit 7. Perform detection.

  The data check unit 8 generates the detection result as an 8-bit decode signal (Read Byte Enable). This 8-bit decode signal corresponds to Byte 7-0, and when ALL “0” or ALL “1” data is detected in the data of each Byte, the Bit at the corresponding Byte position is set to “0”.

In this example, as an 8-bit decode signal, 10100111b
Is generated, and an unnecessary byte is notified to the reply control unit 10. The reply control unit 10 generates HD1 information of the transfer format based on this signal. FIG. 4 is a diagram illustrating a transfer format of this embodiment. As shown in FIG. 4, the transfer format of this embodiment includes HD1 information. The reply control unit 10 receives an 8-bit decode signal (HD1 information) indicating a transfer-unnecessary byte from the data check unit 8 and 8 bytes of data from the read control unit 7, and supplies a reply to the parallel-serial conversion unit 11. The parallel-serial conversion unit 11 removes the unnecessary data portion 3 bytes based on the HD1 information from the reply control unit 10 and performs serial transfer in the transfer format shown in FIG.

  In the data communication system 15 of the present embodiment, the second serial communication control device 2 (or the first serial communication control device 1) includes a Data Check mechanism for 8 Byte data. As a result, data unnecessary for transfer can be removed, and serial transfer without waste of transfer length becomes possible.

[Second Embodiment]
Below, 2nd Embodiment of this invention is described. The second embodiment is applicable when the second serial communication control device 2 (or the first serial communication control device 1) is compatible with the Burst Read method. In the Burst Read method, in order to reduce the number of request data, the address is transferred only for the first access, and for subsequent accesses, the address is not transferred, and a continuous area is read by address increment in hardware.

  In the second serial communication control device 2 of the present embodiment, the address check unit 9 calculates an access unnecessary area from the address received from the request control unit 4 at the time of Burst Read. The specific operation of the second embodiment will be described below corresponding to the case where Burst Read is performed from address 00h in the area shown in FIG.

  As shown in FIG. 2, addresses 00h to 38h are areas that do not require reading. When Burst Read is executed from address 00h, the address check unit 9 calculates an access unnecessary area. In this case, the address 40h is calculated as a Skip count. The reply control unit 10 receives this Skip count from the address check unit 9 and returns a reply to the parallel-serial conversion unit 11.

  FIG. 5 is a diagram illustrating a configuration of a transfer format in the second embodiment. The reply control unit 10 receives the skip count (HD1 information) and 8 bytes of data from the read control unit 7 and supplies Reply to the parallel-serial conversion unit 11. The parallel-serial conversion unit 11 performs serial transfer in the transfer format shown in FIG. 5 based on the HD1 information from the reply control unit 10.

  The reply control unit 10 also passes the Skip count as an increment value to the request control unit 4.

Since the request control unit 4 performs reading by setting the next access as 40h, it is possible to perform processing in which a total of seven accesses from 08 to 38h are skipped.

  The conventional address increment is performed in a fixed 8h. Conventionally, since + 8h is incremented, an area that does not need to be read is also accessed, and transfer is wasted. In this embodiment, in such a case, it is possible to skip up to the next effective address by checking the read address. Therefore, the number of unnecessary reads is reduced, and access to unnecessary areas is skipped to reduce the number of processes.

[Comparative example]
Hereinafter, for comparison, the configuration and operation in the case where the processing by the data check unit 8 and the address check unit 9 is not performed in the first serial communication control device 1 of the above-described embodiment will be described.

  In the first serial communication control device 1 in the comparative example, serial transfer is performed using the maximum number of bits. In this case, data transfer is performed with the maximum transfer length even though the number of bits does not need to be transferred. As a result, transfer may take time. When serial transfer is performed using the maximum number of bits, this data may include bytes that are not necessary for transfer (intangible register values: for example, ALL “0” data or ALL “1” data). . As described above, when unnecessary data is included in the transfer, the serial transfer takes much time.

  In the data communication system 15 in the comparative example, the data serially transferred from the first serial communication control device 1 is serial-parallel converted by the serial-parallel conversion unit 3 of the second serial communication control device 2 and taken into the request control unit 4. It is. The second serial communication control device 2 reads the data from the registry group 5 in response to an instruction from the first serial communication control device 1 by the request control unit 4, passes it to the reply control unit 10, performs parallel-serial conversion, and performs first-serial conversion. Return to the communication control device 1.

As described in the description of FIG. 2 above, this data may include an insignificant register value. For example, an operation when 8-byte read access is performed on data corresponding to the address 40h (dotted line frame) shown in FIG. 2 will be described. In this case, the actual register value is 5 bytes, and 3 bytes in the blank portion are inexistent register values and are read as All “0”.

  When the request control unit 4 receives an 8-byte read command from the serial-parallel conversion unit 3, the request control unit 4 instructs the read control unit 7 to read data. The read control unit 7 reads data from the registry group 5 via the selector 6. The data read from this address 40h is 8 bytes, but includes 3 bytes in the blank portion.

  FIG. 7 shows a reply transfer format at the time of 8-byte read access in the comparative example. As shown in FIG. 7, in the case of the transfer format of the second serial communication control device 2 that does not include the data check unit 8 or the address check unit 9, the reply data is transferred as 8 bytes. For this reason, transfer is performed even for the blank 3 bytes All “0” data which does not need to be transferred. Therefore, the serial transfer takes time corresponding to the unnecessary data. In this comparative example, when it takes 185 ns to transmit 1-bit data, data transfer corresponding to the format shown in FIG. 7 takes 14.8 μs.

  In the above-described embodiment, since the transfer length of serial transfer is variable, transfer with a reduced number of bits is possible. Therefore, the transfer time can be shortened compared with the conventional data transfer apparatus. Specifically, in the case of 3 bytes unnecessary data, 3 bytes transfer is not required for the format of FIG. At this time, since HD1 is transferred in the format shown in FIG. 4, the transfer is reduced by 2 bytes from the comparative example (14.8 μs → 11.84 μs). Further, since the access to the unnecessary area is skipped, the number of processes is reduced, and the transfer time can be shortened as compared with the conventional data transfer apparatus (in this embodiment, 32 times → 19 times).

FIG. 1 is a block diagram illustrating the configuration of the data communication system 15 of this embodiment. FIG. 2 is a block diagram illustrating the configuration of the registry group 5 of this embodiment. FIG. 3 is a timing chart illustrating the serial transfer operation. FIG. 4 is a diagram illustrating a transfer format of this embodiment. FIG. 5 is a diagram illustrating a transfer format of the second embodiment. FIG. 6 is a block diagram illustrating the configuration of the comparative example. FIG. 7 is a diagram illustrating a transfer format in the comparative example.

Explanation of symbols

1 ... 1st serial communication control device (master)
2 ... Second serial communication controller (slave)
DESCRIPTION OF SYMBOLS 3 ... Serial-parallel conversion part 4 ... Request control part 5 ... Registry group 6 ... Selector 7 ... Read control part 8 ... Data check part 9 ... Address check part 10 ... Reply control part 11 ... Parallel-serial conversion part 12 ... 1st Serial interface 13 ... second serial interface 15 ... data communication system

Claims (11)

A serial-parallel converter that converts serial data received via the serial interface into parallel data and outputs the parallel data as a parallel request;
A request control unit for executing a parallel request supplied from the serial-parallel conversion unit;
A registry group that holds various types of LSI information read by a Read instruction specified by a command included in the serial data;
Based on the address supplied from the request control unit, a selector for selecting data from the registry group,
In response to the Read command, a read control unit that reads data through the selector and outputs the read data as reply data;
Data for detecting Bytes of ALL “0” or ALL “1” for each Byte of the Byte data supplied from the read control unit, and generating a decoding signal of Bytes indicating the detection result A check section;
A reply control unit that generates reply data for transmission based on the reply data and the decoded signal of the plurality of bits;
A data transfer apparatus comprising: a parallel-serial conversion unit that generates serial data obtained by serially converting the reply data for transmission and serially transfers the serial data via a serial interface. The data transfer device according to claim 1, wherein
The data check unit
The multi-bit decode signal is generated corresponding to Byte 7-0, and when ALL “0” data or ALL “1” data is detected in the data of each Byte, a flag is set in the Bit at the corresponding Byte position. A data transfer device. The data transfer device according to claim 2, wherein
The data check unit
The detection condition of ALL “0” or ALL “1” is held in the storage device,
The detection condition held in the storage device is variable. A data transfer device that performs data transfer in burst mode,
A serial-parallel converter that converts serial data received via the serial interface into parallel data and outputs the parallel data as a parallel request;
A request control unit for executing a parallel request supplied from the serial-parallel conversion unit;
A registry group that holds various types of LSI information read by a Read instruction specified by a command included in the serial data;
Based on the address supplied from the request control unit, a selector for selecting data from the registry group,
In response to the Read command, a read control unit that reads data through the selector and outputs the read data as reply data;
In the burst mode, the address for the Read instruction is checked, the area of the registry value that does not exist in the registry group is calculated as a read unnecessary area, and a Skip count is generated that skips the address of the read unnecessary area in the next access. An address check section;
A reply control unit that generates reply data for transmission based on the reply data and a Skip count;
A data transfer apparatus comprising: a parallel-serial conversion unit that generates serial data obtained by serially converting the reply data for transmission and serially transfers the serial data via a serial interface. The data transfer device according to claim 4, wherein
The reply control unit includes:
Supplying the Skip count received from the address check unit to the request control unit;
The request control unit
Based on the Skip count, an address is generated by skipping unnecessary bytes included in the registry group as an unnecessary area,
The selector is
A data transfer apparatus for performing reading by skipping the unnecessary area. In the data transfer device according to any one of claims 1 to 5,
The parallel request includes a valid signal, CMD, AD and DT,
The request control unit
Supplying an address to be read from the registry group to the selector,
The selector is a data transfer device that reads the data from the registry group in units of 8 bytes. The data transfer device according to any one of claims 1 to 6,
The various information includes setting values including mode or log information,
The registry group includes a register and a buffer,
The data read device, wherein the selector reads, as the ALL “0” or the ALL “1”, a byte unnecessary for transfer included in the registry group. [A] converting serial data received via the serial interface into parallel data and outputting the parallel data as a parallel request;
[B] executing the parallel request;
[C] selecting data from a group of registries holding various pieces of LSI information based on addresses obtained by executing parallel requests;
[D] in response to a Read instruction obtained by executing a parallel request, reading data from the registry group, and outputting the read data as reply data;
[E] Bytes of ALL “0” or ALL “1” are detected for each Byte of the multiple Byte data supplied as reply data, and a multi-bit decode signal indicating the detection result is generated. And steps to
[F] generating reply data for transmission based on the reply data and the decoded signal of the plurality of bits;
[G] A data transfer method comprising: generating serial data obtained by serially converting the reply data for transmission, and serially transferring the serial data via a serial interface. The data transfer method according to claim 8, wherein
The step [e] includes
Generating the multi-bit decode signal corresponding to Byte 7-0;
When ALL “0” data or ALL “1” data is detected in the data of each byte, the bit at the byte position corresponding to the detected ALL “0” data or ALL “1” data is set to “0”. A data transfer method including the step of: A data transfer method for performing data transfer in burst mode,
[A] converting serial data received via the serial interface into parallel data and outputting the parallel data as a parallel request;
[B] executing the parallel request;
[C] selecting data from a group of registries holding various pieces of LSI information based on addresses obtained by executing parallel requests;
[D] in response to a Read instruction obtained by executing a parallel request, reading data from the registry group, and outputting the read data as reply data;
[E] In the burst mode, the address for the Read instruction is checked, the area of the registry value having no registry group entity is calculated as a read unnecessary area, and the skip count for skipping the address of the read unnecessary area in the next access A step of generating
[F] generating reply data for transmission based on the reply data and the Skip count;
[G] A data transfer method comprising: generating serial data obtained by serially converting the reply data for transmission, and serially transferring the serial data via a serial interface. The data transfer method according to claim 10, further comprising:
[H] Based on the Skip count, generating an address that causes a Skip included as an unnecessary area to be included in the registry group to be transferred;
[I] A data transfer method comprising a step of performing reading by skipping the unnecessary area based on the address.

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