JP2008198692A - Manufacturing method of electro-optic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of an electro-optic device capable of exposing and forming a resist pattern for flattening a global step by a photo mask independent of a region, a circuit configuration or the like having the global step. <P>SOLUTION: The electro-optic device is manufactured by the manufacturing method including processes of: forming a third interlayer insulation film 43 on the surface of a pixel circuit element layer 7a and a peripheral circuit element layer 7b formed on a substrate 10 (a); polishing the surface of the third interlayer insulation film 43 (b) to form a resist 65 (c); exposing a pattern to the resist 65 by means of an exposure system having a focal depth smaller than twice a step d on the surface of the resist 65 while being focused on a height corresponding to an upper level of the step of the resist 65 (d); then developing the pattern to remove it and etching the third insulation film 43 using the resist 65 having the pattern formed as a mask, and thereafter peeling the resist 65. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an electro-optical device having a substrate on which a circuit element layer is formed.

  One of the electro-optical devices is a liquid crystal device having a configuration in which an element substrate having a circuit element layer and a counter substrate disposed opposite to the circuit substrate layer are provided, and liquid crystal is sealed between the element substrate and the counter substrate. is there. In general, the circuit element layer includes a TFT (Thin Film Transistor) element, various wirings, and the like. For example, the circuit element layer is formed in the pixel circuit element layer of the liquid crystal device and around the pixel area. Peripheral circuit element layer.

  By the way, when an insulating film is laminated on the circuit element layer, if it is polished and flattened by CMP (Chemical Mechanical Polishing) or the like, the difference in element density between the pixel circuit element layer and the peripheral circuit element layer is caused. As a result, a step called a global step may remain on the surface of the insulating film. Specifically, the insulating film may remain thick in the peripheral circuit element layer formation region where the element density is high, and a step may be formed between the insulating film in the pixel circuit element layer formation region. As means for flattening the level difference, Patent Document 1 describes a method of etching a part of an insulating film after forming a resist pattern on the insulating film.

JP-A-11-67767

  However, in order to implement such a method, there is a problem that a region where a global step is generated must be investigated in advance and a photomask for exposing the resist in accordance with the region must be prepared. In particular, when the circuit arrangement on the substrate differs depending on the model, the photomask must be created for each model.

  The present invention has been made in view of the above problems, and in order to flatten the global level difference with a photomask that does not depend on the region where the global level difference occurs or the circuit layout, etc., due to one of the effects of the present invention. This resist pattern can be exposed and formed.

  An electro-optical device manufacturing method according to the present invention is a method for manufacturing an electro-optical device having a substrate on which a circuit element layer is formed, the step of forming an insulating film on the circuit element layer, A step of polishing the surface, a step of applying a resist on the insulating film, and a predetermined pattern on the resist by focusing on the height corresponding to the upper stage so that the lower stage of the steps of the resist is not focused. A step of exposing the resist, a step of developing the predetermined pattern of the resist, a step of etching the insulating film using the resist on which the predetermined pattern is formed as a mask, and a step of peeling the resist It is characterized by that.

  According to such a method, in the step of exposing a predetermined pattern on the resist, the pattern is transferred by exposure only to the upper region of the resist, that is, the resist region corresponding to the upper step of the global step of the insulating film. At this time, the resist region corresponding to the lower step of the resist, that is, the lower step of the global step of the insulating film is not focused, and the pattern is not transferred by exposure. By etching the insulating film using the resist pattern thus obtained as a mask, only a portion corresponding to the upper stage of the global step (for example, a portion having a large film thickness) is etched and thinned. Therefore, even if the polished insulating film has a step such as a global step, the step can be flattened. In addition, the pattern transfer area by exposure is not selected by the mask pattern of the photomask (reticle) used for exposure, but by focusing the image only on the upper stage of the resist by narrowing the depth of focus of the exposure system. Automatically selected. For this reason, it is not necessary to consider the circuit arrangement, the global level distribution tendency, and the like in the creation of the photomask. For example, a uniform mask pattern may be formed on the entire surface. Therefore, it is not necessary to prepare a different photomask for each type of electro-optical device to be manufactured, and the manufacturing process of the electro-optical device can be simplified, and the manufacturing cost can be reduced.

  The circuit element layer may include a pixel circuit element layer in the pixel area and a peripheral circuit element layer in the peripheral circuit area arranged around the pixel area. In such a case, the polished insulating film may have a global step due to a difference in element density between the pixel circuit element layer and the peripheral circuit element layer. Can be eliminated.

  In the electro-optical device manufacturing method, the step of exposing the predetermined pattern may be performed using an exposure system having a depth of focus smaller than twice the thickness of the step of the resist. According to such a method, in the step of exposing a predetermined pattern on the resist, it is possible to focus only on the upper stage of the resist and not to focus on the lower stage of the resist. As a result, the pattern can be transferred by exposure only to the upper stage of the resist.

  In the electro-optical device manufacturing method, the step of exposing the predetermined pattern may include a step of exposing the resist to a plurality of circular patterns. In this way, the insulating film can be etched into a flatter state. In addition, the depth of focus of the exposure system can be easily controlled.

  In the method for manufacturing the electro-optical device, it is preferable that the circular pattern has a diameter that is equal to or less than a height of the step and is formed at an interval substantially equal to the diameter. In this way, the depth of focus of the exposure system can be easily made smaller than twice the step in the thickness direction of the resist surface.

  In the method for manufacturing the electro-optical device, the step of exposing the predetermined pattern may include a step of exposing the resist to a plurality of slit-shaped patterns using a stepper. In this way, the insulating film can be etched into a flatter state. In addition, the depth of focus of the exposure system can be easily controlled.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings shown below, the dimensions and ratios of the components are appropriately different from the actual ones in order to make the components large enough to be recognized on the drawings.

(A. Electro-optical device)
1A and 1B are diagrams showing a liquid crystal device 100 as an electro-optical device of the present invention, in which FIG. 1A is a plan view, and FIG. FIG.

  The liquid crystal device 100 includes an element substrate 10a including a substrate 10 such as quartz or glass, and a counter substrate 20a including a substrate 20 such as quartz or glass. The element substrate 10 a and the counter substrate 20 a are bonded to each other with a frame-shaped sealing material 52 facing each other, and a liquid crystal 50 is sealed in a region partitioned by the sealing material 52. This region is a region in which pixels contributing to display and pixel circuits constituting the pixels are formed, and is hereinafter also referred to as a pixel circuit region 8a.

  A data line driving circuit 101 and an external connection terminal 102 are formed along one side of the element substrate 10a in a region outside the sealing material 52, and the scanning line driving circuit 104 is formed along two sides adjacent to the one side. Is formed. The data line driving circuit 101 and the scanning line driving circuit 104 are configured by elements formed on the substrate 10. Hereinafter, the formation region of these circuits is also referred to as a peripheral circuit region 8b. In the corner portion of the counter substrate 20a, a vertical conductive material 106 for providing electrical continuity between the element substrate 10a and the counter substrate 20a is disposed.

  The element substrate 10a is generally manufactured from a disk-shaped wafer having a size that includes a plurality of element substrates 10a. FIG. 2 is a plan view showing a wafer 10A serving as a base of the element substrate 10a. Components corresponding to the plurality of element substrates 10a are formed in the wafer 10A. The counter substrate 20a is bonded to the wafer 10A, and the wafer 10A is broken to manufacture the liquid crystal device 100.

  FIG. 3 is a cross-sectional view showing the pixel structure of the liquid crystal device 100 in detail. Hereinafter, the configuration of the liquid crystal device 100 in the pixel circuit region 8a and the peripheral circuit region 8b will be described in detail with reference to FIG.

  First, the configuration in the pixel circuit region 8a will be described. Various components are arranged in a laminated structure in the pixel circuit region 8a of the element substrate 10a. This stacked structure includes, in order from the bottom, a first layer including the scanning line 11a, a second layer including the TFT element 30 and the like, a third layer including the storage capacitor 70, a fourth layer including the data line 6a and the like, and a shield layer 73. And the like, and a sixth layer including the pixel electrode 9a, the alignment film 16, and the like. In addition, a base insulating film 12 is provided between the first layer and the second layer, a first interlayer insulating film 41 is provided between the second layer and the third layer, and a gap between the third layer and the fourth layer. Includes a second interlayer insulating film 42, a third interlayer insulating film 43 between the fourth layer and the fifth layer, a fourth interlayer insulating film 44 between the fifth layer and the sixth layer, Each is provided to prevent the above-mentioned respective layers from being short-circuited. The various insulating films 12, 41, 42, 43, and 44 are also provided with contact holes for electrically connecting the constituent elements of the respective layers. Hereinafter, each of these elements will be described in order from the lower layer.

  The first layer includes, for example, a simple metal, an alloy containing at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate of these, or conductive polysilicon is provided. One scanning line 11a is electrically connected to the TFT elements 30 of a plurality of pixels, and has a function of simultaneously controlling ON / OFF of these TFT elements 30. The scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, and also has a function of blocking light entering the TFT element 30 from below. As a result, generation of light leakage current in the semiconductor layer of the TFT element 30 can be suppressed, and high-quality image display without flicker or the like can be achieved.

  In the second layer, the TFT element 30 including the gate electrode 3a is provided. The TFT element 30 has an LDD (Lightly Doped Drain) structure. The TFT element 30 includes the above-described gate electrode 3a, a channel region 1a of a semiconductor layer in which a channel is formed by an electric field from the gate electrode 3a, a high concentration source region 1b, a high concentration drain region 1c in the semiconductor layer, and the like. These components are made of, for example, a polysilicon film. The TFT element 30 also includes an insulating film 2 that functions as a gate insulating film that insulates the gate electrode 3a from the semiconductor layer.

  A relay electrode 79 is formed on the second layer as the same film as the gate electrode 3a. Since the relay electrode 79 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.

  A base insulating film 12 made of, for example, a silicon oxide film is provided on the scanning line 11 a and below the TFT element 30. The base insulating film 12 is provided with contact holes on both sides of the semiconductor layer in plan view. A side wall 3b that electrically connects the scanning line 11a and the gate electrode 3a is formed at the contact hole. The side wall portion 3b can block light incident on the semiconductor layer of the TFT element 30 from the side.

  In the third layer, a storage capacitor 70 is provided. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode electrically connected to the high concentration drain region 1c of the TFT element 30 and the pixel electrode 9a, and a capacitor electrode 72 as a fixed potential side capacitor electrode. It has a configuration in which the dielectric films (not shown) are arranged to face each other. More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. Further, the lower electrode 71 has a function as a pixel potential side capacitance electrode, and also has a function of relay-connecting the pixel electrode 9 a and the high concentration drain region 1 c of the TFT element 30. This relay connection is made through the relay electrode 79 as described later. The capacitor electrode 72 functions as a fixed potential side capacitor electrode of the storage capacitor 70. The capacitor electrode 72 is electrically connected to a shield layer 73 having a fixed potential in order to make this a fixed potential.

  The dielectric film included in the storage capacitor 70 is composed of a silicon oxide film such as a relatively thin HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride film having a film thickness of about 5 to 200 nm, for example. Is done. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film, the better as long as the reliability of the film is sufficiently obtained. In this embodiment, the dielectric film has a two-layer structure in which a silicon oxide film is a lower layer and a silicon nitride film is an upper layer.

  On the TFT element 30 or the gate electrode 3a and the relay electrode 79, and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole for electrically connecting the high concentration drain region 1c of the TFT element 30 and the lower electrode 71 constituting the storage capacitor 70, and a relay with the lower electrode 71 are relayed. A contact hole for electrically connecting the electrode 79 is opened.

  A second interlayer insulating film 42 made of, for example, a silicon oxide film is formed on the first interlayer insulating film 41, that is, between the third layer and a fourth layer described later. The second interlayer insulating film 42 is provided with a contact hole for electrically connecting a shield layer relay layer 61 described later and a capacitor electrode 72 which is an upper electrode of the storage capacitor 70. In addition, a contact hole for electrically connecting the high concentration source region 1b of the TFT element 30 and the data line 6a through the second interlayer insulating film 42 and the first interlayer insulating film 41, and a second to be described later. A contact hole for electrically connecting the relay electrode 62 and the relay electrode 79 is formed.

  A data line 6a is provided in the fourth layer. The data lines 6a are formed in a stripe shape in a direction perpendicular to the scanning lines 11a in plan view. The data line 6a is formed, for example, by laminating a composite titanium layer, an aluminum layer, and a titanium nitride layer in which titanium and titanium nitride are laminated in this order. The data line 6a is electrically connected to the high concentration source region 1b of the TFT element 30 through the contact hole described above. In the fourth layer, a shield layer relay layer 61 and a second relay electrode 62 are formed as the same film as the data line 6a.

  Among the components of the pixel circuit region 8a, the components from the first layer to the fourth layer are collectively referred to as “pixel circuit element layer 7a” below. The pixel circuit element layer 7a corresponds to the circuit element layer in the present invention.

  A shield layer 73 is formed on the fifth layer. The shield layer 73 is formed in a grid-like region so as to cover the data line 6a and the scanning line 11a in a plan view. The shield layer 73 is set to a fixed potential by being electrically connected to a constant potential source. The constant potential source may be a positive power source or a negative power source supplied to the data line driving circuit 101, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20a. The presence of such a shield layer 73 can eliminate the influence of capacitive coupling that occurs between the data line 6a and the pixel electrode 9a. Since the shield layer 73 is formed in a lattice shape, it is possible to suppress this so that unnecessary capacitive coupling does not occur in the portion where the scanning line 11a extends.

  Further, a third relay electrode 74 as a relay layer is formed on the fifth layer as the same film as the shield layer 73. The third relay electrode 74 has a function of relaying an electrical connection between the second relay electrode 62 and the pixel electrode 9a. Note that the space between the shield layer 73 and the third relay electrode 74 is not continuously formed in a planar shape, but is formed so as to be divided for patterning.

  The shield layer 73 and the third relay electrode 74 described above have a two-layer structure of a lower layer made of aluminum and an upper layer made of titanium nitride. The lower layer of the third relay electrode 74 is electrically connected to the second relay electrode 62, and the upper layer is connected to the pixel electrode 9a. Since the shield layer 73 and the third relay electrode 74 include aluminum that is relatively excellent in light reflection performance and include titanium nitride that is relatively excellent in light absorption performance, the shield layer 73 and the third relay electrode 74 can function as a light shielding layer. Such a light shielding function can be similarly applied to the capacitor electrode 72 and the data line 6a described above. The shield layer 73, the third relay electrode 74, the capacitor electrode 72, and the data line 6 a form a part of the laminated structure constructed on the element substrate 10 a, and the upper light shielding that blocks light incident on the TFT element 30 from above. Functions as a membrane.

  A third interlayer insulating film 43 made of a silicon oxide film or the like is formed on the data line 6a and below the shield layer 73. The surface of the third interlayer insulating film 43 has irregularities due to the shape of the constituent elements below the fourth layer when formed, but is polished and flattened by subsequent CMP or the like. A contact hole for electrically connecting the shield layer 73 and the shield layer relay layer 61 and the third relay electrode 74 and the second relay electrode 62 are electrically connected to the third interlayer insulating film 43. A contact hole is opened. The third interlayer insulating film 43 corresponds to the insulating film in the present invention.

  On the sixth layer, transparent pixel electrodes 9a made of ITO (Indium Tin Oxide) or the like are formed in a matrix, and an alignment film 16 is laminated on the pixel electrodes 9a. A fourth interlayer insulating film 44 made of a silicon oxide film or the like is formed under the pixel electrode 9a. The fourth interlayer insulating film 44 is also polished and planarized by CMP or the like. In the fourth interlayer insulating film 44, a contact hole for electrically connecting the pixel electrode 9a and the third relay electrode 74 is opened.

  On the other hand, the counter substrate 20 a includes a substrate 20, a counter electrode 21 formed on the substrate 20, and a polyimide-based alignment film 22. The counter electrode 21 is made of a transparent conductive film such as ITO. The alignment films 16 and 22 are rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules contained in the liquid crystal 50.

  Next, the configuration in the peripheral circuit region 8b will be described. Similarly to the pixel circuit region 8a, the peripheral circuit region 8b of the element substrate 10a also has a layer structure from the first layer to the sixth layer, a base insulating film 12 and a first interlayer insulating film 41 formed between these layers. , Second interlayer insulating film 42, third interlayer insulating film 43, and fourth interlayer insulating film 44. Similar to the pixel circuit region 8a, the surface of the third interlayer insulating film 43 has irregularities due to the shape of the components below the fourth layer when formed, but is polished and flattened by subsequent CMP or the like. Has been. In addition, since the materials, characteristics, and the like of the respective constituent elements are the same as those of the pixel circuit region 8a, the description thereof is omitted.

  The circuit elements in the peripheral circuit region 8b are composed of TFT elements 30 provided in the second layer, various wirings, and the like. In FIG. 3, the wiring 63 formed in the fourth layer is electrically connected to the high concentration source region 1b of the TFT element 30, and the wiring 64 formed in the fourth layer is connected to the high concentration drain region 1c. Is formed. Further, the wiring 64 is further electrically connected to a wiring 75 formed in the fifth layer. The TFT element 30 and various wirings are electrically connected via contact holes provided in an insulating film as appropriate. However, these are examples, and the wiring in the peripheral circuit region 8b may be formed in any of the first layer to the sixth layer as necessary, and a relay layer or the like is also provided as appropriate. A circuit in the peripheral circuit region 8b is configured by various elements including the TFT element 30 and various wirings.

  Here, among the components of the peripheral circuit region 8b, the components from the first layer to the fourth layer are collectively referred to as “peripheral circuit element layer 7b” below. The peripheral circuit element layer 7b corresponds to the circuit element layer in the present invention, like the pixel circuit element layer 7a.

  In the pixel circuit region 8a described above, the TFT element 30 that blocks transmitted light, various wirings that are electrically connected thereto, a relay layer, and the like are not formed in the region where the pixel electrode 9a is formed. On the other hand, there is no such area in the peripheral circuit area 8b, and various elements are arranged with high density. Therefore, the components in the peripheral circuit region 8b are formed at a higher density than the components in the pixel circuit region 8a.

  The liquid crystal device 100 having the above-described configuration operates as follows. That is, first, when a drive voltage is applied between the pixel electrode 9 a and the counter electrode 21, an electric field is generated in the layer of the liquid crystal 50. Here, the driving voltage is applied by the functions of various elements such as the data line driving circuit 101 and the scanning line driving circuit 104 formed in the peripheral circuit region 8b and the TFT element 30 formed in the pixel circuit region 8a. Is done. The liquid crystal 50 changes the alignment direction according to the electric field. The liquid crystal device 100 is a device that performs display based on a polarization conversion function corresponding to the alignment direction of the liquid crystal 50 and a polarization selection function of a polarizing plate (not shown) disposed outside the liquid crystal device 100.

(B. Electro-optical device manufacturing method)
Next, a method for manufacturing the liquid crystal device 100 as an electro-optical device will be described with reference to FIGS. Among these, FIG. 4 is a flowchart which shows the manufacturing method of the liquid crystal device 100 of this embodiment. 5 and 6 are cross-sectional views in the manufacturing process of the liquid crystal device 100. FIG. Hereinafter, it demonstrates along the flowchart of FIG.

  In step S1, the pixel circuit element layer 7a and the peripheral circuit element layer 7b described above are formed on the substrate 10. This step is performed using various film forming techniques such as atmospheric pressure or reduced pressure CVD, spin coating, photolithography, and the like, and is performed on the substrate 10 in the state of the wafer 10A shown in FIG. As a result, the pixel circuit element layer 7a is formed in the pixel circuit area 8a, and the peripheral circuit element layer 7b having an element density higher than that of the pixel circuit element layer 7a is formed in the peripheral circuit area 8b (FIG. 5A). )). In FIGS. 5 and 6, the detailed description of the components in the pixel circuit element layer 7a and the peripheral circuit element layer 7b is omitted.

  Next, in step S2, a third interlayer insulating film 43 is formed so as to overlap the pixel circuit element layer 7a and the peripheral circuit element layer 7b (FIG. 5A). This step is performed by forming a silicate glass film, a silicon nitride film, a silicon oxide film, or the like by, for example, normal pressure or low pressure CVD. The third interlayer insulating film 43 is formed in a state having irregularities, reflecting the shapes of the surface layers of the pixel circuit element layer 7a and the peripheral circuit element layer 7b.

  Next, in step S3, the surface of the third interlayer insulating film 43 is polished (FIG. 5B). More specifically, the entire surface of the third interlayer insulating film 43 formed on the substrate 10 is polished by CMP or the like. As a result, fine irregularities on the surface of the third interlayer insulating film 43 are removed and planarized. However, a step called a global step remains on the surface of the third interlayer insulating film 43 due to a difference in element density between the pixel circuit element layer 7a and the peripheral circuit element layer 7b. Specifically, the third interlayer insulating film 43 remains thick in the peripheral circuit region 8b having a high element density, and a step is formed between the third interlayer insulating film 43 in the pixel circuit region 8a. That is, in the third interlayer insulating film 43, a global step is formed with the peripheral circuit region 8b as the upper stage and the pixel circuit region 8a as the lower stage. According to the manufacturing method of this embodiment, this global level | step difference can be planarized by implementing process S4 and subsequent steps.

  In step S4, a photosensitive resist 65 is formed on the third interlayer insulating film 43 (FIG. 5C). The resist 65 may be either a positive type or a negative type, but in this embodiment, a positive type resist 65 is used. The resist 65 is formed with a step reflecting the global step of the third interlayer insulating film 43. That is, the surface position of the resist 65 is relatively higher in the peripheral circuit region 8b than in the pixel circuit region 8a. Hereinafter, the surface position of the resist 65 formed in the peripheral circuit region 8b is “upper”, and the surface position of the resist 65 formed in the pixel circuit region 8a and having a relatively low surface position is “ Sometimes referred to as “lower”. Hereinafter, the distance between the upper and lower steps of the surface of the resist 65, that is, the height along the thickness direction of the step on the surface of the resist 65 is d (hereinafter, simply referred to as “step d on the surface of the resist 65”). Also called). In this embodiment, d is about 0.5 μm. Here, the level difference d on the surface of the resist 65 corresponds to the “thickness of the level difference of the resist” in the present invention.

  In the subsequent step S5, the resist 65 is exposed and developed. More specifically, first, the resist 65 is irradiated (exposed) with light by a stepper via a photomask (reticle) 80, whereby the mask pattern formed on the photomask 80 is reduced and transferred (FIG. 5D).

  FIG. 7 is a plan view showing the shape of the photomask 80. A plurality of circular mask patterns 81 are formed in the photomask 80, and light is transmitted at the positions of the mask patterns 81. Therefore, a large number of patterns similar to the circular mask pattern 81 are reduced and transferred onto the resist 65. In this specification, a pattern formed on the photomask 80 is referred to as a “mask pattern”, and a pattern transferred onto the resist 65 by exposure is simply referred to as a “pattern”. The size of the mask pattern 81 is designed so that the diameter of the pattern when it is reduced and transferred onto the resist 65 substantially coincides with the step d on the surface of the resist 65. In addition, each mask pattern 81 is formed in a matrix with an interval substantially equal to its diameter. That is, the array pitch between the light transmitting portions corresponding to the mask pattern 81 and the other light shielding portions is 1: 1 along the rows and columns passing through the diameter of the mask pattern 81. The photomask 80 is capable of evenly transferring a pattern similar to the circular mask pattern 81 over the entire wafer 10A (FIG. 2), and the arrangement of the pixel circuit region 8a and the peripheral circuit region 8b. No mask pattern corresponding to is provided.

  The stepper having the photomask 80, the condenser lens, and the exposure machine corresponds to the exposure system in the present invention. Such an exposure system optimizes the function of the exposure machine, the type of resist 65 and the film forming process thereof, the size and arrangement pitch of the mask pattern 81 of the photomask 80, and the like, so that the level difference d on the surface of the resist 65 is improved. Can be adjusted to have a depth of focus that is less than 2 times.

  FIG. 8 is a diagram for explaining the depth of focus in this specification. The horizontal axis of the figure shows the deviation of the position of the resist 65 placed in the exposure system from the theoretical focal position of the exposure system, and the vertical axis of the pattern transferred to the resist 65 placed at that position. Show dimensions. Curves 90 and 91 correspond to transfer results when photomasks having different mask patterns are used. A curve 90 corresponds to the exposure system of the present embodiment, and is a transfer result when the photomask 80 is used. A curve 91 corresponds to a transfer result when a photomask having a larger mask pattern is used.

  The origin of the horizontal axis is the theoretically focused position in the exposure system. Now, paying attention to the curve 90, it can be seen that the pattern is transferred onto the resist 65 with the largest dimension at this position. When the resist 65 is displaced in a direction away from the focal position (in the positive direction of the horizontal axis in the figure), the size of the transferred pattern gradually decreases as the focal point is deviated, and is displaced by 0.5 μm. It will not be transcribed. Similarly, even when the resist 65 is displaced in the direction approaching the focal position (minus direction on the horizontal axis in the figure), the size of the transferred pattern gradually decreases, and when the resist 65 is displaced by 0.5 μm, the pattern is not transferred. . On the horizontal axis of the figure, the range where the pattern is transferred is called the depth of focus. In other words, the pattern is not transferred when the surface of the resist 65 is deviated by 1/2 of the focal depth from the theoretical focal position. A curve 90 corresponds to the exposure system of this embodiment. Therefore, the focal depth 90d of the exposure system of this embodiment is 1 μm. This corresponds to twice the level difference d on the surface of the resist 65.

  As for the curve 91 corresponding to the photomask having a mask pattern larger than the photomask 80, the pattern transferred at each position is larger than the curve 90, and the focal depth 91d is larger than the focal depth 90d. As described above, the depth of focus depends on the size of the mask pattern. In addition to this, the depth of focus also depends on the function of the exposure apparatus, the type of resist 65 and its film forming process, the pitch of the mask pattern, and the like.

  Returning to FIG. 4, in the step S5, exposure is performed focusing on the upper stage of the resist 65 (that is, the surface of the resist 65 in the peripheral circuit region 8b). As a result, the pattern is transferred to the resist 65 in the peripheral circuit region 8b by exposure. On the other hand, as described above, the depth of focus of the exposure system of this embodiment is 1 μm, and the step d on the surface of the resist 65 is 0.5 μm. Therefore, the lower stage of the resist 65 (that is, the surface of the resist 65 in the pixel circuit region 8a). ), The focus is shifted by half the depth of focus. Therefore, the pattern is not transferred to the resist 65 in the pixel circuit region 8a. As a result, in step S5, a predetermined pattern can be exposed on the resist 65 while focusing on the height corresponding to the upper stage so that the lower stage of the steps of the resist 65 does not focus. That is, the pattern is transferred by exposure only to the portion corresponding to the upper stage of the resist 65, that is, the portion corresponding to the upper stage of the global step, and the exposed portion 65a is altered (FIG. 5D). Thereafter, development is performed, and the exposed portion 65a of the resist 65 is removed. Thus, a pattern is formed on a part of the resist 65.

  Next, in step S6, the third interlayer insulating film 43 is etched using the patterned resist 65 as a mask. This step can be performed by wet etching using, for example, hydrogen fluoride or buffered hydrofluoric acid as an etchant. As a result, as shown in FIG. 6A, the third interlayer insulating film 43 is eroded and thinned from the vicinity of the opening formed in the resist 65 by exposure and development. Here, since the opening of the resist 65 is provided only in the peripheral circuit region 8b, only the portion corresponding to the upper stage of the global step in the third interlayer insulating film 43 can be thinned. Etching in this step is preferably isotropic etching because the third interlayer insulating film 43 is also etched in the planar direction. Then, by continuing the etching, the third interlayer insulating film 43 in the peripheral circuit region 8b is finally thinned as shown in FIG. 6B, and the third interlayer insulating film 43 and the surface of the pixel circuit region 8a are thinned. The heights will match. That is, the global step remaining in the third interlayer insulating film 43 can be eliminated and planarized.

  In the subsequent step S7, the resist 65 is stripped (FIG. 6C). As a result, the third interlayer insulating film 43 having a flat surface without a global step is exposed on the substrate 10.

  Thereafter, the element substrate 10a is completed through steps S8 to S10. That is, a fifth layer including the shield layer 73 and the like is formed on the third interlayer insulating film 43 in step S8. Next, in step S9, a fourth interlayer insulating film 44 is formed on the fifth layer, and the surface thereof is polished and planarized by CMP or the like. At this time, the global step in the lower layer of the fourth interlayer insulating film 44 has been eliminated, and therefore no global step is generated in the fourth interlayer insulating film 44. In step S10, a sixth layer including the pixel electrode 9a and the like is formed on the fourth interlayer insulating film 44.

  In the subsequent step S11, the counter substrate 20a is bonded to the element substrate 10a, and the liquid crystal 50 is sealed between the element substrate 10a and the counter substrate 20a. This process is performed by bonding the counter substrate 20a corresponding to a single product to a large number of element substrates 10a formed on the wafer 10A through the sealing material 52, and then injecting the liquid crystal 50. Alternatively, after the liquid crystal 50 is dropped onto the wafer 10A on which a large number of element substrates 10a are formed, the same wafer on which a large number of counter substrates 20a are formed may be bonded together. A method of attaching the counter substrate 20a after dropping the required amount of the liquid crystal 50 in this way is called ODF (One Drop Fill).

  Finally, in step S12, the wafer 10A is broken to cut out a portion corresponding to the single liquid crystal device 100, and an external circuit such as an FPC (Flexible Printed Circuit), a frame, or the like is mounted.

  The liquid crystal device 100 is completed through the above steps. According to such a manufacturing method, even if a part of the third interlayer insulating film 43 after polishing remains thick and a global step is generated, the thick remaining portion can be selectively etched and thinned. As a result, global steps can be eliminated. Further, according to the manufacturing method, a resist mask used for etching the third interlayer insulating film 43 can be easily formed. That is, the region where the pattern is transferred to the resist 65 by exposure is not selected by the mask pattern of the photomask (reticle) 80, but is focused only on the upper stage of the resist 65 by narrowing the depth of focus of the exposure system. Automatically selected by imaging. For this reason, in the creation of the photomask 80, it is not necessary to consider the circuit arrangement, the global step distribution tendency, etc., and a uniform mask pattern may be formed on the entire surface. Therefore, it is not necessary to prepare a different photomask 80 for each model of the liquid crystal device 100 to be manufactured, the manufacturing process of the liquid crystal device 100 can be simplified, and the manufacturing cost can be reduced.

  As mentioned above, although embodiment of this invention was described, various deformation | transformation can be added with respect to the said embodiment in the range which does not deviate from the meaning of this invention. As modifications, for example, the following can be considered.

(Modification 1)
In the above embodiment, the third interlayer insulating film 43 is etched to eliminate the global level difference, but the present invention is not limited to this. In carrying out the present invention, it is sufficient that the insulating film formed on the circuit element layer is etched. As the insulating film, for example, a fourth interlayer between the fifth layer and the sixth layer is used. The insulating film 44 can also be selected.

  In this case, the pixel circuit element layer 7a, the peripheral circuit element layer 7b, the third interlayer insulating film 43, and the fifth layer are formed on the substrate 10, and then the fourth interlayer insulating film 44 is formed and planarized by CMP or the like. To do. At this time, a global step remains in the fourth interlayer insulating film 44. Here, by performing steps corresponding to step S4 to step S7 of the above embodiment (that is, formation of resist 65, exposure / development, etching of fourth interlayer insulating film 44, peeling of resist 65), the fourth interlayer insulating film 44 global steps can be eliminated. Then, the liquid crystal device 100 can be manufactured by performing the process S10 (sixth layer formation) and subsequent steps of the above embodiment.

(Modification 2)
In the above-described embodiment, the depth of focus of the exposure system is about twice the level difference d on the surface of the resist 65, but may be smaller than twice the level difference d. One method for this is to make the diameter of the mask pattern 81 of the photomask 80 smaller than the step d. In addition, the depth of focus can be reduced by adjusting the function of the exposure device, the type of resist 65 and its film formation process, the pitch of the mask pattern 81, and the like. In this way, the range of the resist 65 in the thickness direction in which the pattern is imaged during exposure can be narrowed, so that it is possible to reliably prevent the pattern from being transferred to the lower stage of the resist 65.

(Modification 3)
In the above-described embodiment, the exposure is performed using the photomask 80 having the circular mask pattern 81, but the purpose is not limited to this, and a depth of focus smaller than twice the step difference d on the surface of the resist 65 is realized. If possible, photomasks having various mask patterns can be used. FIG. 9 is a plan view showing an example of the shape of the photomask according to this modification. The photomask 80a shown in this figure is provided with a plurality of equally spaced slit-shaped mask patterns 81a vertically and horizontally. That is, the photomask 80a includes a lattice-shaped light-transmitting portion and square light-shielding portions arranged in a matrix. Even when such a photomask 80a is used, a pattern can be selectively transferred only to the upper stage of the resist 65.

2A and 2B show a liquid crystal device as an electro-optical device, in which FIG. The top view which shows the wafer used as the base | substrate of an element substrate. FIG. 4 is a cross-sectional view illustrating a pixel structure of a liquid crystal device in detail. 6 is a flowchart showing a method for manufacturing a liquid crystal device. (A) to (d) are cross-sectional views in the manufacturing process of the liquid crystal device. (A) to (c) are cross-sectional views in the manufacturing process of the liquid crystal device. The top view which shows the shape of a photomask. The figure for demonstrating the depth of focus in this specification. The top view which shows the shape of the photomask which concerns on the modification of this invention.

Explanation of symbols

  7a ... pixel circuit element layer, 7b ... peripheral circuit element layer, 8a ... pixel circuit area, 8b ... peripheral circuit area, 10, 20 ... substrate, 10A ... wafer, 10a ... element substrate, 20a ... counter substrate, 30 ... TFT element , 41 ... first interlayer insulating film, 42 ... second interlayer insulating film, 43 ... third interlayer insulating film, 44 ... fourth interlayer insulating film, 50 ... liquid crystal, 52 ... sealing material, 65 ... resist, 80, 80a ... Photomask (reticle), 81, 81a ... mask pattern, 90d, 91d ... depth of focus, 100 ... liquid crystal device as electro-optical device, 101 ... data line driving circuit, 104 ... scanning line driving circuit.

Claims (5)

A method of manufacturing an electro-optical device having a substrate on which a circuit element layer is formed,
Forming an insulating film on the circuit element layer;
Polishing the surface of the insulating film;
Applying a resist on the insulating film;
A step of exposing a predetermined pattern on the resist while focusing on a height corresponding to the upper stage so that the lower stage of the steps of the resist does not focus on the lower stage;
Developing the predetermined pattern of the resist;
Etching the insulating film using the resist in which the predetermined pattern is formed as a mask;
And a step of stripping the resist. A method of manufacturing the electro-optical device according to claim 1,
The method of manufacturing an electro-optical device, wherein the step of exposing the predetermined pattern is performed using an exposure system having a depth of focus smaller than twice the thickness of the step of the resist. A method of manufacturing an electro-optical device according to claim 1 or 2,
The step of exposing the predetermined pattern includes a step of exposing a plurality of circular patterns to the resist. A method for manufacturing the electro-optical device according to claim 3,
The method of manufacturing an electro-optical device, wherein the circular pattern has a diameter that is equal to or less than a height of the step, and is formed at an interval substantially equal to the diameter. A method of manufacturing an electro-optical device according to claim 1 or 2,
The step of exposing the predetermined pattern includes a step of exposing a plurality of slit-shaped patterns to the resist with a stepper.

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