JP2008198668A - Flattening and polishing method and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flattening and polishing method by which higher flattening and polishing can be established for CMP polishing, and to provide a method of manufacturing a semiconductor device using the flattening and polishing method. <P>SOLUTION: This method is used to flatten and polish a target wafer. A polishing slurry containing abrasive grains and an encapsulated surfactant 36 with a coated surface is employed to flatten the surface to be polished. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a planarization polishing method used in a semiconductor manufacturing process and a semiconductor device manufacturing method.

  In a manufacturing process of a semiconductor device, so-called semiconductor integrated circuit, a CMP (chemical mechanical polishing) technique is widely used as a technique for planarizing the surface in a process of forming an STI (shallow trench isolation) region as an element isolation region. It has been. An STI region in a semiconductor device is generally formed as shown in FIG.

  First, as shown in FIG. 6A, a silicon nitride (SiN) film 2 is formed on the surface of the silicon semiconductor substrate 1.

  Next, a resist mask (not shown) having a required pattern having an opening in a portion corresponding to the STI region to be formed on the silicon nitride film 2 is formed by using a photolithography technique. Then, as shown in FIG. 6B, the silicon nitride film 2 is patterned by dry etching through a resist mask, and a groove 3 having a required pattern is formed on the silicon substrate 1 by dry etching using the silicon nitride film 2 as a mask. Here, the region where the silicon nitride film 2 is formed becomes a later element formation region.

  Next, as shown in FIG. 6C, a silicon oxide (SiO 2) film 4 is embedded in the trench 3 by CVD (chemical vapor deposition). At this time, the silicon oxide film 4 is also deposited on the substrate surface other than the groove 3 (that is, the silicon nitride film 2).

  Next, as shown in FIG. 6D, the silicon oxide (SiO 2) film deposited on the substrate surface other than the groove 3 is polished and removed by the CMP method. As a result, an STI region (element isolation region) 5 in which the silicon oxide film 4 is buried in the trench 3 is formed. In this subsequent process, the silicon nitride film 2 is removed, and a required semiconductor element is formed in the removed region.

  With the recent high integration of semiconductor elements, the planarization performance required for the CMP process (so-called STI-CMP process) in forming the STI region 5 has become increasingly severe and has been used for polishing an oxide film conventionally. With the silica-based slurry, it has become impossible to satisfy the required performance. This is because the area ratio of the silicon nitride film 2 on which the silicon oxide film 4 is formed in a convex shape, that is, the subsequent element formation region is not uniform within the semiconductor wafer surface. A high convex silicon oxide film 4a is formed in a region where the area ratio of the silicon nitride film 2 is high, and a low convex silicon oxide film 4b is deposited in a region where the area ratio of the silicon nitride film 2 is low.

  Specifically, the area ratio of the convex portion is determined from the selection ratio of the silicon nitride film 2 and the silicon oxide film 4 until the polishing removal of the silicon oxide film 4a in the region where the convex portion has a high area ratio is completed. The silicon oxide film 4 in the groove 3 in the low region is excessively polished. By this excessive polishing, as shown in FIG. 6E, so-called dishing 6 occurs, and the flattening deteriorates. Deterioration of flatness leads to deterioration of reliability and yield of semiconductor elements.

  As a measure for improving the flatness of the STI-CMP process, there is a polishing method using a ceria-based slurry containing ceria (cerium oxide: CeO2) abrasive grains and an additive (so-called surfactant). This is because, in the convex portion of the surface to be polished, the additive is desorbed due to pressure concentration during polishing and the polishing proceeds, but in the concave portion having a low pressure, polishing is suppressed by the adsorbed additive. It is intended to obtain a highly flat polished surface. This ceria-based slurry is advantageous not only in terms of flatness but also in terms of polishing rate and selection ratio as compared with a silica-based slurry.

  As a highly planarized polishing method using ceria abrasive grains, for example, there is Patent Document 1. This is achieved by using a CMP polishing liquid (slurry for polishing) containing a cerium oxide particle and a surfactant having selective adsorption properties of a silicon nitride film to achieve high planarization by reducing the polishing rate of the silicon nitride film by the surfactant. This is a method of polishing.

JP 2004-14624 A

  By the way, even in the STI-CMP process using the ceria-based slurry, it is still difficult to obtain a highly flat polished surface due to the influence of the density difference in the element formation region. This will be further described with reference to FIGS. 7A and 7B. Now, a ceria-based slurry containing ceria abrasive grains 12 and a surfactant 13 acting on the abrasive grains 12, that is, a ceria-based slurry containing a surfactant 13 having a protective action on the film surface of the silicon oxide film 4 in the recess 3 is obtained. The case of using will be described. As shown in FIGS. 7A and 7B, when ceria-based slurry was used and polishing was started by pressing the polishing pad 11 against the surface to be polished, a high pressure was applied to the convex portion 4a, so the surfactant 13 was removed. In the convex portion 4a, selective polishing proceeds, and the surface to be polished becomes flat. However, since the ceria-based slurry has a higher polishing rate of the silicon oxide film 4 than the silicon nitride film 2, the dishing 6 becomes prominent especially in the region where the element isolation region 5 is large, and the flatness deteriorates.

  In addition, the ceria-based slurry has a problem that there are more scratches than the silica-based slurry, and in particular, when the scratch is generated in the element formation region and reaches the underlying Si substrate, there is a problem that the yield is deteriorated.

  In view of the above, the present invention provides a planarization polishing method that enables higher planarization polishing in polishing using the CMP method, and a method for manufacturing a semiconductor device using the planarization polishing method. It is.

The flattening polishing method according to the present invention is a flattening polishing method for flatly polishing a wafer to be polished, using a polishing slurry containing abrasive grains and a surfactant whose surface is coated and encapsulated. The surface to be polished is polished flat.
In this flattening polishing, the polished surface is preferably an oxide film.

  In the method of manufacturing a semiconductor device according to the present invention, an oxide film deposited on a region other than a groove portion of a semiconductor substrate is encapsulated with abrasive grains and a surface when forming an STI region serving as an element isolation region. It has the process of grind | polishing flatly using the slurry for grinding | polishing containing surfactant.

  In the present invention, since the surfactant contained in the slurry for polishing is encapsulated with the surface coated, the capsule is broken and selectively supplied to the low area requiring protection by the surfactant. In other parts, the capsule is not broken and there is no protective action, so that the polishing proceeds. Thereby, highly planarized polishing can be performed.

According to the planarization polishing method of the present invention, the surfactant acts directly on the surface to be polished in accordance with the progress of polishing within the surface of the wafer to be polished, so that highly flattening polishing can be performed.
According to the method for manufacturing a semiconductor device according to the present invention, the surfactant acts directly on the surface to be polished in accordance with the progress of polishing in the surface of the wafer to be polished. Polishing can be performed.

  Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to this example.

  The present embodiment is a case where the present invention is applied to the manufacture of a semiconductor device, a so-called semiconductor integrated circuit, and is particularly a case where the present invention is applied to planarization polishing of an oxide film by a CMP method when forming an element isolation region by the STI. As an example, the film to be polished is a high-density plasma SiO 2 film.

  FIG. 1 shows a schematic configuration of a general CMP apparatus used for polishing according to the present embodiment. The CMP apparatus 21 has a surface plate 23 that is rotatably arranged around a rotation shaft 22, and a polishing pad 24 is disposed on the surface plate 23. A slurry supply pipe 26 for supplying the polishing slurry 25 according to the present embodiment is disposed above the polishing pad 24. The object to be polished to be flattened, in this example, the semiconductor wafer 27 is placed so that the surface to be polished is in contact with the polishing pad 24. The polishing head 28 is brought into contact with the back surface of the semiconductor wafer 27 with a required load. The polishing head 28 is configured to be rotated around the shaft 29 together with the semiconductor wafer 27 while applying a required load to the semiconductor wafer 27.

  As shown in FIG. 3A, the semiconductor wafer 27 which is a wafer to be polished has the same configuration as that of FIG. 6C described above. That is, a silicon nitride (SiN) film 31 is formed on the surface of the silicon semiconductor substrate 27a, and a resist mask having an opening having a required pattern is formed on the silicon nitride film 31 by using a photolithography technique. Then, the silicon nitride film 31 is patterned by dry etching, and a groove 32 having a required pattern is formed in the silicon substrate 27a using the silicon nitride film 31 as a mask. The groove 32 is formed at a position corresponding to the STI region that becomes the element isolation region. Next, a silicon oxide (SiO 2) film 33 is deposited on the entire surface of the substrate by a CVD method so as to be embedded in the trench 32. In this manner, the area ratio of the silicon oxide film 31 is small in the vicinity of the convex areas 33a and 33b of the silicon oxide film, that is, the convex area 33a having a large area ratio and a large height in accordance with the density difference of the area ratio of the silicon nitride film 31. The semiconductor wafer 27 in which the convex region 33b having a small height is mixed is formed.

Next, using the CMP apparatus 21 shown in FIG. 1, together with the planarization polishing method according to one embodiment of the present invention, the semiconductor wafer 27 is planarized and polished using this planarization polishing method to form the STI region. A method for manufacturing a semiconductor device will be described.
In the present embodiment, first, as shown in FIG. 3A, the semiconductor wafer 27 is placed so that the surface to be polished is in contact with the polishing pad 24 of the CMP apparatus 21.

  Next, as shown in FIGS. 3A and 3B, the semiconductor wafer 27 to be polished held by the polishing head 28 while dripping the polishing slurry 25 according to the present embodiment from the slurry supply pipe 26 onto the polishing pad 24. The surface is pressed against the polishing pad 24 and a load is applied to start polishing. The polishing slurry 25 includes ceria abrasive grains (not shown) and a surfactant 36 (indicated by white circles) whose surface is coated and encapsulated. This surfactant is a surfactant having a protective effect on the silicon oxide film 33 to be polished. The encapsulated surfactant 36 is formed by coating a surfactant 37 with a coating wall 35 as shown in FIG. A specific slurry configuration will be described later.

In the state of FIG. 3A, the polishing slurry 25 is supplied onto the polishing pad 24, whereby the encapsulated surfactant 36 adheres to the entire surface including the convex regions 33a and 33b of the surface to be polished.
In the state of FIG. 3B, the encapsulated surfactant 36 adhering to the convex regions 3a and 33b on the surface to be polished is pushed away by touching the polishing pad 24 and adheres to the concave region 33c on the surface to be polished.

  Next, as shown in FIG. 3C, polishing of the convex region proceeds. In this polishing, the convex area 33b having a low area ratio and a small height progresses quickly, so that as shown in the enlarged view A, pressure and shear are applied to the encapsulated surfactant 36 present in the vicinity of the convex area. It takes power.

  Then, as shown in FIG. 4D, the capsule is broken by the pressure and shearing force, and the surfactant 37 (shown by a black circle) is released.

  As shown in FIG. 3E, since the concave portion 33c is protected by the surfactant 37 even during the polishing of the convex region 33a, the progress of the polishing is suppressed.

As shown in FIG. 4F, as the polishing of the convex region 33a progresses, the capsule is broken and the surfactant 37 acts sequentially. Then, as shown in FIG. 4G, the entire surface is flatly polished regardless of the difference in the area ratio of the silicon nitride film 31, that is, the so-called density difference in the element formation region, and is flattened when the silicon nitride film 31 is reached. The polishing process ends. As a result, a highly planarized polished surface can be obtained. In this manner, dishing does not occur and a good STI region 38 is formed.
Thereafter, the silicon nitride film 31 is removed, a required semiconductor element is formed in the element formation region from which the silicon nitride film 31 has been removed, and a target semiconductor device is obtained.

  In FIGS. 3A to 4G, the planarization polishing reaching the silicon nitride film 31 is performed by one polishing process, but may be performed by two other processes.

  Next, a planarization polishing method according to another embodiment of the present invention in which planarization is performed by two polishing processes, and a semiconductor device manufacturing method using the planarization polishing method will be described. In the present embodiment, a polishing slurry in which a surfactant encapsulated in a ceria-based slurry is added is used for the first time until the convex regions 33a and 33b of the surface to be polished by the silicon oxide film 33 are flattened. Polishing process is performed. That is, the process of FIG. 4F described above is followed by a process of planarizing the silicon oxide film 33 of FIG. Next, a second polishing process is performed until the silicon nitride film 31 is exposed, and the high planarization polishing of FIG. 4G is completed.

  The second polishing process may be performed only with a polishing slurry to which no surfactant is added. In the second polishing process, the surface to be polished at the time of polishing is already flattened and the remaining film is thin, so that polishing is completed while maintaining a highly flat polished surface without using a surfactant. (See FIG. 3G). As the slurry used for the second polishing treatment, the same ceria-based slurry as that used in the first polishing may be used, or a silica-based, alumina-based, or iron nitrate-based slurry may be used. In particular, from the viewpoint of scratching, it is desirable to finish the polished surface with a silica-based slurry.

  Next, a specific polishing method using a polishing slurry containing a coated and encapsulated surfactant will be described. Here, the required amount of the coated surfactant is added to the polishing slurry in advance, 2 wt% in this example, and polishing is performed under the following conditions while supplying this polishing slurry onto the wafer to be polished through the polishing pad. Do.

[Polishing conditions]
Plate rotation speed: 100rpm
Polishing head rotation speed: 107 rpm
Polishing pressure: 300 hPa
Polishing pad conditioner conditions: Ex-situ
Ceria-based slurry flow rate (surfactant 2wt% added): 200cc / min

  The particle diameter of the ceria particles, that is, the particle diameter of cerium oxide (CeO2) can be 50 nm to 250 nm.

  Here, an acidic ceria-based slurry is used as the polishing slurry, but silica, alumina, iron nitrate-based slurry, or the like may be used in addition thereto. The addition amount of the coated surfactant is desirably in the range of 0.1 to 10 wt%. This numerical value is a concentration within a range where good polishing characteristics (flatness, prefecture speed) can be obtained.

  As a method for supplying the coated surfactant, it can be premixed and supplied to the polishing slurry. In addition, the coated surfactant may be supplied as an aqueous solution separately from the polishing slurry, or the surfactant supply pipe for supplying the surfactant aqueous solution may be connected to the slurry supply pipe for supply. Also good.

  The surfactant to be coated has an action of suppressing polishing of the oxide film. Here, alkylbenzene sulfonate is used as the surfactant, but in addition to that, fatty acid sodium salt, alkyl sulfate, sulfate ester salt, fatty acid potassium salt, polyoxyethylene alkyl ether sulfate, fatty acid ester, α-olefin sulfone. Acid salts, monoalkyl phosphate esters, alkane sulfonates, amino acids, polyacrylates, ammonium polyacrylates, polycarboxylic acid ammonium salts, sulfosuccinic acid diester salts, alkylamine hydrochlorides, alkyl ether sulfonates, etc. May be used.

  As the coating material for encapsulating, a material that can be easily coated and does not alter the surfactant and the polishing slurry is used. Here, polyurethane resin is used, but other polymer materials that do not react with surfactants or slurries, for example, polystyrene resin, polyester resin, polyurea resin, polyamide resin, polyethylene resin, polyvinyl alcohol resin, polycarbonate Resins, melamine resins, urea resins, gelatin and the like may be used.

  The size of the surfactant molecule is about 2 nm to 3 nm. The size of the coated surfactant can be about 10 nm to 5000 nm. The surfactant encapsulated here includes a single surfactant or a coating in which a plurality of single surfactants are aggregated. The thickness of the coating is set so as to have a mechanical strength that is broken by the polishing pressure and shearing force applied to the coating film during polishing. That is, the mechanical strength of the coating film is set to be equal to or lower than the mechanical strength due to the polishing pressure and the shearing force.

  Surfactant coating (coating) methods are roughly classified into chemical methods, physicochemical methods, and mechanical methods. Examples of the surfactant coating method in the present invention include a seamless encapsulation method, an interfacial polymerization method, an in-situ polymerization method, a submerged drying method, a coacervation method, a spray drying method, and a dry mixing method. In particular, as a method for coating a liquid surfactant, an interfacial polymerization method, an in-situ polymerization method, a coacervation method, a seamless encapsulation method, and the like are suitable.

1. Chemical method (forms coating film by chemical reaction).
In the interfacial polymerization method, separate monomers are supplied from both the dispersed phase and the dispersion medium, and a coating film is formed by a polymerization reaction on the surface of the dispersed phase, that is, the interface.
In the in-situ polymerization method, a monomer or other reactant is supplied only from either the dispersed phase or the dispersion medium, and a coating film is formed by a polymerization reaction on the surface of the core material.

2. Physicochemical method (forms coating film by precipitation, solidification, etc.).
In the coacervation method, a core material is dispersed in a solution in which a resin serving as a coating material is dissolved, and the resin is deposited around the core material to form a coating film.
In the in-liquid drying method, a coating material solution containing a core substance is dispersed in a liquid medium to prepare an emulsion, and the solvent is removed by decompression or heating to form a coating film.

3. Mechanical method (mechanically forming a coating film).
In the spray drying method, the core material is added, the coating material solution is sprayed and sprayed into hot air, and the liquid crossing the coating material is evaporated to form a coating film.

4). Other methods.
In the seamless encapsulation method, a seamless coating film is formed using a material that becomes spherical due to interfacial tension when a liquid is dropped.

  According to the planarization polishing method and the semiconductor device manufacturing method according to the above-described embodiment, since the polishing slurry to which the coated surfactant is added is used, the surfactant which is the additive is the surface of the wafer to be polished. It selectively acts directly on the surface to be polished according to the progress of the polishing inside. As a result, high planarization polishing not depending on the density difference in the element formation region can be performed with higher accuracy and efficiency, and the reliability and yield of the semiconductor element are improved. In addition, since the amount of the surfactant used can be minimized, the manufacturing cost of the semiconductor device can be reduced.

  As described above, the planarization polishing method according to the present embodiment is performed using a polishing slurry containing abrasive grains and a surfactant whose surface is coated and encapsulated. In this polishing method, polishing pressure and shearing force are applied to the encapsulated surfactant adhering to the concave portion near the convex portion as the convex portion of the surface to be polished is flattened, destroying the coating film and releasing the interfacial chemical. The progress of polishing in the vicinity is selectively suppressed. In the wafer surface, the surfactants act sequentially as the polishing of the convex portions progresses, so high planarization polishing is possible without depending on the density difference of the element formation region, and the reliability and yield of the semiconductor elements are improved. .

  In Patent Document 1 described above, the surfactant acts selectively depending on the film type of the surface to be polished, whereas the present invention allows the surfactant to act by the progress of polishing due to the difference in density of the pattern. Therefore, flattening is performed on the surface to be polished made of the same material before the different material (for example, if the surface to be polished is SiO2, the different material is SiN) is exposed to the surface to be polished. It is possible to perform polishing with higher flatness. Furthermore, since the remaining film is thin when high-flat polishing is completed, it is possible to perform final polishing with, for example, a conventional silica-based slurry with few scratches while maintaining flatness. As a result, scratches can be reduced, and the degree of freedom in the polishing process is expanded.

  In the above example, the planarization polishing method of the present invention is applied to polishing a semiconductor wafer. However, it can also be applied to polishing other substrates (wafers), that is, substrates having an oxide film on the surface to be polished.

It is a block diagram which shows schematic structure of the CMP apparatus applied to this invention. It is typical sectional drawing of the encapsulated surfactant. 1A to 1C are manufacturing process diagrams (part 1) illustrating an embodiment of a planarization polishing method according to the present invention and a method of manufacturing a semiconductor device using the polishing method. DG is the manufacturing process figure (the 2) which shows one Embodiment of the planarization grinding | polishing method which concerns on this invention, and the manufacturing method of the semiconductor device using this grinding | polishing method. It is process drawing in the middle which shows other embodiment of the planarization grinding | polishing method which concerns on this invention, and the manufacturing method of the semiconductor device using this grinding | polishing method. A to E are manufacturing process diagrams showing an example of a manufacturing method of a semiconductor device using a conventional planarization polishing method. It is explanatory drawing with which it uses for description of the conventional grinding | polishing state.

Explanation of symbols

  21..CMP apparatus, 23..Surface plate, 24..Polishing pad, 25..Slurry for polishing, 26..Slurry supply pipe, 27..Semiconductor wafer, 28..Polishing head, 27a..Silicon semiconductor substrate 31 ... Silicon nitride film 32 ... Groove part 33 ... Silicon oxide film 33a, 33b ... Projection area 35 ... Coating wall 36 ... Encapsulated surfactant 37 ... Surfactant Agents, 38 ·· STI region

Claims (13)

A planarization polishing method for polishing a wafer to be polished flatly,
A flattening polishing method comprising polishing a surface to be polished flatly using a polishing slurry containing abrasive grains and a surfactant whose surface is coated and encapsulated. The planarization polishing method according to claim 1, wherein the surface to be polished is an oxide film. The planarization polishing method according to claim 2, wherein a ceria-based polishing slurry in which the abrasive grains are ceria particles is used. The planarization polishing method according to claim 2, wherein the surfactant is a surfactant that acts on the oxide film to be polished. The oxide film is a silicon oxide film formed over the groove portion of the substrate and on the underlying silicon nitride film other than the groove portion,
The planarization polishing method according to claim 2, wherein the surfactant is a surfactant that acts on the silicon oxide film. Using the first polishing slurry containing abrasive grains and a surface-coated and encapsulated surfactant, polishing is performed until the convex region of the surface to be polished is flattened,
The flattening polishing method according to claim 2, wherein the subsequent polishing is performed using a second polishing slurry not containing a surfactant. The planarization polishing method according to claim 1, wherein the mechanical strength of the encapsulated surfactant coating film is equal to or lower than the mechanical strength due to polishing pressure and shear force. In forming the STI region that becomes the element isolation region,
A step of polishing flatly an oxide film deposited on a region other than a groove portion of a semiconductor substrate using a polishing slurry containing abrasive grains and a surfactant whose surface is coated and encapsulated. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 8, wherein an oxide film on a region other than the groove is deposited on a base film of a nitride film. The planarization polishing method according to claim 8, wherein a ceria-based polishing slurry in which the abrasive grains are ceria particles is used. The planarization polishing method according to claim 8, wherein the surfactant is a surfactant that acts on the oxide film to be polished. Using the first polishing slurry containing abrasive grains and a surface-coated encapsulated surfactant, polishing is performed until the convex region of the oxide film is flattened,
The method for manufacturing a semiconductor device according to claim 8, wherein the subsequent polishing is performed using a second polishing slurry that does not contain a surfactant. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the mechanical strength of the encapsulated surfactant coating film is equal to or less than the mechanical strength due to polishing pressure and shearing force.

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