JP2008193301A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of simplifying a circuit and improving freedom of data input/output timing. <P>SOLUTION: An IC configuration block 104 assigns an input PORT-A to a head of an external pin in ascending order of pin number, assigns an output PORT-B to an end of the external pin number in descending order of pin number, assigns signals of a group of other functions OPTION to remaining external pins, and assigns signals of the input group PORT-A preferentially to signals of the group of other functions OPTION. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device for image processing of a digital copying machine.

  Conventionally, for example, in a semiconductor integrated circuit device used for image processing of a digital copying machine, an image processing block can support a plurality of image formats. Corresponding to such a plurality of image formats, for the input of image data to the semiconductor integrated circuit device or the output of image data from the semiconductor integrated circuit device, for example, as shown in FIG. Hereinafter, the mode is simply selected). 4A is a mode table showing modes that can be selected when image data is input (denoted as Input in the figure), and FIG. 4B is a mode table when image data is output (in the figure, Output and Output). It is a mode table showing modes that can be selected.

  First, as shown in FIG. 4A, when inputting image data, 4-bit or 8-bit pixel data can be input simultaneously from 1 to 4 lines. That is, the total bit width of pixel data that can be input simultaneously is 4 bits to 16 bits. Corresponding to these, there are five modes from 4A to 16B that can be selected at the time of input.

  On the other hand, as shown in FIG. 4B, when outputting image data, 2-bit or 4-bit pixel data can be simultaneously output from 1 to 4 lines. That is, the total bit width of pixel data that can be output simultaneously is 4 bits or 8 bits. Corresponding to these, four modes from 4A to 8B can be selected at the time of output.

  As described above, when five modes can be selected at the time of image data input and four modes at the time of output, the total bit widths at the time of input and at the time of output are all combinations of six modes of input and output. . FIG. 5 is a table in which six combinations of the five modes at the time of input and the four modes at the time of output correspond to the external pins of the semiconductor integrated circuit device virtually viewed one-dimensionally. is there. In this table, the external pins of the semiconductor integrated circuit device are virtually one-dimensionally assigned from pin number 1 to pin number 28. As shown in FIG. 5, the image data input PORT-A for image processing is assigned in correspondence with the total bit width from PORT-A1 in ascending order of pin numbers, that is, from the first. Then, the image data output PORT-B is sequentially assigned in correspondence with the pin numbers assigned to the input data in order from PORT-B1. Here, Mode 0 in FIG. 5 will be described as an example. Mode 0 is a case where 4A is selected as the mode at the time of input (see FIG. 4A) and 8A or 8B is selected as the mode at the time of output (see FIG. 4B). In Mode 0, PORT-A1 is assigned to pin number 1, and a total bit width of 4 bits is sequentially associated. That is, PORT-A4 is assigned to pin number 4. The output data PORT-B1 is continuously assigned to the pin number 5, and the total bit width of 8 bits is sequentially associated. That is, PORT-B8 is assigned to pin number 14.

  Further, after assigning input / output of image data, other functions OPTION are sequentially assigned to the remaining external pins. In the case of Mode 0, OPTION 1 to OPTION 12 are assigned to pin number 15 to pin number 28.

Further, for example, the invention according to Patent Document 1 discloses a configuration in which an external pin is switched and used for selectively using a high speed circuit and a low speed circuit.
JP 2002-352585 A

  However, in the conventional example, since the external pins of the semiconductor integrated circuit device are assigned in the order of input data and output data, there are many options for assignment to the external pins. For example, when attention is focused on PORT-B1 of the pixel data to be output (shaded display portion in FIG. 5), the result is as follows. That is, pin number 5 is in Mode 0 and Mode 3, pin number 11 is in Mode 1 and Mode 4, pin number 21 is in Mode 2 and Mode 5, and there are three choices of pin numbers for one pixel data to be output. On the other hand, focusing on the pin number 11, there are the following four data options for one pin number. That is, pixel data PORT-B5 to be output in Mode0, pixel data PORT-B1 to be output in Mode1 and Mode4, pixel data PORT-A9 and Mode3 to be input in Mode2 and Mode5, and other functions OPTION1.

  In general, as the mode increases, the number of combinations increases. If the signal to be selected is the same clock system as that of the semiconductor integrated circuit device, a selector can be provided as the logic of the synchronization circuit to select one signal. However, when the signal to be selected has an asynchronous relationship with the clock of the semiconductor integrated circuit device, the delay of the selector is added to the delay to the external pin. There is a problem that it becomes difficult.

  The present invention has been made paying attention to the above points, and an object of the present invention is to provide a semiconductor integrated circuit device capable of simplifying a circuit and increasing the degree of freedom in setting data input / output timing. .

  In order to solve the above-described problems, a semiconductor integrated circuit device according to the present invention has the following configuration.

  (1) In a semiconductor integrated circuit device having a plurality of external pins and operating in a plurality of operation modes, a plurality of signals are divided into a plurality of groups for each function, and a plurality of signals in each group are assigned to the plurality of external pins. Input / output assigning means for assigning predetermined priority for use is provided, wherein the input / output assigning means assigns a first group of the groups to the head of the external pin and a second group at the tail of the external pin. A semiconductor integrated circuit device characterized by being assigned.

  (2) The semiconductor integrated circuit device according to (1), wherein the number of signals in the group varies according to the operation mode.

  (3) In the semiconductor integrated circuit device according to (1), the input / output assignment unit assigns the first group of signals in the positive order of pin numbers assigned to the external pins, and the second group. Is assigned in the reverse order of the pin numbers assigned to the external pins.

  (4) In the semiconductor integrated circuit device according to (1), when the input / output assignment unit has output pins that are not assigned after assigning the signals of the first group and the second group, A semiconductor integrated circuit device, wherein a signal of a third group of the groups is assigned to an output pin not assigned.

  (5) In the semiconductor integrated circuit device according to (4), the input / output allocation unit gives priority to the signal of the first group over the signal of the third group, or the third group. The semiconductor integrated circuit device is characterized in that the second group of signals is prioritized over the output pins and assigned to the output pins.

  According to the present invention, since a plurality of signals are divided into a plurality of groups for each function, and the use priority order of the external pins of each group is reversed to each other, the semiconductor integrated circuit is not affected by the mode selection of other groups. Data can be placed on external pins of the circuit device. Further, it is possible to reduce the number of bits for selecting signals to be input to the external pins or for selecting signals to be output from the external pins, thereby increasing the degree of freedom in simplifying the circuit and setting the timing of data input / output. be able to.

  Hereinafter, the best mode for carrying out the present invention will be described in detail.

(Embodiment)
An embodiment of the present invention will be described with reference to a package diagram of the semiconductor integrated circuit device in FIG. 2 and a block diagram inside the semiconductor integrated circuit device in FIG.

  In FIG. 2, among the pin numbers assigned to the external pins of the semiconductor integrated circuit device, pin numbers 6, 18, 30, and 42 are assigned as power supply pins (same as VCC in the figure, and the following parentheses are also applied). It is done. Pin numbers 7, 19, 31, and 43 are assigned as ground (GND) pins. The clock (Clock1, Clock2) signal is assigned to pin number 48 and pin number 41. Further, the pin number 47 is assigned to a reset (Reset) signal, the pin number 46 is assigned to a chip select (CS) signal, the pin number 45 is assigned to a write (Wr) signal, and the pin number 44 is assigned to a read (Rd) signal.

  In FIG. 3, among the internal buses connecting the respective blocks in the semiconductor integrated circuit device 100, the address bus is represented as Adr1: 0 and the data bus is represented as Data7: 0. Signals from the external pin numbers 39 (Adr0) and 40 (Adr1) are transmitted to the address bus Adr1: 0. Further, signals of pin numbers 29 (Data 0) and 32-38 (Data 1 to Data 7) of the external pins are transmitted to the data bus Data 7: 0. The CPU interface 101 uses the register block 102 based on the signals of the CS signal (pin number 46), the Wr signal (pin number 45), the Rd signal (pin number 44), the address bus Adr0-1 and the data bus Data0-7. Write to and read from.

  The register block 102 holds a flag for controlling an operation mode (hereinafter simply referred to as a mode) of each block described later. The clock control block 103 selects a clock 1 signal (pin number 48) and a clock 2 signal (pin number 41) according to the mode, and generates a distribution clock to each block.

  The input output (hereinafter simply referred to as IO) configuration block (corresponding to input / output allocation means) 104 operates as follows. That is, input / output of the option block 105 and the image processing block 106 is input from an external pin by selecting a pixel data signal or a signal of another function according to a mode according to a flag signal output from the register block 102 or Output to external pin. PORT-A1 to A16 are data buses for transmitting input pixel data signals, PORT-B1 to B8 are data buses for transmitting output pixel data signals, and OPTIONs 1 to 16 are other functions. This is a data bus for transmitting the signals. The option block 105 is used as an IO port. The IO configuration block 104 includes PORT-A1 to A16 as input groups (corresponding to the first group), PORT-B1 to B8 as output groups (corresponding to the second group), and OPTION1 to 16 as other function groups. (Equivalent to the third group) That is, a plurality of signals are divided into a plurality of groups for each function.

  The image processing block 106 can support a plurality of image formats. Corresponding to such a plurality of image formats, for the input of image data to the semiconductor integrated circuit device 100 or the output of image data from the semiconductor integrated circuit device 100, for example, a plurality of modes as shown in FIG. Can be selected. 4A is a mode table showing modes that can be selected when image data is input (denoted as Input in the figure), and FIG. 4B is a mode table when image data is output (in the figure, Output and Output). It is a mode table showing modes that can be selected.

  First, as shown in FIG. 4A, when inputting image data, 4-bit or 8-bit pixel data can be input simultaneously from 1 to 4 lines. That is, the total bit width of pixel data that can be input simultaneously is 4 bits to 16 bits. Corresponding to these, there are five modes from 4A to 16B that can be selected at the time of input.

  On the other hand, as shown in FIG. 4B, when outputting image data, 2-bit or 4-bit pixel data can be simultaneously output from 1 to 4 lines. That is, the total bit width of pixel data that can be output simultaneously is 4 bits or 8 bits. Corresponding to these, four modes from 4A to 8B can be selected at the time of output. The image processing block 106 has a function of absorbing and converting the difference by buffering the difference between the number of input and output lines in the image processing block 106, and a gradation conversion by error diffusion. Built-in function to convert by technology.

  As described above, when five modes can be selected at the time of image data input and four modes at the time of output, the total bit widths at the time of input and at the time of output are all combinations of six modes of input and output. . In addition, the number of signals varies depending on the mode in both the input group and the output group.

  FIG. 1 is a table in which six combinations of five modes at the time of input and four modes at the time of output correspond to the external pins of the semiconductor integrated circuit device 100 virtually in one dimension. is there. In this table, the external pins of the semiconductor integrated circuit device 100 are virtually allocated one-dimensionally from pin number 1 to pin number 28. As described with reference to FIG. 2, the pin numbers 6 and 18 and the pin numbers 7 and 19 are not shown in FIG. 1 because they are a power supply (VCC) pin and a ground (GND) pin.

  As shown in FIG. 1, the image data input group PORT-A for image processing is assigned to the head of the output pin, and the total bit width from PORT-A1 is corresponded in ascending order of pin numbers, that is, from the first. Let assign. On the other hand, in the present embodiment, the image data output group PORT-B is assigned to the tail of the external pin in order from PORT-B1, and assigned in reverse order from the pin number 28. Here, Mode 0 in FIG. 1 will be described as an example. Mode 0 is a case where 4A is selected as the mode during input (see FIG. 4A) and 8A or 8B is selected as the mode during output (see FIG. 4B). In Mode 0, PORT-A1 is assigned to pin number 1, and a total bit width of 4 bits is sequentially associated. That is, PORT-A4 is assigned to pin number 4. On the other hand, the image data output group PORT-B assigns PORT-B1 to the pin number 28, assigns the pin numbers in the reverse order, and assigns the image data outputs in the forward order. That is, PORT-B2 is assigned to pin number 27, PORT-B3 is assigned to pin number 26, and PORT-B8 is assigned to pin number 21.

  Further, after assigning input / output of image data, other function groups OPTION are sequentially assigned to the remaining external pins that are not assigned. In the case of Mode 0, OPTION 1 to OPTION 12 are assigned to pin number 5 to pin number 20.

  Note that even in Mode 1 and Mode 2 where the total bit width of the output group PORT-B is Mode 0, the pin numbers assigned to other functions OPTION are fixed to the same arrangement as that of Mode 0. In this case, the input group PORT-A is preferentially assigned to the output pin. That is, as shown in FIG. 1, for example, in Mode 1, the input group signals PORT-A 5 to PORT-A 8 are assigned with priority over the other function group signals OPTION 1 to OPTION 4 from pin number 5 to pin number 10. ing.

  As described above, according to the present embodiment, the usage priority order of the external pins between the input group and the output group is reversed, thereby minimizing the number of input stages from the external pins and the selector stage of the output stage. ing.

  For example, if attention is paid to PORT-B1 in FIG. 1, the data is output from pin number 28 of a fixed external pin regardless of the mode of the input group.

  On the other hand, when attention is paid to the pin number 21 of the external pin, PORT-B8 in Mode0, Mode1, and Mode2 is OPTION13 in Mode3, Mode4, and Mode5. As described above, in this embodiment, the pin number 21 may be a two-input selector of PORT-B8 or OPTION13, and the data input / output timing can be easily set.

Assignment table of external pins of semiconductor integrated circuit device according to an embodiment of the present invention Package diagram of semiconductor integrated circuit device according to an embodiment of the present invention 1 is a block diagram of the inside of a semiconductor integrated circuit device according to an embodiment of the present invention. (A) is a mode table indicating modes that can be selected when image data is input, and (b) is a mode table indicating modes that can be selected when image data is output. Assignment table of external pins of semiconductor integrated circuit device according to conventional example

Explanation of symbols

100 Semiconductor Integrated Circuit Device 101 CPU Interface 102 Register Block 103 Clock Control Block 104 IO Configuration Block 105 Option Block 106 Image Processing Block

Claims (5)

In a semiconductor integrated circuit device having a plurality of external pins and operating in a plurality of operation modes,
A plurality of signals are divided into a plurality of groups for each function, and provided with input / output allocation means for assigning a plurality of signals in each group to the plurality of external pins in advance by assigning a use priority.
The input / output assigning means assigns a first group of the groups to the head of the external pin and assigns a second group to the tail of the external pin. The semiconductor integrated circuit device according to claim 1,
The number of signals in the group varies according to the operation mode. The semiconductor integrated circuit device according to claim 1,
The input / output assigning means assigns the first group of signals in the normal order of the pin numbers assigned to the external pins, and assigns the second group of signals in the reverse order of the pin numbers assigned to the external pins. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1,
The input / output allocating means outputs the signal of the third group out of the group without the allocation when there is an unassigned output pin after the signals of the first group and the second group are allocated. A semiconductor integrated circuit device which is assigned to a pin. The semiconductor integrated circuit device according to claim 4,
The input / output allocation means prioritizes the signal of the first group over the signal of the third group, or prioritizes the signal of the second group over the signal of the third group. A semiconductor integrated circuit device which is assigned to a pin.

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