JP2008192753A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its method, equipped with a damascence wiring of excellent stress-migration resistance and electro-migration resistance. <P>SOLUTION: The semiconductor device includes an insulating film 101 formed on a semiconductor substrate, and a wiring 105 embedded in a recess 102 of the insulating film 101. A Pd film 106 formed by electroless plating is provided on the upper surface of a copper layer 105. The thickness of the Pd film 106 is larger than one atom layer, being 10 nm or less. A CoWP film 107 formed by electroless plating is provided on the upper surface of the Pd film 106. Thus, diffusing of the material constituting the CoWP film 107 into the copper layer 105 is prevented by the Pd film 106, improving reliability of the semiconductor device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device provided with damascene wiring and a manufacturing method thereof.

  In recent years, with the miniaturization of semiconductor devices, a technique for forming low-resistance wiring is required. As a technique for reducing resistance of wiring, development of damascene wiring using copper as a main material has been widely performed. However, along with further miniaturization of semiconductor devices, there are concerns about an increase in wiring resistance and a decrease in reliability in damascene wiring. Therefore, a process for selectively growing a metal cap layer such as a cobalt-tungsten-phosphorus (CoWP) film on the damascene wiring to improve the reliability of the damascene wiring has been proposed (see, for example, Patent Documents 1 to 3). ).

  Hereinafter, a method for manufacturing a semiconductor device including a damascene wiring on which the metal cap layer is formed will be described with reference to FIG. First, as shown in FIG. 2A, an insulating film 201 is formed over a semiconductor substrate (not shown) on which a semiconductor element such as a transistor is formed. The concave portion 202 is formed on the insulating film 201 by applying a known lithography method and dry etching method. A barrier layer 203 made of tantalum (Ta) or the like is formed on the insulating film 201 in which the recesses 202 are formed by a sputtering method or the like.

  Next, as shown in FIG. 2B, a seed layer 204 made of copper is formed on the barrier layer 203 by sputtering or the like. Subsequently, as shown in FIG. 2C, a copper layer 205 is formed on the seed layer 204 by electrolytic plating using the seed layer 204 as an electrode. At this time, the inside of the recess 202 is filled with the copper layer 205. Then, as shown in FIG. 2D, a copper layer 205, a seed layer 204, and a barrier layer 203 are formed on the insulating film 201 other than the concave portion 202 by chemical mechanical polishing (CMP). Is removed.

  Thereafter, as shown in FIG. 2E, a CoWP film 206 is formed to a thickness of about 1 nm to 20 nm on the upper surface of the copper layer 205 filled in the recesses 202 by an electroless plating method. In order to grow the CoWP film by the electroless plating method, a catalyst layer is required at a site where the CoWP film is grown. However, since copper has low catalytic activity, it does not function sufficiently as a catalyst layer for depositing a CoWP film. Therefore, in order to grow the CoWP film 206 on the copper layer 205, first, a catalyst layer such as a palladium (Pd) film is formed on the upper surface of the copper layer 205.

  In order to form a Pd film on the copper layer 205, displacement plating is used. For example, when a semiconductor substrate on which the copper layer 205 illustrated in FIG. 2D is formed is immersed in a hydrochloric acid solution of palladium chloride, copper is dissolved in the solution. At this time, electrons released as copper dissolves are captured by palladium ions having a smaller ionization tendency than copper, and the palladium atoms are replaced with copper atoms. Such substitution occurs only on the surface of the copper layer 205. Therefore, a Pd film is formed only on the upper surface of the copper layer 205. By performing electroless plating using the Pd film thus formed as a catalyst layer, the CoWP film 206 can be selectively grown only on the upper surface of the copper layer 205.

As described above, a semiconductor device including the CoWP film 206 on the upper surface of the wiring can be manufactured.
Special table 2003-505882 gazette JP 2004-179589 A JP 2004-200303 A

  However, since the CoWP film 206 has a higher resistance than the copper layer 205, an increase in wiring resistance has become apparent with further miniaturization of the semiconductor device. In addition, Co atoms having high resistance diffuse into the copper layer 205 in the wiring having the above-described structure due to heat generation accompanying the increase in resistance of the wiring. The diffusion further increases the wiring resistance. As a result, there arises a problem that the stress migration resistance and electromigration resistance of the damascene wiring are lowered.

  In the above manufacturing method, the catalyst layer is formed by displacement plating. In displacement plating, the amount of Cu, which is the main material of the wiring, decreases due to substitution of Cu atoms and dissolution of Cu in a hydrochloric acid solution. Furthermore, when the dissolution of Cu proceeds along the grain boundary of the copper layer 205, voids are formed in the copper layer 205. Such a phenomenon also contributes to a decrease in stress migration resistance and electromigration resistance of the wiring.

  The present invention has been proposed in view of the above-described conventional circumstances, and an object thereof is to provide a semiconductor device including a damascene wiring having excellent stress migration resistance and electromigration resistance and a method for manufacturing the same.

  In order to achieve the above object, the semiconductor device according to the present invention employs the following technical means. That is, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a wiring embedded in the insulating film. A first cap layer is provided on the upper surface of the wiring. The film thickness of the first cap layer is larger than one atomic layer and 10 nm or less. In addition, a second cap layer formed on the upper surface of the first cap layer is provided to prevent diffusion of the material constituting the wiring.

  According to this configuration, the first cap layer can prevent the material constituting the second cap layer from diffusing into the wiring. As a result, an increase in wiring resistance can be suppressed and the reliability of the semiconductor device can be improved.

  In the above configuration, the wiring may employ a configuration including a barrier layer and a wiring layer. As a result, the wiring layer can be prevented from diffusing into the insulating film. The wiring may further include a seed layer between the barrier layer and the wiring layer. Thereby, the adhesiveness of a wiring layer and a barrier layer can be improved.

  Further, from the viewpoint of reducing the wiring resistance, it is preferable that the first cap layer has a lower specific resistance than the second cap layer. Furthermore, the first cap layer preferably has a higher melting point than the second cap layer. Thus, even when the semiconductor device is heated, the first cap layer can prevent the second cap layer from diffusing into the wiring.

  On the other hand, in another aspect, the present invention can provide a method for manufacturing a semiconductor device. That is, in the method for manufacturing a semiconductor device according to the present invention, first, an insulating film is formed on a semiconductor substrate. Next, a recess is formed in the insulating film, and a wiring embedded in the recess is formed. In addition, a first cap layer is formed on the upper surface of the wiring by electroless plating. A second cap layer is formed on the upper surface of the first cap layer by electroless plating. Here, electroless plating refers to a plating method in which a metal is deposited by an oxidation-reduction reaction using a solution containing a metal and a reducing agent.

  The wiring can be formed as follows. First, a barrier layer is formed on the insulating film in which the recesses are formed. Next, a wiring layer is formed on the barrier layer. Then, the barrier layer and the wiring layer formed other than the recess are removed.

  In addition, in order to prevent a wiring layer from melt | dissolving in a plating solution, it is preferable that the pH value of the plating solution used for the electroless plating which forms a 1st cap layer is 5-12.

  According to the present invention, since the second cap layer is formed on the wiring via the first cap layer having a thickness of one atomic layer or more, the second cap layer and the wiring are directly connected to each other. Do not touch. For this reason, even if the second cap layer is a film containing a high-resistance metal such as a CoWP film, the high-resistance metal can be prevented from diffusing into the wiring. Therefore, an increase in wiring resistance can be suppressed. As a result, it is possible to achieve a special effect of improving electromigration resistance and stress migration resistance.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the present invention is embodied by an example applied to a semiconductor device manufacturing method using a damascene method. FIG. 1 is a cross-sectional view showing the manufacturing process of the semiconductor device of this embodiment. In FIG. 1, there is a semiconductor substrate on which a semiconductor element such as a transistor is formed below the insulating film 101. However, the description is omitted here because it is not directly related to the present invention. .

First, as shown in FIG. 1A, an insulating film 101 is formed over a semiconductor substrate. Here, the insulating film 101 is made of a material (SiC, SiO ₂ , SiN, SiOC, SiON, etc.) composed of silicon (Si) and carbon (C), oxygen (O), nitrogen (N), or the like. Next, by applying a known lithography method and dry etching method to the insulating film 101, the concave portion 102 is formed on the surface portion of the insulating film 101. On the insulating film 101 in which the recess 102 is formed, a barrier layer 103 having a thickness of about 20 nm made of Ta is formed by sputtering. The film forming conditions here are a target bias of 30 kW, a substrate bias of 300 W, and an Ar gas flow rate of 8 sccm. In this embodiment, a Ta film is used as the barrier layer 103. However, refractory metals such as titanium (Ti), tungsten (W), and ruthenium (Ru), and N, C, and Si are doped therein. A film made of a material can also be used. The barrier layer 103 may be a laminated film of these. In the present embodiment, the barrier layer 103 is formed using a sputtering method, but may be formed using a CVD (Chemical Vapor Deposition) method or the like.

  Next, as shown in FIG. 1B, a seed layer 104 having a thickness of about 40 nm made of copper (Cu) is formed on the barrier layer 103 by a sputtering method. The film forming conditions here are a target bias of 40 kW and a substrate bias of 600 W. In this embodiment, a Cu film is used as the seed layer 104. However, any conductive film such as Ru or platinum (Pt) can be used as long as it can function as an electrode for electrolytic plating in the next step. it can. In addition, the conductor film constituting the seed layer 104 may be doped with a metal such as aluminum (Al), tin (Sn), manganese (Mn), or Ti. Furthermore, the seed layer 104 can be formed not only by the sputtering method but also by the CVD method.

Subsequently, as shown in FIG. 1C, a copper layer 105 having a thickness of about 1000 nm is formed on the seed layer 104 by electrolytic plating. Here, the copper layer 105 (wiring layer) is formed by immersing the semiconductor substrate on which the seed layer 104 is formed in a copper sulfate solution and supplying current to the seed layer 104. By the electroplating, the inside of the recess 102 is filled with the copper layer 105. The plating solution is a plating solution mainly composed of copper sulfate, and has a Cu concentration of 10 to 40 g / L and a sulfuric acid concentration of 10 to 200 g / L. The plating solution temperature is room temperature, and the current density of the current supplied to the seed layer 104 is about 5 to 50 mA / mm ² .

When the formation of the copper layer 105 is completed, as shown in FIG. 1D, the copper layer 105, the seed layer 104, and the barrier layer 103 on the insulating film 101 other than the recess 102 are removed by CMP. . After the barrier layer 103 on the insulating film 101 is removed, the semiconductor substrate is washed with an acidic solution in an N ₂ atmosphere. Here, the N ₂ atmosphere is used for cleaning, but any atmosphere that does not contain a highly reactive gas such as F ₂ or O ₂ may be used. For example, the cleaning may be performed in an inert gas atmosphere such as He or Ar.

Next, as shown in FIG. 1E, a first cap layer 106 is formed on the copper layer 105 embedded in the recess 102 by an electroless plating method. In the present embodiment, the electroless plating for forming the first cap layer 106 is performed in the same atmosphere as the cleaning with the acidic solution. For example, a plating solution of 40 ° C. to 95 ° C. is supplied to the center of the semiconductor substrate that rotates in the circumferential direction around the substrate center as the rotation axis in the atmosphere. Here, palladium chloride 0.01 mol / dm ^3, ethylenediamine 0.08 mol / dm ^3, sodium phosphinate 0.06 mol / dm ^3, using a plating solution containing a thio diglycolic acid 30 mg / dm ^3. In order to prevent the copper layer 105 from dissolving in the plating solution, the pH value of the plating solution is preferably in the range of 5 to 12, and more preferably in the range of 6 to 10. Further, the rotational speed of the semiconductor substrate when supplying the plating solution may be about 5 rpm. As a result, a Pd film is deposited on the copper layer 105 by an oxidation-reduction reaction, and the first cap layer 106 is formed.

  The first cap layer 106 has a function of preventing the constituent material of the second cap layer 107 formed on the first cap layer 106 in the subsequent process from diffusing into the copper layer 105. In the present embodiment, the first cap layer 106 is formed not by the displacement plating method but by the electroless plating method. For this reason, the film thickness of the first cap layer 106 can be one atomic layer or more.

  In the displacement plating method, Cu atoms present on the surface of the copper layer 105 are replaced with Pd atoms. For this reason, Cu atoms not exposed on the surface are not replaced. Further, in displacement plating, not all Cu atoms exposed on the surface are replaced, but only a part thereof is replaced. For example, one Cu atom is replaced with one Pd atom per 100 Cu atoms. Therefore, the thickness of the first cap layer 106 formed by the displacement plating method is less than one atomic layer, and the material constituting the second cap layer 107 cannot be prevented from diffusing into the copper layer 105. .

  On the other hand, in this embodiment, since the first cap layer 106 can be formed with a film thickness of one atomic layer or more, the material constituting the second cap layer 107 diffuses into the copper layer 105. Can be prevented. Further, in electroless plating, Cu atoms are not substituted and the amount of Cu in the wiring is not reduced unlike substitution plating. Note that the thickness of the first cap layer 106 is preferably 10 nm or less. This is because when the thickness of the first cap layer 106 exceeds 10 nm, the possibility of an electroless plating film unintentionally growing on the insulating film 101 increases in the step of forming the first cap layer 106. This is because a short circuit between adjacent wirings easily occurs.

  Subsequently, as shown in FIG. 1F, a second cap layer 107 made of a CoWP film is formed on the first cap layer 106 with a thickness of about 1 to 20 nm by an electroless plating method. . Here, the second cap layer 107 prevents diffusion of the material constituting the wiring (here, the copper layer 105). For the formation of the CoWP film, for example, the CoWP film can be formed by a plating solution containing cobalt sulfate, sodium hypophosphite, and sodium tungstate as main components and containing an additive such as a chelating agent or an organic acid. . The film forming temperature may be about 40 to 95 ° C., for example.

  In the present embodiment, a Pd film is used as the first cap layer 106, but other materials can also be used. From the viewpoint of suppressing an increase in wiring resistance, a material having a specific resistance lower than that of the high-resistance metal (here, Co) constituting the second cap layer 107 can be used. For example, Au, Ag, Mo or the like having a lower specific resistance than Co can be used. In addition, from the viewpoint of preventing the material constituting the second cap layer 107 from diffusing into the copper layer 105 under a heating environment, it is more than the high resistance metal (here, Co) constituting the second cap layer 107. A material having a high melting point can be used. For example, Pt or Pd having a melting point higher than that of Co can be used.

  When the wiring is formed as described above, an insulating film is formed on the entire surface of the semiconductor substrate. When forming the upper layer wiring, the above-described procedure is repeatedly performed.

  In the copper wiring formed by the above steps, the high resistance metal made of the second cap layer 107 does not directly contact the copper wiring. For this reason, it is possible to prevent Co from diffusing into the Cu wiring. As a result, an increase in wiring resistance is suppressed. As a result of suppressing the increase in wiring resistance, a semiconductor device having excellent stress migration resistance and electromigration resistance can be manufactured.

  As described above, according to the present invention, it is possible to prevent the high-resistance metal constituting the second cap layer made of a CoWP film or the like from diffusing into the wiring. For this reason, the upper layer of wiring resistance can be suppressed. As a result, a semiconductor device having excellent stress migration resistance and electromigration resistance can be manufactured.

  The embodiments described above do not limit the technical scope of the present invention, and various modifications and applications can be made within the scope of the present invention other than those already described. For example, in the above embodiment, an example in which the wiring includes a copper layer, a seed layer, and a barrier layer has been described. However, the seed layer and the barrier layer are not essential elements of the present invention, and the wiring is limited to the above-described structure. It is not something. In the above description, the case where the material of the second cap layer is CoWP has been described. However, the second cap layer may be a metal film having a copper diffusion prevention function. For example, the second cap layer can be formed of an alloy in which tank stainless or molybdenum is added to cobalt or nickel.

  The present invention has the effect of improving the stress migration resistance and electromigration resistance of wiring, and is useful as a semiconductor device and a method for manufacturing a semiconductor device.

Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Process sectional view showing the manufacturing process of a conventional semiconductor device

Explanation of symbols

101 Insulating film 102 Recessed part 103 Barrier layer 104 Seed layer 105 Copper layer (wiring layer)
106 First cap layer (Pd film)
107 Second cap layer (CoWP film)

Claims (8)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
Wiring embedded in the insulating film;
A first cap layer formed on the upper surface of the wiring and having a thickness of greater than one atomic layer and not greater than 10 nm;
A second cap layer formed on an upper surface of the first cap layer and preventing diffusion of a material constituting the wiring;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the wiring includes a barrier layer and a wiring layer.   The semiconductor device according to claim 2, wherein the wiring further includes a seed layer between the barrier layer and the wiring layer.   The semiconductor device according to claim 1, wherein the first cap layer is made of a material having a specific resistance smaller than that of the second cap layer.   The semiconductor device according to claim 1, wherein the first cap layer is made of a material having a melting point higher than that of the second cap layer. Forming an insulating film on the semiconductor substrate;
Forming a recess in the insulating film;
Forming a wiring embedded in the recess;
Forming a first cap layer on the upper surface of the wiring by electroless plating;
Forming a second cap layer for preventing diffusion of the material constituting the wiring by electroless plating on the upper surface of the first cap layer;
A method for manufacturing a semiconductor device, comprising: The step of forming the wiring includes
Forming a barrier layer on the insulating film in which the recess is formed;
Forming a wiring layer on the barrier layer;
Removing the barrier layer and the wiring layer formed other than the recess;
A method for manufacturing a semiconductor device according to claim 6.   The method for manufacturing a semiconductor device according to claim 6 or 7, wherein a pH value of a plating solution used for electroless plating for forming the first cap layer is 5 to 12.

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