JP2008191450A - Pixel circuit, drive method of pixel circuit, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress errors in grayscale of an electro-optical element. <P>SOLUTION: The pixel circuit P includes the electro-optical element E having a grayscale, corresponding to a drive current IDR flowing through a path r1, a drive transistor TDR disposed in the path r1 and controlling the drive current IDR according to the potential VG at the gate, and a capacitive element CA having electrodes a1 and a2. The electrode a2 is connected to the gate of the drive transistor TDR. In a writing period PWRT where the potential VG is set to a potential corresponding to a data signal X[j], the electrode 1a is connected to the anode of the electro-optical element E, and a current IDT for detection is supplied to the electro-optical element E to set the potential VA at the electrode a1 to a potential VDT, corresponding to the voltage across the electrooptical element E. In a drive period PDRV after the write period PWRT, the potential VG is set by making the potential VA vary to the predetermined potential VCT, while the electrode a1 is set in an insulated state from the electro-optical element E. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for controlling the gradation of an electro-optical element such as an organic light-emitting diode element.

  A pixel circuit using a transistor (hereinafter referred to as “driving transistor”) for controlling a driving current supplied to an electro-optical element has been proposed (for example, Patent Document 1). As shown in FIG. 24, in one pixel circuit, the drive transistor TDR and the electro-optical element E (organic light emitting diode element) are arranged on the path r1. The drive transistor TDR controls the amount of drive current IDR flowing through the path r1 according to the gate potential VG, so that the electro-optical element E has a desired gradation.

FIG. 25 is a conceptual diagram in which the voltage (drain-source voltage) -current characteristic FTR of the driving transistor TDR and the voltage-current characteristic FEL_1 of the electro-optical element E are shown together. The intersection of the characteristic FTR and the characteristic FEL_1 in FIG. 25 corresponds to the operating point P1 of the pixel circuit. That is, when the pixel circuit is driven, the drive current IDR of the current amount A1 flows through the path r1.
JP 2002-156923 A

  By the way, the electrical characteristics of the electro-optical element E may generate an initial error in manufacturing or an error due to deterioration over time. A characteristic FEL_2 in FIG. 25 is a voltage-current characteristic of the electro-optical element E when there is an error. Since the pixel circuit operates with the intersection of the characteristic FTR and the characteristic FEL_2 as the operating point P2, the drive current IDR supplied to the path r1 is the same as when the electro-optical element E has the desired characteristic FEL_1 (current amount A1). In comparison, the current amount A2 is low. Therefore, there is a problem that an error (difference from an expected value and variation between elements) also occurs in the gradation of the electro-optic element E. In view of the above circumstances, an object of the present invention is to solve the problem of suppressing an error in gradation of an electro-optical element.

  In order to solve the above problems, a driving method of a pixel circuit according to the present invention includes an electro-optic element having a gradation corresponding to a first current (for example, the driving current IDR in FIG. 5) flowing in the first path, A pixel circuit including a driving transistor arranged on one path and controlling a first current in accordance with a gate potential, and a capacitor element having a first electrode and a second electrode connected to the gate of the driving transistor. In the driving method, in the first period (for example, the writing period PWRT in FIGS. 2 and 11) in which the gate potential of the driving transistor is set to a potential corresponding to the data signal, the first electrode is electrically connected to the electro-optic element. And connecting the electro-optic element with a second current (for example, the detection current IDT in FIG. 4), the potential of the first electrode is set to a potential corresponding to the voltage across the electro-optic element, Second period after the first period During the period (for example, the driving period PDRV in FIGS. 2 and 11), the potential of the gate of the driving transistor is changed by changing the potential of the first electrode to a predetermined potential while the first electrode is electrically insulated from the electro-optical element. Is set.

  According to the above configuration, since the potential of the gate of the driving transistor (and the current amount of the first current) is set according to the voltage across the electro-optical element when the second current is supplied, the electro-optical element It is possible to suppress an error in the gradation of the electro-optic element due to the error in the electrical characteristics.

  In a preferred aspect of the present invention, the first path is formed between the first power supply line to which the first power supply potential is supplied and the second power supply line to which the second power supply potential lower than the first power supply potential is supplied. In the first period, the first feeding line to which the first potential (for example, the first potential VHH in FIG. 9) between the first power supply potential and the second power supply potential is supplied is connected to the electro-optic element. A second current is passed through the electro-optic element via two paths. According to the above aspect, the amount of the second current can be appropriately adjusted according to the first potential. For example, in an aspect in which an image is displayed by using a light emitting element that emits light by supplying current as an electro-optical element, the first potential is selected so that the amount of light emission in the first period is sufficiently reduced. Contrast can be improved.

  In a preferred aspect of the present invention, the first path is formed between the first power supply line to which the first power supply potential is supplied and the second power supply line to which the second power supply potential lower than the first power supply potential is supplied. In the second period, the first electrode is connected to the second power supply line to which the second potential between the first power supply potential and the second power supply potential is supplied. According to the above aspect, the amount of change in the potential of the gate of the driving transistor in the second period (and the amount of the first current) can be adjusted as appropriate according to the second potential.

  In the driving method according to one aspect of the present invention, in the compensation period before the start of the first period, the gate potential of the driving transistor is set to a potential corresponding to the threshold voltage of the driving transistor, and the compensation period and the first period are set. The first electrode is electrically connected to the electro-optic element and a second current is supplied to the electro-optic element. According to the above aspect, since the potential of the gate of the driving transistor is set to a potential corresponding to the threshold voltage during the compensation period, it is possible to compensate for an error in the threshold voltage of the driving transistor. In addition, since the first electrode is connected to the electro-optic element and the second current is supplied to the electro-optic element over both the compensation period and the first period, the potential of the first electrode is changed to the electrical potential of the electro-optic element. There is an advantage that the potential can be reliably set according to the characteristics.

  More preferably, in the initialization period before the start of the compensation period, the potential of the gate of the driving transistor and the potential of the first electrode are initialized to a predetermined potential. In this aspect, since the potential of the gate of the driving transistor and the potential of the first electrode are initialized, the gate potential of the driving transistor is set with high accuracy regardless of the potential immediately before the compensation period or the first period. Thus, it becomes possible to set the potential to the desired value.

A driving method according to another aspect of the present invention includes an electro-optical element having a gradation according to a first current, a driving transistor that controls the first current according to a gate potential, a first electrode, and a driving transistor A method of driving a pixel circuit including a capacitive element having a second electrode connected to a gate, wherein the second electrode is set to a potential corresponding to a data signal and the first electrode is set in a first period. The potential is set according to the electrical characteristics of the electro-optic element, the potential of the first electrode is changed in the second period after the first period, and the potential of the gate of the driving transistor after the change is changed. A first current is supplied to the electro-optic element. In the above aspect, since the potential of the gate of the driving transistor (and the amount of the first current) is set according to the electrical characteristics of the electro-optic element and the data signal, the electrical characteristics of the electro-optic element It is possible to suppress the gray level error of the electro-optic element due to the characteristic error.
In the above aspect, in an aspect in which the electro-optical element has a pair of electrodes (for example, an aspect in which a light-emitting element having a light-emitting layer interposed between an anode and a cathode is an electro-optical element), The potential corresponding to the characteristics is, for example, a pair of potentials corresponding to the electrical characteristics of the electro-optical element when the second current is supplied to the electro-optical element in a state where the electro-optical element and the first electrode are connected. It is a potential according to the voltage between the electrodes. According to the above aspect, it is possible to compensate for an error in the current-voltage characteristics of the electro-optic element.

  The pixel circuit according to the present invention includes an electro-optical element having a gradation corresponding to the first current flowing through the first path, and a driving transistor disposed on the first path and controlling the first current according to the potential of the gate. A capacitive element having a first electrode and a second electrode connected to the gate of the driving transistor, and a first switching element that controls whether or not a second current can be supplied to the electro-optical element (for example, in FIGS. 3 and 10) Transistor QE), a second switching element for controlling electrical connection between the first electrode and the electro-optic element (for example, transistor QB in FIGS. 3 and 10), a power supply line to which a predetermined potential is supplied, and a first A third switching element (for example, the transistor QC in FIGS. 3 and 10) for controlling the electrical connection with the electrode is provided.

  In the pixel circuit described above, the potential of the first electrode is established by conducting the first switching element and the second switching element in the first period in which the gate potential of the driving transistor is set to a potential corresponding to the data signal. Is set to a potential corresponding to the voltage across the electro-optic element when the second current is supplied, and the third switching element is turned off in the second period after the first period. It is possible to employ a driving method in which the gate potential of the driving transistor is set by turning on the switching element. That is, the potential of the gate of the driving transistor (and the current amount of the first current) is set according to the voltage across the electro-optical element when the second current is supplied, and thus the electrical characteristics of the electro-optical element. It is possible to suppress an error in the gradation of the electro-optic element due to the error.

  The electro-optical device according to the present invention is an electro-optical device including a pixel circuit and a driving circuit (for example, the scanning line driving circuit 22 in FIG. 1), and the pixel circuit has a first current flowing in the first path. An electro-optical element having a gradation corresponding to the first level, a driving transistor arranged on the first path and controlling the first current according to the potential of the gate, and a second electrode connected to the first electrode and the gate of the driving transistor. A capacitive element having an electrode; a first switching element that controls whether a second current can be supplied to the electro-optic element; a second switching element that controls electrical connection between the first electrode and the electro-optic element; The driving circuit includes a power supply line to which a predetermined potential is supplied and a third switching element that controls electrical connection between the first electrode, and the driving circuit has the gate potential of the driving transistor set to a potential corresponding to the data signal. First In the period, the first switching element and the second switching element are controlled to be in a conducting state and the third switching element is controlled to be in a non-conducting state. In the second period after the elapse of the first period, the first switching element and the second switching element are The second switching element is controlled to be in a non-conductive state, and the third switching element is controlled to be in a conductive state. Also with the above configuration, the same operations and effects as the pixel circuit according to the present invention are exhibited.

  The electro-optical device according to the invention is used in various electronic apparatuses. A typical example of an electronic device is a device that uses an electro-optical device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone. However, the use of the electro-optical device according to the present invention is not limited to image display. For example, the electro-optical device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

<A: First Embodiment>
<A-1: Configuration>
FIG. 1 is a block diagram showing a configuration of an electro-optical device (display device) according to a first embodiment of the present invention. As shown in FIG. 1, the electro-optical device 100 includes a pixel unit 10 in which a plurality of pixel circuits P are arranged, a scanning line driving circuit 22 and a data line driving circuit 24 that drive each pixel circuit P, and a pixel unit 10. And a voltage generation circuit 26 for supplying a predetermined potential (VEL, VCT). The scanning line driving circuit 22, the data line driving circuit 24, and the voltage generation circuit 26 may be mounted on the electro-optical device 100 as separate circuits, or a part or all of these circuits may be a single unit. The circuit may be mounted on the electro-optical device 100.

  In the pixel unit 10, M sets of control line groups 12 extending in the X direction and N data lines 14 extending in the Y direction perpendicular to the X direction are formed. The set of control line groups 12 includes a plurality of control lines (not shown). Each pixel circuit P is arranged corresponding to each intersection of the control line group 12 and the data line 14. Accordingly, the plurality of pixel circuits P are arranged in a matrix of vertical M rows × horizontal N columns.

  FIG. 2 is a timing chart for explaining the operation of the electro-optical device 100. The scanning line driving circuit 22 generates control signals Y1 [1] to Y1 [M] and control signals Y2 [1] to Y2 [M] and outputs them from the control line group 12 to the pixel unit 10. The control signals Y1 [1] to Y1 [M] are pulse signals for sequentially selecting the pixel circuits P of the pixel unit 10 in units of rows. As shown in FIG. 2, M control signals Y1 [i] supplied to the pixel circuit P in the i-th row (i = 1 to M) are defined so as not to overlap each other in one frame. The writing period PWRT becomes high level (active level) in the i-th writing period PWRT, and is maintained at the low level outside the writing period PWRT. The control signal Y2 [i] is at a high level during the period PDRV immediately after the writing period PWRT when the control signal Y1 [i] is at a high level (hereinafter referred to as “driving period”), and is at a low level outside the driving period PDRV. To maintain.

  The data line driving circuit 24 in FIG. 1 generates data signals X [1] to X [N] and outputs them to the data lines 14. The data signal X [j] supplied to the data line 14 in the j-th column (j = 1 to N) belongs to the i-th row in the writing period PWRT in which the control signal Y1 [i] is at the high level. The potential VDATA is set in accordance with the gradation specified for the pixel circuit P in the j-th column. The gradation of each pixel circuit P is designated by an image signal (not shown) supplied from the outside.

  The voltage generation circuit 26 is a circuit that generates a power supply potential VEL and a ground potential VCT. The power supply potential VEL is higher than the ground potential VCT. The power supply potential VEL is supplied to each pixel circuit P through the power supply line 161, and the ground potential VCT is supplied to each pixel circuit P through the power supply line 162.

  FIG. 3 is a circuit diagram showing a configuration of one pixel circuit P. In the drawing, only one pixel circuit P in the j-th column belonging to the i-th row is representatively shown. As shown in FIG. 3, the electro-optic element E and the drive transistor TDR are arranged on a path r1 formed between the power supply line 161 and the power supply line 162. The electro-optic element E is an organic light-emitting diode element in which a light-emitting layer formed of an organic EL (Electroluminescence) material is interposed between an anode and a cathode. The electro-optical element E emits light when current is supplied to the light emitting layer. The cathode of the electro-optic element E is electrically connected to the power line 162.

  The drive transistor TDR is a p-channel type thin film transistor that controls the amount of current flowing in the path r1 (hereinafter referred to as “drive current”) IDR in accordance with the gate potential VG. The source (S) of the drive transistor TDR is electrically connected to the power supply line 161.

  As shown in FIG. 3, the pixel circuit P includes two capacitive elements (C0, CA). The capacitive element C0 is interposed between the gate and source of the driving transistor TDR and holds the voltage between them. Capacitance element CA includes electrodes a1 and a2. The electrode a2 is electrically connected to the gate of the driving transistor TDR.

  The pixel circuit P includes five n-channel transistors (QA, QB, QC, QD, QE) that function as switching elements. The control signal Y1 [i] is supplied from the scanning line drive circuit 22 to the gates of the transistors QB, QD and QE, and the control signal Y2 [i] is supplied from the scanning line drive circuit 22 to the gates of the transistors QA and QC. .

  The transistor QA is interposed between the drain (D) of the driving transistor TDR and the anode of the electro-optic element E, and controls the electrical connection (conduction / non-conduction) between them. That is, the path r1 of the drive current IDR is established when the transistor QA is turned on, and the drive current IDR is cut off when the transistor QA is changed to the non-conductive state.

  The transistor QB is interposed between the electrode a1 of the capacitive element CA and the anode of the electro-optic element E and controls the electrical connection between them. The transistor QC is interposed between the electrode a1 and the power supply line 162 and controls the electrical connection between them. The transistor QD is interposed between the gate of the driving transistor TDR and the data line 14 and controls the electrical connection between them.

  The transistor QE is interposed between the anode of the electro-optic element E and the power supply line 161 to control the electrical connection between them. That is, when the transistor QE is turned on, a path r2 from the power supply line 161 to the anode of the electro-optic element E via the transistor QE is formed, and when the transistor QE transitions to a non-conductive state, the path r2 is blocked.

  A resistance element R is interposed on the path r2 (between the power supply line 161 and the transistor QE). The resistance element R is formed of a material of a conductive layer having a relatively high resistivity among the conductive layers constituting the pixel circuit P. More specifically, the resistance element R can be formed of a material (for example, polysilicon) common to the semiconductor layers of the driving transistor TDR and the transistors QA to QE.

<A-2: Operation>
Next, a specific operation of the electro-optical device 100 will be described with reference to FIGS. 4 and 5. Hereinafter, the operation of the pixel circuit P in the j-th column belonging to the i-th row will be described by dividing it into a writing period PWRT and a driving period PDRV. 4 and 5, the transistors QA to QE of the pixel circuit P are illustrated as switches for convenience.

[A] Write period PWRT (FIG. 4)
As shown in FIG. 2, the control signal Y2 [i] is set to the low level in the writing period PWRT, so that the transistors QA and QC maintain the non-conducting state. Therefore, as shown in FIG. 4, the path r 1 of the drive current IDR is blocked and the electrode a 1 of the capacitive element CA is electrically insulated from the power line 162.

  On the other hand, the control signal Y1 [i] changes to the high level in the writing period PWRT. Therefore, as shown in FIG. 4, when the transistor QD is turned on, the gate of the driving transistor TDR is connected to the data line 14. Since the data line driving circuit 24 sets the data signal X [j] to the potential VDATA corresponding to the gradation of the pixel circuit P in the writing period PWRT, the potential VG of the gate of the driving transistor TDR is set as shown in FIG. The potential is set to VDATA. The potential VDATA is held by the capacitive element C0.

  Further, when the control signal Y1 [i] transitions to a high level, the transistors QB and QE become conductive. That is, as shown in FIG. 4, the electrode a1 of the capacitive element CA and the anode of the electro-optic element E are electrically connected via the transistor QB, and the power line 161 and the anode of the electro-optic element E are connected. A route r2 is formed. Therefore, a current (hereinafter referred to as “detection current”) IDT flows from the power supply line 161 to the power supply line 162 via the resistance element R, the transistor QE, and the electro-optical element E. Since the electrode a1 is connected to the anode of the electro-optical element E, during the writing period PWRT, the potential VA of the electrode a1 is a potential corresponding to the electrical characteristics of the electro-optical element E as shown in FIG. It converges to the potential VDT (hereinafter referred to as “detection potential”). That is, the detection potential VDT is a potential corresponding to the voltage across the electro-optical element E when the detection current IDR is supplied.

[B] Driving period PDRV (FIG. 5)
As shown in FIG. 2, since the control signal Y1 [i] transitions to a low level during the driving period PDRV, the transistors QB, QD, and QE are turned off. Therefore, as shown in FIG. 5, the anode of the electro-optical element E is electrically insulated from the power supply line 161 and the electrode a1. That is, the path r2 of the detection current IDT is interrupted. Further, since the impedance of the gate of the driving transistor TDR is sufficiently high, when the transistor QD transitions to a non-conducting state, the gate of the driving transistor TDR enters an electrically floating state.

On the other hand, the control signal Y2 [i] maintains a high level during the driving period PDRV. Therefore, the transistor QC conducts as shown in FIG. Since the transistor QB is in a non-conductive state, when the transistor QC is turned on and the electrode a1 is electrically connected to the power supply line 162, the potential VA of the electrode a1 is changed during the writing period PWRT as shown in FIG. The detection potential VDT thus set decreases to the ground potential VCT. On the other hand, the gate (electrode a2) of the driving transistor TDR is in a floating state. Therefore, when the potential VA of the electrode a1 is lowered by the change amount ΔVA from the detection potential VDT to the ground potential VCT, the potential VG of the electrode a2 that constitutes the capacitive element CA together with the electrode a1 is as shown in FIG. Then, the potential ΔDATA is lowered from the potential VDATA set in the writing period PWRT.
VG = VDATA−ΔVG (1)
As shown in the following equation (2), the change amount ΔVG of the potential VG in the equation (1) is the capacitance element CA (capacitance value cA), the capacitance element C0 (capacitance value c0), and the gate capacitance (capacitance) of the drive transistor TDR. It is determined according to the capacity ratio with the value cG).
ΔVG = cA / (c0 + cA + cG) × ΔVA (2)

  Further, as shown in FIG. 5, in the drive period PDRV, the transistor QA is turned on to form the path r1 of the drive current IDR. Accordingly, the drive current IDR corresponding to the potential VG of the expression (1) is supplied from the power supply line 161 to the electro-optical element E via the drive transistor TDR and the transistor QA. The electro-optical element E emits light by supplying the driving current IDR.

  FIG. 6 is a conceptual diagram in which the voltage-current characteristic FR of the resistance element R and the voltage-current characteristic FEL (FEL_1, FEL_2) of the electro-optical element E are shown together. The electrical characteristics of the electro-optic element E change every moment due to deterioration over time. A characteristic FEL_1 in FIG. 6 is an initial voltage-current characteristic of the electro-optical element E, and a characteristic FEL_2 is a voltage-current characteristic after deterioration. As shown in FIG. 6, the resistance value of the electro-optical element E increases with time. FIG. 7 shows both the waveforms of the potentials VA and VG (solid lines) when the electro-optical element E has the characteristic FEL_1 and the waveforms of the potentials VA and VG (broken lines) when the electro-optical element E has the characteristic FEL_2. Has been.

  When the detection current IDT is supplied from the path r2 to the electro-optic element E in the writing period PWRT as shown in FIG. 4, the potential VA of the electrode a1 is detected according to the intersection of the characteristic FR and the characteristic FEL in FIG. Set to VDT. That is, as shown in FIGS. 6 and 7, the potential VA of the electrode a1 is set to the detection potential VDT_1 when the electro-optical element E has the characteristic FEL_1, and is detected when the electro-optical element E has the characteristic FEL_2. The detection potential VDT_2 is set higher than the potential VDT_1.

  On the other hand, the change amount ΔVA of the potential VA at the start of the driving period PDRV increases as the detection potential VDT set for the electrode a1 in the writing period PWRT increases. For example, as shown in FIGS. 6 and 7, the change amount ΔVA_2 of the potential VA when the electro-optical element E has the characteristic FEL_2 is larger than the change amount ΔVA_1 when the electro-optical element E has the characteristic FEL_1. . That is, the higher the resistance value of the electro-optical element E (the more the deterioration of the electro-optical element E progresses), the greater the change amount ΔVA.

  Since the drive transistor TDR is a p-channel type, the drive current IDR increases as the potential VG decreases as the change amount ΔVG increases (equation (1)). Further, as shown in the equation (2), the change amount ΔVG of the potential VG in the driving period PDRV is proportional to the change amount ΔVA. Therefore, the drive current IDR increases as the change amount ΔVA of the potential VA of the electrode a1 increases. That is, the drive current IDR increases as the resistance value of the electro-optic element E (the voltage between both ends when the detection current IDT is supplied) is higher.

  As described above, in the present embodiment, the drive current IDR is corrected according to the electrical characteristics of the electro-optical element E, so that the characteristic deterioration due to the deterioration of the electro-optical element E is effectively compensated. Therefore, it is possible to faithfully express the intended gradation regardless of the characteristics of the electro-optical element E.

  In the above description, it is assumed that the voltage-current characteristic of one electro-optical element E changes from the characteristic FEL_1 to the characteristic FEL_2 over time, but the electrical characteristics between the electro-optical elements E constituting the pixel unit 10 are assumed. If they are different, it is possible to suppress the gradation variation (gradation unevenness) of each electro-optic element E for the same reason as described with reference to FIG. For example, the voltage-current characteristic of one electro-optical element E of the pixel unit 10 is the characteristic FEL_1 in FIG. 6, and the voltage-current characteristic of another electro-optical element E is the characteristic FEL_2 in FIG. When gradations are designated, variations in both gradations are suppressed or eliminated. That is, according to this embodiment, it is possible to faithfully control the electro-optic element E to the intended gradation regardless of the electrical characteristics.

  A characteristic FR_1 in FIG. 6 is a voltage-current characteristic of the resistance element R when the resistance value of the resistance element R is lowered as compared with the case of the characteristic FR. As shown in the figure, the difference δ in the detection potential VDT (change amount ΔVA) between when the electro-optical element E has the characteristic FEL_1 and when it has the characteristic FEL_2 decreases as the resistance value of the resistance element R decreases. . Therefore, in order to detect the difference in characteristics of the electro-optical element E with high accuracy and sufficiently reflect the difference in the drive current IDR, the resistance element R is set to a resistance value comparable to that of the electro-optical element E. Is desirable.

<B: Second Embodiment>
FIG. 8 is a circuit diagram showing a configuration of the pixel circuit P in the second embodiment of the present invention. As shown in the figure, a feed line 181 and a feed line 182 are formed in the pixel portion 10. The transistor QE is interposed between the anode of the electro-optic element E and the power supply line 181 to control the electrical connection between them. The transistor QC is interposed between the electrode a1 of the capacitive element CA and the power supply line 182, and controls the electrical connection between them.

  The voltage generation circuit 26 generates a first potential VHH and a second potential VLL in addition to the power supply potential VEL and the ground potential VCT. As shown in FIG. 9, the first potential VHH is lower than the power supply potential VEL and higher than the ground potential VCT, and the second potential VLL is lower than the first potential VHH and higher than the ground potential VCT. is there. The first potential VHH is supplied to each pixel circuit P via the power supply line 181, and the second potential VLL is supplied to each pixel circuit P via the power supply line 181. However, the first potential VHH may be lower than the second potential VLL.

  When the transistor QE is turned on in the writing period PWRT, a detection current IDT corresponding to the first potential VHH is supplied from the power supply line 181 to the electro-optical element E via the path r2. Since the first potential VHH is lower than the power supply potential VEL, the detection current IDT supplied to the electro-optical element E in this embodiment is smaller than that in the first embodiment.

  The electro-optical element E emits light by supplying the detection current IDT in the writing period PWRT. If the amount of light emission at the time of supply of the detection current IDT is large, the gradation of the actual electro-optical element E becomes bright even when, for example, turn-off in the drive period PDRV is instructed (that is, when black is displayed). This may cause a problem that the contrast of the image is lowered. In this embodiment, since the first potential VHH that is different from the power supply potential VEL is used to generate the detection current IDT, the detection current IDT is appropriately reduced by setting the first potential VHH to a low potential. Is possible. Therefore, the contrast of the image can be maintained at a high level.

  On the other hand, when the transistor QC is turned on in the driving period PDRV, the potential VA of the electrode a1 drops from the detection potential VDT set in the writing period PWRT to the second potential VLL of the feeder line 182. That is, the change amount ΔVA of the potential VA is a difference value between the detection potential VDT and the second potential VLL. Accordingly, the gate potential VG of the drive transistor TDR is set to a potential corresponding to the second potential VLL in the drive period PDRV. As described above, since the second potential VLL different from the ground potential VCT is supplied to the electrode a1, the amount of the drive current IDR can be adjusted by appropriately selecting the second potential VLL. Therefore, there is an advantage that the gradation of the gradation over the entire pixel portion 10 can be easily adjusted.

<C: Third Embodiment>
<C-1: Configuration>
FIG. 10 is a circuit diagram showing the configuration of the pixel circuit P in the third embodiment of the present invention. As shown in the figure, the pixel circuit P of this embodiment has a configuration in which a capacitor CB and n-channel transistors QF and QG are added to the pixel circuit P of the first embodiment illustrated in FIG. .

  The transistor QF is a switching element that is interposed between the gate and drain of the driving transistor TDR and controls the electrical connection between them. When the transistor QF is turned on, the gate and drain of the driving transistor TDR are electrically connected (diode connection).

  The capacitive element CB has electrodes b1 and b2. The electrode b1 is electrically connected to the gate of the drive transistor TDR (electrode a2 of the capacitive element CA). The transistor QD is interposed between the electrode b2 and the data line 14 and controls the electrical connection between them. The transistor QG is interposed between the electrode b2 and the power supply line 185 to control the electrical connection between them. A predetermined potential (hereinafter referred to as “reset potential”) VRS is supplied to the power supply line 185 from the voltage generation circuit 26.

  FIG. 11 is a timing chart for explaining the operation of the pixel circuit P. The scanning line driving circuit 22 generates control signals Y1 [i] to Y5 [i] and outputs them to the pixel circuits P in the i-th row. The control signal Y1 [i] is supplied to the gate of the transistor QD, the control signal Y2 [i] is supplied to the gates of the transistors QF and QG, and the control signal Y3 [i] is supplied to the gates of the transistors QA and QC. The control signal Y4 [i] is supplied to the gate of the transistor QB, and the control signal Y5 [i] is supplied to the gate of the transistor QE.

  As in the first embodiment, the control signal Y1 [i] is at a high level in the writing period PWRT of the i-th row. An initialization period PRS and a compensation period PCP are set immediately before the write period PWRT, and a drive period PDRV is set immediately after the write period PWRT.

<C-2: Operation>
Next, a specific operation of the electro-optical device 100 will be described with reference to FIGS. Hereinafter, the operation of the pixel circuit P in the j-th column belonging to the i-th row will be described by being divided into an initialization period PRS, a compensation period PCP, a writing period PWRT, and a driving period PDRV. 12 to 15, the transistors QA to QG of the pixel circuit P are illustrated as switches for convenience, as in FIGS. 4 and 5.

[A] Initialization period PRS (FIG. 12)
As shown in FIGS. 11 and 12, in the initialization period PRS, the control signals Y1 [i] and Y5 [i] are set to the low level, so that the transistors QD and QE are turned off. On the other hand, the control signals Y2 [i] to Y4 [i] maintain a high level during the initialization period PRS. When the transistor QG is turned on by the control signal Y2 [i], the potential of the electrode b2 of the capacitive element CB is initialized to the reset potential VRS of the power supply line 185. In addition, as shown in FIG. 12, the transistors QA, QB, QC and QF are turned on to connect the gate of the drive transistor TDR to the power supply line 162. Therefore, the gate potential VG and the potential VA of the electrode a1 are initialized to the ground potential VCT as shown in FIG.

[B] Compensation period PCP (FIG. 13)
In the compensation period PCP, when the control signal Y3 [i] transitions to the low level, the transistors QA and QC change to the non-conducting state as shown in FIG. Since the drive transistor TDR is diode-connected by the transistor QF, the gate potential VG rises from the potential VCT immediately after initialization as shown in FIG. It converges to a difference value (VG = VEL−VTH) with respect to the threshold voltage VTH of the driving transistor TDR. On the other hand, the supply of the reset potential VRS to the electrode b2 is continued by maintaining the transistor QG in the conductive state.

  In the compensation period PCP, the control signal Y5 [i] transitions to a high level, thereby turning on the transistor QE. Therefore, as shown in FIG. 13, the detection current IDT is supplied from the power supply line 161 to the electro-optical element E via the path r2. Since the electrode a1 of the capacitive element CA is connected to the anode of the electro-optic element E via the transistor QB, the potential VA of the electrode a1 is the electro-optic element when the detection current IDT is supplied as shown in FIG. The detection potential VDT is set according to the voltage between both ends of E.

[C] Write period PWRT (FIG. 14)
In the writing period PWRT, the control signals Y3 [i] to Y5 [i] maintain the same level as the compensation period PCP. Therefore, as shown in FIG. 14, the supply of the detection current IDT to the electro-optical element E and the supply of the detection potential VDT to the electrode a1 are continued from the compensation period PCP. However, the supply of the detection current IDT and the detection potential VDT may be executed only in either the compensation period PCP or the write period PWRT.

  On the other hand, the transistor QG changes to a non-conductive state when the control signal Y2 [i] changes to the low level. Accordingly, the supply of the reset potential VRS to the electrode b2 is stopped. Further, the transistor QD becomes conductive when the control signal Y1 [i] transitions to a high level. Therefore, the electrode b2 is connected to the data line 14 as shown in FIG. In the writing period PWRT, the data signal X [j] is set to the potential VDATA corresponding to the gradation designated for the pixel circuit P, so the potential of the electrode b2 is set in the initialization period PRS and the compensation period PCP. The reset potential VRS is changed to the potential VDATA.

In the writing period PWRT, the transistor QF is turned off by the low-level control signal Y2 [i], so that the diode connection of the driving transistor TDR is released. As a result, the gate of the driving transistor TDR is in an electrically floating state. Since the impedance of the gate of the drive transistor TDR is sufficiently high, when the electrode b2 is lowered from the reset potential VRS to the potential VDATA by the change amount ΔV (ΔV = VRS−VDATA) in the above state, the potential VG of the electrode b1 is as shown in FIG. As shown in FIG. 5, the voltage drops by the change amount k · ΔV from the potential (VEL−VTH) set in the compensation period PCP. Therefore, the potential VG is set to the level of the following expression (3) at the end point of the writing period PWRT. The coefficient k is a numerical value determined in accordance with the capacitance ratio between the capacitive elements C0, CA and CB and the gate capacitance of the driving transistor TDR.
VG = VEL−VTH−k · ΔV (3)

[D] Driving period PDRV (FIG. 15)
As shown in FIG. 11, in the drive period PDRV, the control signal Y3 [i] transitions to a high level, so that the transistor QC is turned on and the electrode a1 is connected to the power line 162 as shown in FIG. Therefore, as shown in FIG. 11, the potential VA of the electrode a1 decreases by a change amount ΔVA (ΔVA = VDT−VCT) from the detection potential VDT set in the compensation period PCP and the writing period PWRT to the ground potential VCT. .

Further, since the gate of the drive transistor TDR is in the floating state in the drive period PDRV, the potential VG of the drive transistor TDR is lowered by a change amount ΔVG proportional to the change amount ΔVA of the potential VA, as shown in FIG. That is, the potential VG is set to the level of Expression (4) immediately after the start of the driving period PDRV.
VG = VEL-VTH-k. [Delta] V- [Delta] VG (4)

  Further, when the control signal Y3 [i] transits to a high level during the driving period PDRV, the transistor QA becomes conductive. That is, the path r1 of the drive current IDR is formed. Accordingly, the drive current IDR corresponding to the potential VG in the equation (4) is supplied from the power supply line 161 to the electro-optical element E via the drive transistor TDR and the transistor QA. The electro-optical element E emits light by supplying the driving current IDR.

Assuming that the drive transistor TDR operates in the saturation region, the amount of drive current IDR in the drive period PDRV is expressed by the following equation (5). In Equation (5), “β” is the gain coefficient of the driving transistor TDR, and “VGS” is the voltage between the gate and the source of the driving transistor TDR.
IDR = (β / 2) (VGS−VTH) ²
= (Β / 2) (VEL−VG−VTH) ² (5)
By substituting Equation (4), Equation (5) is transformed into Equation (6) below.
IDR = (β / 2) (k · ΔV + ΔVG) ² (6)
That is, the amount of drive current IDR does not depend on the threshold voltage VTH of the drive transistor TDR. Therefore, an error (unevenness) in gradation of the electro-optic element E due to an error in the threshold voltage VTH of each drive transistor TDR (difference from a design value or a difference from the drive transistor TDR of another pixel circuit P) is suppressed. be able to.

  Further, since the change amount ΔVG in the equation (6) is set according to the voltage between both ends of the electro-optical element E when the detection current IDR is supplied, the drive current IDR is the same as in the first embodiment. The amount of current is adjusted according to the electrical characteristics of the electro-optic element E. Therefore, also in this embodiment, it is possible to faithfully express the intended gradation regardless of the characteristics of the electro-optical element E.

<D: Modification>
Various modifications are added to the above embodiments. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

(1) Modification 1
The configuration of the pixel circuit P is changed as appropriate. For example, the transistor QA in FIG. 3 can be omitted if there is no need to limit the time for which the electro-optical element E is driven. In the configuration in which the potential VG is held in the gate capacitance of the driving transistor TDR, the capacitive element C0 in FIGS. 3 and 10 can be omitted. Further, the conductivity type of the driving transistor TDR and the transistors QA to QG is appropriately changed. That is, a configuration in which the driving transistor TDR is an n-channel type and a configuration in which the transistors QA to QG are a p-channel type are also employed.

  Further, in each of the above embodiments, the configuration in which each pixel circuit P includes the transistor QD in order to supply the data signal X [j] to each pixel circuit P in a plurality of rows in a time division manner is illustrated. On the other hand, when the electro-optical device 100 of the present invention is used as, for example, an exposure device (line head) of an image forming apparatus, a plurality of pixel circuits P are arranged only in the X direction (main scanning direction). Selection of P is unnecessary. Therefore, the transistor QD in FIGS. 3 and 10 is omitted. That is, in the configuration of FIG. 3, the data line 14 is directly connected to the gate of the drive transistor TDR, and in the configuration of FIG. 10, the data line 14 is directly connected to the electrode b2 of the capacitive element CB.

  In each of the above embodiments, the timing for turning on the transistor QE is common to the N pixel circuits P in each row. Therefore, a configuration in which N pixel circuits P share one transistor QE is also employed. That is, as shown in FIG. 16, the anode of the electro-optic element E in each of the N pixel circuits P belonging to each row is connected to the power supply line 161 through one transistor QE. When the transistor QE is turned on, the detection current IDT is simultaneously supplied from the power supply line 161 to the electro-optical elements E of the N pixel circuits P through the transistor QE.

(2) Modification 2
In each of the above embodiments, the configuration in which the resistance element R is provided in each pixel circuit P is exemplified, but the number and position of the resistance elements R are appropriately changed. For example, as shown in FIG. 17, a configuration in which M pixel circuits P belonging to each column are connected to a power supply line 161 through a common resistance element R, or as shown in FIG. 18, N pixels belonging to each row. A configuration in which the pixel circuit P is connected to the power supply line 161 through a common resistance element R is also employed. As shown in FIG. 19, all the pixel circuits P configuring the pixel unit 10 may be connected to the power supply line 161 via the common resistance element R.

(3) Modification 3
Instead of (or together with) the resistance element R in each of the above embodiments (including the configurations of FIGS. 17 to 19), a diode element may be arranged in the path r2. The diode element is formed in a process common to other elements of the pixel circuit P (for example, the electro-optical element E, the driving transistor TDR, and the transistors QA to QG). Further, the resistance between the source and drain of the transistor QE may be used instead of the resistance element R. That is, the resistance element R independent from other elements is not necessarily required in the present invention.

(4) Modification 4
In each of the above embodiments, the configuration in which the operation of connecting the electrode a1 to the power supply line 162 and the operation of supplying the drive current IDR to the electro-optical element E are executed in parallel from the start point of the drive period PDRV. These operations may be performed in separate periods. For example, a configuration in which a period in which the potential VG is set by connecting the electrode a1 and the power supply line 162 is provided between the writing period PWRT and the driving period PDRV, and supply of the driving current IDR is started in the driving period PDRV is also adopted. Is done.

(5) Modification 5
In the third embodiment, the same configuration as that of the second embodiment is adopted. That is, as shown in FIG. 20, instead of the configuration of FIG. 10, a configuration in which the transistor QE is interposed between the power supply line 181 to which the first potential VHH is supplied and the anode of the electro-optic element E, or the second potential A configuration in which the transistor QC is interposed between the power supply line 182 supplied with VLL and the electrode a1 of the capacitive element CA is also employed.

(6) Modification 6
The organic light emitting diode element is merely an example of an electro-optical element. For example, various electro-optical elements such as inorganic EL elements, LED (Light Emitting Diode) elements, and laser diode elements can be employed as the electro-optical elements E in the above embodiments. That is, all elements whose gradation changes with the supply of current are employed as the electro-optical elements of the present invention.

<E: Application example>
Next, electronic equipment using the electro-optical device according to the invention will be described. FIG. 21 to FIG. 23 show forms of electronic devices that employ the electro-optical device 100 according to any one of the forms described above as a display device.

  FIG. 21 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. Since the electro-optical device 100 uses an organic light-emitting diode element as the electro-optical element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 22 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 100 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

  FIG. 23 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The portable information terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 100.

  Note that electronic devices to which the electro-optical device according to the present invention is applied include, in addition to the devices illustrated in FIGS. 21 to 23, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, and electronic papers. Calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices with touch panels, and the like. The use of the electro-optical device according to the invention is not limited to image display. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, an optical head (writing head) that exposes a photoreceptor according to an image to be formed on a recording material such as paper is used. The electro-optical device of the present invention is also used as this type of optical head.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. 6 is a timing chart for explaining the operation of the pixel circuit. It is a circuit diagram which shows the structure of a pixel circuit. It is a circuit diagram which shows the mode of the pixel circuit in the writing period. It is a circuit diagram which shows the mode of the pixel circuit in a drive period. It is a conceptual diagram which shows the voltage-current characteristic of a resistive element or an electro-optical element. 6 is a timing chart for explaining a difference in characteristics of an electro-optic element. It is a circuit diagram which shows the structure of the pixel circuit which concerns on 2nd Embodiment of this invention. It is a conceptual diagram which shows the level of each electric potential. It is a circuit diagram which shows the structure of the pixel circuit which concerns on 3rd Embodiment. 6 is a timing chart for explaining the operation of the pixel circuit. It is a circuit diagram which shows the mode of the pixel circuit in an initialization period. It is a circuit diagram which shows the mode of the pixel circuit in a compensation period. It is a circuit diagram which shows the mode of the pixel circuit in the writing period. It is a circuit diagram which shows the mode of the pixel circuit in a drive period. FIG. 10 is a circuit diagram illustrating a configuration of an electro-optical device according to a modification. FIG. 10 is a circuit diagram illustrating a configuration of an electro-optical device according to a modification. FIG. 10 is a circuit diagram illustrating a configuration of an electro-optical device according to a modification. FIG. 10 is a circuit diagram illustrating a configuration of an electro-optical device according to a modification. It is a circuit diagram which shows the modification of the pixel circuit which concerns on 3rd Embodiment. It is a perspective view which shows the form (personal computer) of the electronic device which concerns on this invention. It is a perspective view which shows the form (cellular phone) of the electronic device which concerns on this invention. It is a perspective view which shows the form (mobile information terminal) of the electronic device which concerns on this invention. It is a circuit diagram which shows the structure of the conventional pixel circuit. It is a conceptual diagram which shows the voltage-current characteristic of a drive transistor or an electro-optical element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Electro-optical device, 10 ... Pixel part, P ... Pixel circuit, E ... Electro-optical element, TDR ... Drive transistor, QA-QG ... Transistor, C0, CA, CB ... Capacitance element, R ...... Resistance element, 12 ...... Control line group, 14 ...... Data line, 161, 162 ...... Power supply line, 181, 182, 185 ...... Feed line, 22 ...... Scan line drive circuit, 24 …… Data line drive Circuit, 26... Voltage generation circuit.

Claims (11)

An electro-optical element having a gradation corresponding to the first current flowing in the first path;
A driving transistor disposed on the first path for controlling the first current in accordance with a gate potential;
A method of driving a pixel circuit comprising: a capacitive element having a first electrode and a second electrode connected to the gate of the driving transistor,
Electrically connecting the first electrode to the electro-optic element and supplying a second current to the electro-optic element in a first period in which the gate potential of the driving transistor is set to a potential corresponding to a data signal; Then, the potential of the first electrode is set to a potential corresponding to the voltage across the electro-optic element,
In the second period after the lapse of the first period, the potential of the first electrode is changed to a predetermined potential in a state where the first electrode is electrically insulated from the electro-optic element. A method for driving a pixel circuit, characterized in that the potential of the pixel circuit is set. The first path is formed between a first power supply line to which a first power supply potential is supplied and a second power supply line to which a second power supply potential lower than the first power supply potential is supplied,
In the first period, the electro-optic is connected to the electro-optic element through a second path that connects the first feeding line to which the first potential between the first power-supply potential and the second power-supply potential is supplied and the electro-optic element. The method for driving a pixel circuit according to claim 1, wherein the second current is passed through the element. The first path is formed between a first power supply line to which a first power supply potential is supplied and a second power supply line to which a second power supply potential lower than the first power supply potential is supplied,
2. The pixel circuit according to claim 1, wherein, in the second period, the first electrode is connected to a second power supply line to which a second potential between the first power supply potential and the second power supply potential is supplied. Driving method. In the compensation period before the start of the first period, the gate potential of the drive transistor is set to a potential corresponding to the threshold voltage of the drive transistor,
4. The first electrode is electrically connected to the electro-optic element and a second current is supplied to the electro-optic element over the compensation period and the first period. A driving method of a pixel circuit according to any one of the above. The pixel circuit driving method according to claim 4, wherein a potential of a gate of the driving transistor and a potential of the first electrode are initialized to a predetermined potential in an initialization period before the start of the compensation period. An electro-optic element having a gradation according to the first current;
A driving transistor for controlling the first current according to a potential of a gate;
A method of driving a pixel circuit comprising: a capacitive element having a first electrode and a second electrode connected to the gate of the driving transistor,
In the first period, the second electrode is set to a potential corresponding to a data signal, and the first electrode is set to a potential corresponding to the electrical characteristics of the electro-optic element,
In the second period after the elapse of the first period, the potential of the first electrode is changed, and the first current corresponding to the potential of the gate of the driving transistor after the change is supplied to the electro-optical element. Circuit driving method. The electro-optic element has a pair of electrodes,
The potential according to the electrical characteristics of the electro-optic element is a voltage between the pair of electrodes when a second current is supplied to the electro-optic element in a state where the electro-optic element and the first electrode are connected. The driving method of the pixel circuit according to claim 6, wherein the potential is in accordance with the pixel voltage. An electro-optical element having a gradation corresponding to the first current flowing in the first path;
A driving transistor disposed on the first path for controlling the first current in accordance with a gate potential;
A capacitive element having a first electrode and a second electrode connected to the gate of the driving transistor;
A first switching element that controls whether or not a second current can be supplied to the electro-optic element;
A second switching element that controls electrical connection between the first electrode and the electro-optic element;
A pixel circuit comprising: a power supply line to which a predetermined potential is supplied; and a third switching element that controls electrical connection between the first electrode. In the first period in which the gate potential of the driving transistor is set to a potential corresponding to a data signal, the first switching element and the second switching element are brought into conduction, whereby the potential of the first electrode becomes Set to a potential according to a voltage across the electro-optic element when the second current is supplied;
The potential of the gate of the driving transistor is set by turning on the third switching element while the second switching element is non-conductive in a second period after the lapse of the first period. The pixel circuit according to 1. An electro-optical device comprising a pixel circuit and a drive circuit,
The pixel circuit includes:
An electro-optical element having a gradation corresponding to the first current flowing in the first path;
A driving transistor disposed on the first path for controlling the first current in accordance with a gate potential;
A capacitive element having a first electrode and a second electrode connected to the gate of the driving transistor;
A first switching element that controls whether or not a second current can be supplied to the electro-optic element;
A second switching element that controls electrical connection between the first electrode and the electro-optic element;
A third switching element that controls electrical connection between the power supply line to which a predetermined potential is supplied and the first electrode;
The drive circuit is
In the first period in which the gate potential of the driving transistor is set to a potential corresponding to a data signal, the first switching element and the second switching element are controlled to be in a conductive state and the third switching element is not in a conductive state. Control to the state,
In the second period after the lapse of the first period, the first switching element and the second switching element are controlled to be in a non-conductive state and the third switching element is controlled to be in a conductive state. Optical device. An electronic apparatus comprising the electro-optical device according to claim 10.

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