JP2010049283A - Electro-optical device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to the improvement of display quality by suppressing the potential fluctuation of a gate of a driving transistor. <P>SOLUTION: The driving transistor generates a driving current corresponding to the potential of the gate. An OLED element emits light in luminance corresponding to the driving current. The transistor switches conduction and nonconduction between the gate and drain of the driving transistor Tdr. A capacitive element includes a first electrode and a second electrode. The second electrode is connected to the gate of the driving transistor. The transistor is interposed between the first electrode and a data line supplied with data potential. A capacitive element is provided between the capacitive element and the data line and is connected between a power line and the gate of the driving transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a layout of elements constituting an electro-optical device including various electro-optical elements such as a light-emitting element made of an organic EL (ElectroLuminescent) material, and an electronic apparatus.

  In this type of electro-optic element, the gradation (typically luminance) changes with the supply of current. Conventionally, a configuration in which this current (hereinafter referred to as “drive current”) is controlled by a transistor (hereinafter referred to as “drive transistor”) has been proposed. However, in this configuration, there is a problem in that the gradation of each electro-optic element varies due to individual differences in the characteristics (particularly threshold voltage) of the drive transistor. In order to suppress this variation in gradation, for example, Patent Documents 1 and 2 disclose a configuration that compensates for differences in threshold voltages of drive transistors.

  FIG. 17 is a circuit diagram showing a configuration of the pixel circuit P0 disclosed in Patent Document 1. In FIG. As shown in the figure, a transistor Tr1 is interposed between the gate and drain of the driving transistor Tdr. One electrode L2 of the capacitive element C1 is connected to the gate of the driving transistor Tdr. The storage capacitor C2 is a capacitor interposed between the gate and source of the drive transistor Tdr. On the other hand, the transistor Tr2 is configured such that the other of the data line 103 and the capacitive element C1 to which a potential (hereinafter referred to as “data potential”) VD corresponding to the luminance specified for the organic light emitting diode element (hereinafter referred to as “OLED element”) 110 is supplied. The switching element is inserted between the first electrode L1 and switches between conduction and non-conduction.

  In the above configuration, first, the transistor Tr1 is turned on by the signal S2. When the drive transistor Tdr is diode-connected in this way, the gate potential of the drive transistor Tdr converges to “VEL−Vth” (Vth is the threshold voltage of the drive transistor Tdr). Second, the transistor Tr1 is turned off, and the transistor Tr2 is turned on by the signal S1 to make the electrode L1 of the capacitor C1 and the data line 103 conductive. By this operation, the gate potential of the drive transistor Tdr changes by a level obtained by dividing the change in potential at the electrode L1 according to the capacitance ratio between the capacitive element C1 and the storage capacitor C2 (that is, the level according to the data potential VD). To do. Third, the transistor Tr2 is turned off, and the signal Tel is used to turn on the transistor Tel. As a result, a drive current Iel that does not depend on the threshold voltage Vth is supplied to the OLED element 110 via the drive transistor Tdr and the transistor Tel. The basic principle for compensating the threshold voltage Vth of the drive transistor Tdr is the same in the configuration disclosed in Patent Document 2.

JP2003-332072A (FIG. 1) JP 2006-30635 A (FIGS. 1 to 3)

  In such a pixel circuit, for example, as shown in FIG. 18, a first capacitor C1 is arranged between the data line and the power supply line. For this reason, parasitic capacitance is generated between the conductor wiring constituting the capacitor C1 and the conductor wiring constituting the data line. In particular, when crosstalk occurs between the capacitor C1 and the data line 103 via the parasitic capacitance, and the voltage of the capacitor C1 fluctuates, the potential of the gate of the driving transistor Tdr and the driving current Iel corresponding to the potential fluctuate. Therefore, the luminance variation of the OLED element 110 occurs.

  In the pixel circuit described in Patent Document 2, a metal shield is provided around the capacitors C1 and C2 to reduce the influence of the electric field of the data line. In such a configuration, a region for providing the metal shield is secured. Therefore, there is a problem that it is difficult to achieve high integration of elements. The present invention has been made in view of such circumstances, and an object of the present invention is to solve the problem of suppressing fluctuations in the gate potential of the driving transistor and contributing to improvement in display quality.

  The present invention can be realized as the following forms or application examples.

  Application Example 1 The electro-optical device corresponds to a plurality of scanning lines including the first scanning lines, a plurality of data lines including the first data lines, and intersections of the plurality of scanning lines and the plurality of data lines. And a plurality of unit circuits including a first unit circuit and a power supply line for supplying a power supply voltage. Here, the first unit circuit includes a drive transistor that sets a drive current according to a gate voltage, an electro-optical element driven by the drive current, a first electrode, and a second electrode. A capacitive element, a first switching element that controls electrical connection between the first data line and the second electrode based on a control signal supplied via the first scanning line, a third electrode, A second capacitive element including a fourth electrode. Further, the driving transistor has a first terminal and a second terminal. The first terminal is connected to the power line. The first electrode is connected to the gate, and the third electrode is connected to the gate or the second electrode. In the first unit circuit, at least a part of the second capacitive element is disposed between the first data line and the first capacitive element. For example, in the case of FIG. 4 or FIG. 6 described later, at least a part of the second capacitor element is disposed between the first data line and the first capacitor element when viewed in plan.

  According to the application example, since the second capacitive element is disposed between the data line and the first capacitive element, it is possible to reduce the parasitic capacitance between the data line and the first capacitive element.

  Application Example 2 The electro-optical device may include a potential line that supplies a predetermined potential. Here, the plurality of data lines include a second data line, the potential line is provided in a direction in which the first data line and the second data line extend, and the first data line and the second data line are provided. Between the data lines, the first capacitive element is disposed between the second capacitive element and the potential line.

  As shown in FIGS. 4 and 6 to be described later, when viewed in plan, the first capacitor element is between the second capacitor element and the potential line between the first data line and the second data line. Is arranged.

  Application Example 3 The plurality of data lines may include a second data line. In this case, between the first data line and the second data line, the first capacitor element may be disposed between a region where the electro-optic element is disposed and the second capacitor element.

  According to the application example, the region where the electro-optic element is disposed or the second capacitor element is disposed between the first data line or the second data line and the first capacitor element. Therefore, it is possible to prevent the potential fluctuation of the first and second data lines from affecting the first capacitor element.

  Application Example 4 At least a part of the first capacitor element or the second capacitor element may be disposed below a region where the electro-optic element is disposed.

  Application Example 5 The third electrode may be connected to the second electrode. In this case, the first unit circuit includes a semiconductor pattern layer including the first semiconductor film, the first electrode, and the fourth electrode of the driving transistor, an insulating layer covering the semiconductor pattern layer, and the insulating layer. And a wiring pattern layer including the second electrode and the third electrode provided thereon. In this case, the second electrode and the third electrode are configured by a common film, and the fourth electrode is provided between the first data line and the first electrode. The fourth electrode is electrically connected to the power line.

  According to the application example, since the fourth electrode is interposed between the first data line and the first electrode, and the fourth electrode is connected to the power supply line, the first data line and the first electrode The coupling capacity between them can be reduced.

  Application Example 6 The third electrode may be connected to the gate. In this case, the first unit circuit includes a semiconductor pattern layer including the first semiconductor film, the first electrode, and the third electrode of the driving transistor, an insulating layer covering the semiconductor pattern layer, and the insulating layer. And a wiring pattern layer including the second electrode and the fourth electrode provided thereon. In this case, the first electrode and the third electrode are constituted by a second semiconductor film provided in common.

  In the above application example, if a plurality of data lines are formed in a layer higher than the wiring pattern layer or the wiring pattern layer, the plurality of data lines and the first electrode are formed by different layers. The plurality of data lines and the first electrode can be arranged three-dimensionally apart, and the coupling capacity between them can be reduced.

  Application Example 7 The third electrode may be connected to the gate. In this case, the first unit circuit includes a semiconductor pattern layer including the first semiconductor film, the second electrode, and the fourth electrode of the driving transistor, an insulating layer covering the semiconductor pattern layer, and the insulating layer. And a wiring pattern layer including the first electrode and the third electrode provided thereon. In this case, the first electrode and the third electrode are formed of a common film.

  Application Example 8 The third electrode may be connected to the second electrode. In this case, the first unit circuit includes a semiconductor pattern layer including the first semiconductor film, the second electrode, and the third electrode of the driving transistor, an insulating layer covering the semiconductor pattern layer, and the insulating layer. And a wiring pattern layer including the first electrode and the fourth electrode provided thereon. In this case, the second electrode and the third electrode are formed of a common film.

  Here, generally, the wiring pattern is thicker than the semiconductor pattern. However, the first electrode and the third electrode are configured by a common film as in Application Example 7, or the second electrode and the third electrode are commonly provided as in Application Example 8. With this configuration, it is not necessary to pattern these electrodes, and unevenness due to the wiring pattern is not formed. Therefore, with such a configuration, the electro-optic element can be arranged on the surface with less unevenness above these electrodes.

  Application Example 9 The electro-optical device corresponds to a plurality of scanning lines including the first scanning lines, a plurality of data lines including the first data lines, and intersections of the plurality of scanning lines and the plurality of data lines. A plurality of unit circuits including a first unit circuit, a power supply line for supplying a power supply voltage, and a potential line for supplying a predetermined potential. Here, the first unit circuit includes a drive transistor that sets a drive current according to a gate voltage, an electro-optical element driven by the drive current, a first electrode, and a second electrode. A capacitance element; a second capacitance element including a third electrode and a fourth electrode; and a gap between the first data line and the second electrode based on a control signal supplied via the first scan line. A first switching element for controlling the electrical connection of the first switching element, a second switching element, and a third switching element for controlling the electrical connection of the first electrode and the potential line. The drive transistor has a first terminal and a second terminal. The first terminal is connected to the power supply line, and the first electrode is connected to the gate. Further, the third electrode is connected to the gate or the second electrode, and the second switching element controls an electrical connection between the second terminal and the gate. In addition, in the first unit circuit, at least a part of the second capacitor element is disposed between the first data line and the first capacitor element.

  In the case of the configuration of the above application example, the third transistor is turned on, the initialization potential (the predetermined potential) is supplied to the second electrode of the first capacitor element, and the first switching element is turned on during the data signal writing period. When the data signal is written to the second electrode of the first capacitor element in the on state and the first switching element and the third switching element are turned off during the light emission period, the second electrode of the first capacitor element is floated during the light emission period. It becomes a state. For this reason, if a large parasitic capacitance exists between the data line and the second electrode, the voltage of the first electrode of the first capacitor element fluctuates with the voltage fluctuation of the data line, and the magnitude of the drive current is reduced. fluctuate. However, according to the configuration of the application example 9, since the second capacitive element is arranged between the data line and the first capacitive element, the parasitic capacitance between the data line and the first capacitive element can be reduced. Can do.

  Application Example 10 An electronic apparatus may include the electro-optical device.

  Application Example 11 An electro-optical device includes a plurality of unit circuits (for example, a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines). 400) shown in FIG. 1 and a plurality of power supply lines for supplying a power supply voltage (for example, 33 shown in FIG. 1) may be included. In this case, each of the plurality of unit circuits includes a first terminal, a second terminal, and a gate terminal connected to the power supply line, and a driving current that flows between the first terminal and the second terminal. A drive transistor whose current level changes according to the voltage of the gate terminal, an electro-optic element driven by the drive current, a first electrode (for example, L1a shown in FIG. 2), and a second electrode (for example, FIG. L1b) shown in FIG. 2, the first capacitor having the first electrode connected to the gate terminal, the data line and the second electrode based on a control signal supplied via the scanning line, The first switching element (for example, shown in FIG. 2) supplies the data signal supplied to the data line to the gate terminal via the first capacitive element when the electrical connection of the first and second data lines is controlled and is in the ON state. Tr1) and the third electrode 4 and an electrode, when supplying the driving current to the electro-optical element from the drive transistor, and a second capacitor for holding a potential of the gate terminal and the second electrode. Further, the first capacitor element and the second capacitor element are disposed adjacent to each other, and a part or all of the second capacitor element is disposed between the data line and the first capacitor element. Yes.

  According to the application example, since the second capacitive element is disposed between the data line and the first capacitive element, it is possible to reduce the parasitic capacitance between the data line and the first capacitive element. As a result, it is possible to suppress crosstalk in which the voltage fluctuation of the data line fluctuates the gate voltage of the driving transistor, and display quality can be greatly improved. Note that it is not necessary for the entire second capacitor element to be disposed between the data line and the first capacitor element, and a portion thereof may be disposed. For example, the connection wiring between the first capacitor element and the drive transistor may be arranged on the data line side with respect to the second capacitor element. Even in this case, since the first capacitor element faces the data line with a part of the second capacitor element, the parasitic capacitance can be reduced.

  Application Example 12 The electro-optical device may include a plurality of potential lines for supplying an initialization potential. In this case, the potential line is arranged in parallel to the data line, and a unit line adjacent to the data line of the unit circuit, the second capacitor element, the first capacitor element, the potential line, and the unit circuit. It is preferable to arrange in the order of the data lines of the circuit.

  According to the application example, the potential line is arranged between the first capacitor element and the data line of the adjacent unit circuit. Since this potential line is supplied with a fixed initialization potential, the parasitic capacitance between the first capacitor element and the data line of the adjacent unit circuit can be greatly reduced. As a result, display quality can be further improved by suppressing crosstalk from the data lines of the unit circuit and the adjacent unit circuit. In Application Example 12, the arrangement of the potential line and the data line in parallel means that the potential line and the data line are arranged so as not to cross each other. Therefore, there are those that are manufactured in the intention that the potential lines and the data lines do not cross each other but are not strictly parallel for manufacturing reasons.

  Application Example 13 The second electrode of the first capacitor element, the fourth electrode of the second capacitor element, the plurality of data lines, and the plurality of potential lines are formed in the same wiring layer, and the electric The optical element may be formed of a layer located above the wiring layer.

  According to the above application example, since the second electrode, the fourth electrode, the data line, and the potential line are formed by the wiring layer, the unevenness of the underlying layer of the layer that forms the electro-optic element is reduced, so that it is substantially flat. An electro-optic element can be formed on the base. As a result, the characteristics of the electro-optic element can be made uniform.

  Application Example 14 The driving transistor includes a semiconductor layer and an insulating layer formed on the semiconductor layer, the wiring layer is formed on the insulating layer, and the first capacitor element includes the wiring layer. The first electrode and the third electrode of the second capacitor element may be formed of the semiconductor layer.

  According to the application example, the first capacitor element is configured by the first electrode provided in the semiconductor layer, the second electrode provided in the wiring layer, and the insulating film provided therebetween, and is provided in the semiconductor layer. Since the second capacitor element is configured by the third electrode, the fourth electrode provided in the wiring layer, and the insulating film provided therebetween, the capacitance value per unit area can be increased. As a result, the area occupied by the first capacitor element and the second capacitor element can be reduced.

  Application Example 15 Each of the plurality of unit circuits controls electrical connection between the second switching element that controls electrical connection between the second terminal and the gate, and the first electrode and the potential line. And a third switching element. In this case, it is preferable that the first capacitor element, the second capacitor element, the drive transistor, and the first switching element are not disposed below the region where the electro-optic element is disposed. Further, when the electro-optic element is configured by a bottom emission type that extracts light to the side where the semiconductor layer and the wiring layer are provided, each of the unit circuits includes the second terminal of the driving transistor and the second terminal. A second switching element that controls electrical connection with the gate terminal; and a third switching element that controls electrical connection between the first electrode of the first capacitor and the potential line. . In this case, it is preferable that the first capacitor element, the second capacitor element, the driving transistor, and the first switching element are not disposed below the region where the electro-optic element is disposed. In addition, it is preferable that the second switching element and the third switching element are not disposed below a region where the electro-optic element is disposed.

  According to the above application example, since no wiring, capacitive element, transistor, or switching element is formed below the electro-optic element, light is not blocked by those structures.

  Application Example 16 It is preferable that at least a part of the first capacitive element or the second capacitive element is disposed below a region where the electro-optic element is disposed. When the electro-optical element is configured by a top emission type that extracts light emitted from the side opposite to the side on which the semiconductor layer or the wiring layer is provided, the area below the region where the electro-optical element is disposed Preferably, a part or all of the first capacitor element and a part or all of the second capacitor element are arranged.

  According to the application example, the region where the electro-optic element is formed and the region where the first capacitor element and the second capacitor element are formed can be three-dimensionally overlapped in the vertical direction, so that the aperture ratio can be improved and higher A fine image can be displayed.

  Application Example 17 In the electro-optical device, a plurality of unit circuits (for example, a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines) 400) shown in FIG. 1, a plurality of power supply lines for supplying a power supply voltage, and a plurality of potential lines for supplying an initialization potential (for example, 33 shown in FIG. 1) may be included. In this case, each of the plurality of unit circuits includes a first terminal, a second terminal, and a gate terminal connected to the power supply line, and a driving current that flows between the first terminal and the second terminal. A drive transistor whose current level changes according to the voltage of the gate terminal, an electro-optic element driven by the drive current, a first electrode (for example, L1a shown in FIG. 2), and a second electrode (for example, FIG. L1b shown in FIG. 2 and the first electrode having the first electrode connected to the gate terminal, the third electrode (eg L2a shown in FIG. 2), and the fourth electrode (eg shown in FIG. 2) L2b), the third electrode is connected to the gate terminal, the fourth electrode is connected to the power supply line, and a control signal supplied via the scanning line , The second power of the data line and the first capacitive element. A first switching element (for example, Tr1 shown in FIG. 2) that controls electrical connection between the driving transistor and a second switching element (for example, that controls electrical connection between the second terminal and the gate terminal of the driving transistor). Tr2) shown in FIG. 2 and a third switching element (for example, Tr3 shown in FIG. 2) for controlling the electrical connection between the first electrode of the first capacitor and the potential line. The first capacitive element and the second capacitive element are disposed adjacent to each other, and a part or all of the second capacitive element is disposed between the data line and the first capacitive element. Yes.

  According to the application example, the third transistor is turned on to supply the initialization potential to the second electrode of the first capacitor element, and in writing the data signal, the first switching element is turned on and the data signal is sent to the first electrode. Write to the second electrode of the capacitor. In the light emission period, the first switching element and the third switching element are turned off. Accordingly, the second electrode of the first capacitor element is in a floating state during the light emission period. For this reason, if a large parasitic capacitance exists between the data line and the second electrode, the voltage of the first electrode of the first capacitor element varies with the voltage variation of the data line, and the magnitude of the drive current varies. . According to this electro-optical device, since the second capacitive element is disposed between the data line and the first capacitive element, it is possible to reduce the parasitic capacitance between the data line and the first capacitive element. As a result, it is possible to suppress crosstalk in which the voltage fluctuation of the data line fluctuates the gate voltage of the driving transistor, and display quality can be greatly improved. Note that it is not necessary for the entire second capacitor element to be disposed between the data line and the first capacitor element, and a portion thereof may be disposed. For example, the connection wiring between the first capacitor element and the drive transistor may be arranged on the data line side with respect to the second capacitor element. Even in this case, since the first capacitor element faces the data line with a part of the second capacitor element, the parasitic capacitance can be reduced.

  In another form, the electronic apparatus may include the above-described electro-optical device. For example, a mobile phone, a personal computer, or an electronic still camera corresponds to the electronic device. However, the use of the electro-optical device is not limited to image display. For example, in an image forming apparatus (printing apparatus) configured to form a latent image on an image carrier such as a photosensitive drum by irradiation of light, the electro-optical device is used as means for exposing the image carrier (so-called exposure head). Can be adopted.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a pixel circuit. The timing chart which shows the waveform of each signal. FIG. 3 is a plan view conceptually showing a configuration of a main part of the electro-optical device. FIG. 3 is a cross-sectional view conceptually showing a configuration of a main part of the electro-optical device. FIG. 10 is a plan view conceptually showing the configuration of a main part of an electro-optical device according to a modification. FIG. 6 is a cross-sectional view conceptually showing the configuration of a main part of an electro-optical device according to a modification. The circuit diagram which shows the structure of the pixel circuit which concerns on a modification. FIG. 10 is a plan view conceptually showing the configuration of a main part of an electro-optical device according to a modification. FIG. 6 is a cross-sectional view conceptually showing the configuration of a main part of an electro-optical device according to a modification. (A) And (b) is the top view and sectional drawing which show notionally the structure of the principal part of the electro-optical apparatus which concerns on a modification. (A) And (b) is the top view and sectional drawing which show notionally the structure of the principal part of the electro-optical apparatus which concerns on a modification. (A) And (b) is the top view and sectional drawing which show notionally the structure of the principal part of the electro-optical apparatus which concerns on a modification. FIG. 11 is a perspective view showing a specific form of the electronic apparatus of the embodiment. FIG. 11 is a perspective view showing a specific form of the electronic apparatus of the embodiment. FIG. 11 is a perspective view showing a specific form of the electronic apparatus of the embodiment. FIG. 6 is a circuit diagram showing a configuration of a conventional pixel circuit. The top view which shows the structure of the conventional pixel circuit.

<A: Configuration of electro-optical device>
The electro-optical device of this embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the present embodiment. As shown in the figure, the electro-optical device 1 includes a pixel region A, a scanning line driving circuit 100, a data line driving circuit 200, a control circuit 300, and a power supply circuit 500. Among these, in the pixel region A, m scanning lines 10 extending in the X direction, m power lines 31 extending in the X direction in pairs with each scanning line 10, and orthogonal to the X direction. N data lines 103 extending in the Y direction are formed. A pixel circuit 400 is disposed at a position corresponding to each intersection of the scanning line 10 and the data line 103. Therefore, these pixel circuits 400 are arranged in a matrix of m rows × n columns.

  The scanning line driving circuit 100 is a circuit for selecting and operating the pixel circuits 400 arranged in the pixel region A in units of rows for each horizontal scanning period. On the other hand, the data line driving circuit 200 generates a data voltage Vdata corresponding to each of one row (n) of pixel circuits 400 selected by the scanning line driving circuit 100 in each horizontal scanning period, and generates each data line 103. Output to. This data voltage Vdata is a voltage corresponding to the gradation (luminance) designated for each pixel circuit 400.

  The control circuit 300 controls each circuit by supplying various control signals such as a clock signal to the scanning line driving circuit 100 and the data line driving circuit 200, and also outputs image data specifying the gradation of each pixel circuit 400. This is supplied to the line driving circuit 200. On the other hand, the power supply circuit 500 generates a higher voltage (hereinafter referred to as “power supply voltage”) Vdd, a lower voltage (hereinafter referred to as “ground voltage”) Vss, and an initialization potential VST. The power supply voltage Vdd is supplied to each pixel circuit 400 through the power supply line 31. Further, the ground voltage Vss is supplied to all the pixel circuits 400 via a predetermined wiring (the ground line 32 shown in FIG. 2). The ground voltage Vss is a potential serving as a voltage reference. The initialization potential VST is supplied to each pixel circuit 400 via the initialization power supply line 33.

  Next, the configuration of each pixel circuit 400 will be described with reference to FIG. In the drawing, only one pixel circuit 400 in the j-th column (j is an integer satisfying 1 ≦ j ≦ n) belonging to the i-th row (i is an integer satisfying 1 ≦ i ≦ m) is illustrated. However, the other pixel circuits 400 have the same configuration. Note that the conductivity type of each transistor included in the pixel circuit 400 is not limited to that illustrated in FIG. A typical example of each transistor shown in FIG. 2 is a thin film transistor using low-temperature polysilicon as a semiconductor layer, but the form and material of each transistor are not limited at all.

  As shown in FIG. 2, the pixel circuit 400 includes an OLED element 420 and a p-channel each inserted between a power supply line 31 to which a power supply voltage Vdd is supplied and a ground line 32 to which a ground voltage Vss is supplied. Type transistor (hereinafter referred to as “driving transistor”) Tdr. The OLED element 420 is an element that emits light with luminance according to a forward current (hereinafter referred to as “driving current”), and has a structure in which a light emitting layer made of an organic EL material is interposed between an anode and a cathode. It has become. The light emitting layer is formed, for example, by discharging a droplet of an organic EL material from an inkjet (droplet discharge) head and drying it. The cathode of the OLED element 420 is connected to the ground line 32. On the other hand, the drive transistor Tdr is a transistor for controlling the drive current flowing through the OLED element 420.

  In addition, as a material of the OLED element 420, an organic light emitting material such as a low molecule / polymer or a dendrimer is used. However, the OLED element 420 is only an example of a light emitting element. That is, instead of the OLED element 420, an inorganic EL element, a field emission (FE) element, a surface-conduction electron (SE) element, a ballistic electron surface emitting (BS) element Various self-luminous elements such as LED (Light Emitting Diode) elements, electrophoretic elements, electrochromic elements, and the like may be used. The present invention is also applied to an exposure apparatus such as a write head used in an optical writing type printer or an electronic copying machine, as in this embodiment. Furthermore, for example, the present invention is also applied to a sensing device such as a biochip.

  In FIG. 1, the scanning line 10 shown as one wiring for convenience is actually the first control line 11, the second control line 12, the third control line 13, and the fourth control as shown in FIG. Includes line 14. A first control signal Sc1 [1] to Sc1 [m] for defining a period during which the data voltage Vdata is taken into the pixel circuit 400 is supplied from the scanning line driving circuit 100 to the first control line 11 of each row. Further, second control signals Sc2 [1] to Sc2 [m] for defining the compensation period of the pixel circuit 400 are supplied from the scanning line driving circuit 100 to the second control lines 12 in each row. Further, the third control signal Sc3 [1] to Sc3 [m] for defining the initialization period of the pixel circuit 400 is supplied from the scanning line driving circuit 100 to the third control line 13 of each row. Further, fourth control signals Sc4 [1] to Sc4 [m] for defining the light emission period of the pixel circuit 400 are supplied from the scanning line driving circuit 100 to the fourth control line 14 of each row.

  The pixel circuit includes an n-channel transistor Tr1, a transistor Tr2, a transistor Tr3, and a transistor Tr4. The gate electrodes of the transistors Tr1 to Tr4 are supplied with a first control signal Sc1 [i], a second control signal Sc2 [i], a third control signal Sc3 [i], and a fourth control signal Sc4 [i], respectively. Are connected to the first control line 11, the second control line 12, the third control line 13, and the fourth control line 14.

  The light emission control transistor Tr4 is provided as a switching element for controlling whether or not a drive current can be supplied from the drive transistor Tdr to the OLED element 420. The drain electrode is connected to the anode of the OLED element 420 and the source electrode is This is an n-channel transistor connected to the drain electrode of the drive transistor Tdr. The gate electrode of the light emission control transistor Tr4 is connected to the fourth control line. Accordingly, the light emission control transistor Tr4 is turned on when the fourth control signal Sc4 [i] supplied to the fourth control line 14 is at a high level, and is turned off when it is at a low level.

  The transistor Tr1 is an n-channel transistor having a source electrode connected to the data line 103 and a drain electrode connected to the second electrode L1b of the capacitor C1, and the transistor Tr1 is electrically connected to the data line 103. It functions as a switching element for switching non-conduction. The gate electrode of the transistor Tr1 is connected to the first control line 11. Therefore, the first transistor Tr1 is turned on when the first control signal Sc1 [i] is at a high level, and is turned off when the first control signal Sc1 [i] is at a low level. When the transistor Tr1 is on, the data line voltage Vdata is supplied to the second electrode L1b of the capacitor C1.

  The transistor Tr2 is provided for compensation of the drive transistor Tdr, and has an n-channel type whose drain electrode is connected to the drain electrode of the drive transistor Tdr and whose source electrode is connected to the gate electrode of the drive transistor Tdr. It is a transistor. The gate electrode of the transistor Tr2 is connected to the second control line 12. Therefore, the transistor Tr2 is turned on when the second control signal Sc2 [i] is at a high level, and is turned off when the second control signal Sc2 [i] is at a low level. When the transistor Tr2 is turned on, the drive transistor Tdr is configured to function as a diode with the gate electrode and the source electrode conducting.

  The capacitive element C1 is provided to hold a voltage corresponding to the gradation signal, and is a capacitor that holds charges between the first electrode L1a and the second electrode L1b. The first electrode L1a is connected to the gate electrode of the drive transistor Tdr, and the second electrode L1b is connected to the drain electrode of the transistor Tr1. The capacitive element C2 is provided to hold a compensation voltage for the driving transistor Tdr, and is a capacitor that holds charges between the first electrode L2a and the second electrode L2b. The first electrode L2a is connected to the gate electrode of the drive transistor Tdr, and the second electrode L2b is connected to the power supply line 31.

  The transistor Tr3 is provided for initialization, and is an n-channel transistor having a drain electrode connected to the initialization power line 33 and a source electrode connected to the second electrode L1b of the capacitor C1. is there. The gate electrode of the transistor Tr3 is connected to the third control line 13. Therefore, the transistor Tr3 is turned on when the third control signal Sc3 [i] is at a high level, and is turned off when the third control signal Sc3 [i] is at a low level.

<B: Operation of the electro-optical device>
FIG. 3 is a timing chart showing waveforms of signals supplied to the pixel circuit 400. As shown in the figure, the first control signals Sc1 [1] to Sc1 [m] are sequentially set to the high level for each horizontal scanning period (1H) within the vertical scanning period (1V). The driving of the pixel circuits 400 in each row is performed by operations of initialization, compensation, writing, and light emission steps. First, in the initialization operation, the scanning line driving circuit 100 sets the first control control signal Sc1 [i] in the i-th row to a low level, the second control control signal Sc2 [i] in the i-th row, and the third control control. The signal Sc3 [i] and the fourth control control signal Sc4 [i] are set to the high level. As a result, the transistor Tr1 is turned off, and the transistor Tr2, the transistor Tr3, and the transistor Tr4 are turned on. At this time, the initialization potential VST (for example, low potential) of the initialization power supply line 33 is supplied to the second electrode L1b of the first capacitive element C1, while the first electrode L1a is OLED through the transistor Tr2 and the transistor Tr4. Connected to element 420. As a result, the potential at both ends of the first capacitive element C1 is initialized, and the charge accumulated in the capacitive element C1 is discharged.

  Thereafter, in the compensation operation, the scanning line driving circuit 100 sets only the second control control signal Sc2 [i] to the high level, the first control control signal Sc1 [i], the third control control signal Sc3 [i], and the fourth control signal. The control signal Sc4 [i] is set to the low level. As a result, the transistor Tr2 is turned on, the transistor Tr1, the transistor Tr3, and the transistor Tr4 are turned off, the voltage VG of the gate electrode of the driving transistor Tdr converges to “Vdd−Vth”, and the voltage of −Vth is applied to the capacitor C2. Will be held. Here, Vth is a threshold value of the driving transistor Tdr.

Thereafter, in the write operation, the data line drive circuit 200 supplies the write voltage Vdata to each corresponding data line 103 in accordance with an instruction from the control circuit 300, and the scan line drive circuit 100 receives the first control control signal Sc1. Only [i] is set to the high level, and the second control control signal Sc2 [i], the third control control signal Sc3 [i], and the fourth control control signal Sc4 [i] are set to the low level. As a result, the transistor Tr1 is turned on, the transistor Tr2, the transistor Tr3, and the transistor Tr4 are turned off, and the voltage Vdata of the data line 103 is supplied to the second electrode L1b of the first capacitor C1. The voltage of the second electrode L1b changes from the initialization potential VST set in the initialization operation to the data voltage Vdata. When the voltage of the second electrode L1b changes by ΔV (ΔV = VST−Vdata) in this way, the voltage VG of the gate electrode of the driving transistor Tdr is changed by the capacitive coupling between the first capacitive element C1 and the second capacitive element C2. The voltage (Vdd−Vth) immediately before the level ΔVb divided by the level divided by the ratio of the capacitance Ca of the first capacitor C1 and the capacitance Cb of the second capacitor C2 to the voltage change ΔV at the two electrodes L1b. ) Will change. Since the change in the voltage VG at the connection point NG is expressed as “ΔV · Ca / (Ca + Cb)”, the voltage VG at the connection point NG is expressed by the following equation by the write operation.
VG = Vdd-Vth-.DELTA.V.Ca / (Ca + Cb) (1)

After the writing is completed, the scanning line driving circuit 100 sets only the fourth control control signal Sc4 [i] to the high level, the first control control signal Sc1 [i], the second control control signal Sc2 [i], and the third control. The control signal Sc3 [i] is set to the low level. As a result, the transistor Tr4 is turned on, the transistor Tr1, the transistor Tr2, and the transistor Tr3 are turned off, and the drive current Iel corresponding to the gate-source voltage of the drive transistor Tdr flows through the OLED element 420. Since the voltage of the gate electrode with respect to the source electrode of the drive transistor Tdr is “− (VG−Vdd)”, the drive current Iel is expressed by the following equation.
Iel = (1/2) β (Vdd−VG−Vth) ² (2)
By substituting equation (1) into equation (2), the following equation can be obtained.
Iel = (1/2) β (k · ΔV) ² (3)
However, k is “Ca / (Ca + Cb)”. As shown in the equation (3), the drive current Iel supplied to the OLED element 420 is determined only by the difference ΔV (= Vdd−Vdata) between the data voltage Vdata and the power supply voltage Vdd, and the threshold of the drive transistor Tdr. It does not depend on the voltage Vth. That is, also in this embodiment, it is possible to compensate for the variation in the threshold voltage Vth of the drive transistor Tdr in each pixel circuit 400 and to cause the OLED element 420 to emit light with a desired luminance with high accuracy.

<C: Structure of capacitive element>
4 is a plan view conceptually showing the structure of one pixel of the electro-optical device configured as described above, and FIG. 5 is a cross-sectional view taken along the line aa ′ in FIG. In FIG. 4, a semiconductor layer (also referred to as a semiconductor pattern layer), a gate wiring layer (“first wiring layer” in the figure; also referred to as a lower wiring pattern layer), and a source wiring layer (“second wiring layer in the figure”). "; Also referred to as the upper wiring pattern layer), these layers are formed on a substrate such as glass as shown in FIG. 5, and layers such as insulating layers are provided between the layers. Although interposed, it is omitted for convenience of illustration. An insulating layer (also referred to as an upper insulating layer) is formed on the source wiring layer (upper wiring pattern layer), and the source wiring is connected to the insulating layer (upper insulating layer) via a terminal T0. An OLED element 420 connected to the layers is formed. Further, a common electrode (ground) is formed on the OLED element 420, but these are not shown.

  Each of the above-described transistors Tr1 to Tr4, Tdr has a structure including a semiconductor layer (semiconductor pattern layer) and a gate wiring layer (lower wiring pattern layer). A lower insulating layer is provided between the gate wiring layer and the semiconductor layer. The common electrode (corresponding to L1a and L2a) provided in the semiconductor layer and the electrodes (L1b and L2b) provided in the gate wiring layer are provided. A capacitive element C1 and a capacitive element C2 are formed therebetween. In this electro-optical device, the capacitive element C 2 is disposed between the capacitive element C 1 and the data line 103.

  Specifically in this embodiment, it is as follows. On the underlying surface such as the surface of the glass substrate, the respective semiconductor films in which the channel regions of the drive transistor Tdr and the transistors Tr1 to Tr4 are defined, the first electrode L1a of the capacitive element C1, and the first of the capacitive element C2 A semiconductor pattern layer including an electrode L2a is provided. The semiconductor film in which the channel region is defined, and the first electrode L1a and the first electrode L2a are formed by selectively performing impurity implantation on the solid semiconductor film formed on the base surface and further patterning. It is divided. By the selective impurity implantation, the conductivity of the first electrode L1a and the first electrode L2a is better than the conductivity of the semiconductor film in which the channel region is defined, but in this embodiment, the first electrode Both L1a and the first electrode L2a are defined as being part of the “semiconductor layer”, ie, “semiconductor pattern layer”.

  The semiconductor pattern layer is covered with the lower insulating layer. On the lower insulating layer, a lower wiring pattern layer including the data line 103, the second electrode L1b of the capacitive element C1, the second electrode L2b of the capacitive element C2, and the initialization power line 33 is provided. It has been. Further, the lower wiring pattern layer is covered with an upper insulating layer.

  The reason for adopting such a layout is as follows. That is, the data voltage Vdata to be written to the pixel circuits 400 in each row is supplied to the data line 103 every horizontal scanning period H. Therefore, the potential of the data line 103 varies every horizontal scanning period H. In an unselected row, the transistor Tr1 is turned off, and ideally, the potential of the second electrode L1b of the first capacitor C1 does not change. However, in the actual layout, there is a parasitic capacitance between the second electrode L1b and the data line 103. For this reason, the second electrode L1b and the data line 103 are capacitively coupled through the parasitic capacitance, and the potential of the second electrode L1b varies. In order to suppress fluctuations in the potential of the second electrode L1b, it is important to reduce the parasitic capacitance. If the first capacitive element C1 is arranged closer to the data line 103 than the second capacitive element C2, the parasitic capacitance increases and the potential of the second electrode L1b varies greatly. Therefore, the second capacitor element C2 is provided between the first capacitor element C1 and the data line 103, and the distance between the first capacitor element C1 and the data line 103 is increased.

According to this layout, the parasitic capacitance can be reduced and the crosstalk between the capacitive element C1 and the data line 103 can be reduced. As a result, fluctuations in the potential of the gate of the drive transistor Tdr due to fluctuations in the potential of the capacitive element C1 can be suppressed, contributing to improvement in display quality. As shown in FIG. 5, which is a cross-sectional view taken along the line aa ′ in FIG. 4, in the present embodiment, the data line 103, the second electrode L1b of the capacitive element C1, and the second electrode L2b of the capacitive element C2 The first electrode L1a of the capacitive element C1 and the first electrode L2a of the capacitive element C2 are provided by a semiconductor layer. Thus, it is preferable that the first electrode L1a of the capacitive element C1, the first electrode L2a of the capacitive element C2, and the data line 103 are formed of different layers. Here, the first electrode L1a of the capacitive element C1 is connected to the power supply line 31 to which the power supply voltage Vdd is supplied. Therefore, although the power supply voltage Vdd is supplied to the first electrode L1a, the first electrode L1a may be connected to another wiring supplied with a fixed potential.
In this embodiment, since the first electrode L1a of the capacitive element C1 and the first electrode L2a of the capacitive element C2 are common electrodes provided in the semiconductor layer, the layout area is reduced, which contributes to high integration. be able to. Further, since the first electrode L1a of the capacitive element C1, the first electrode L2a of the capacitive element C2, the data line 103, the initialization power supply line 33 and the like are formed on the same plane of the first wiring layer, the transparent electrode layer The planarity of the light emitting functional layer can be improved. Thereby, it can contribute to the improvement of display quality.

<D: Modification>
Various modifications can be made to each of the above embodiments.

  (1) For example, in the above-described embodiment, the example in which the OLED element 420 is configured as the bottom emission type as illustrated in FIGS. 4 and 5 has been described. However, for example, as illustrated in FIGS. It can also be configured as. In the top emission type OLED element 420 shown in FIG. 7, light is emitted upward. For this reason, a reflective metal is provided to reflect light directed downward from the light emitting functional layer. In the top emission type, a circuit element can be laid out in a region below the OLED element 420. In this example, the first capacitor element C1 and the second capacitor element C2 are arranged.

  As shown in FIG. 6, the layout is made in the order of data line 103 → second capacitor element C2 → first capacitor element C1 → initialization power line 33 → data line 103 in the X direction. In the top emission type, since the first capacitor element C1 can be disposed in the region where the OLED element 420 is formed, the first capacitor element C1 is separated from the data line 103a of the pixel circuit 400 via the second capacitor element C2. However, the distance from the data line 103b of the adjacent pixel circuit is reduced. However, the initialization power supply line 33 is disposed between the first capacitor element C1 and the data line 103b. Since the initialization power supply line 33 is supplied with a fixed initialization potential VST, the parasitic capacitance between the first capacitor element C1 and the data line 103b can be reduced. As a result, crosstalk between the capacitive element C1 and the data line 103b of the adjacent pixel circuit can be reduced, and the quality of the display image can be improved. In addition, since the OLED element 420 and various circuit elements can be three-dimensionally laid out, it is possible to improve the aperture ratio and display a higher definition image.

  (2) In the above embodiment, the first electrode L2a (third electrode) of the capacitive element C2 is electrically connected to the first electrode L1a (first electrode) of the capacitive element C1. However, as shown in FIG. 8, the first electrode L2a (third electrode) of the capacitive element C2 may be electrically connected to the second electrode L1b (second electrode) of the capacitive element C1.

  (3) In the above embodiment, the data line 103 is included in the lower wiring pattern layer provided on the lower insulating layer. However, as shown in FIGS. 9 and 10, the data line 103 m may be included in the upper wiring pattern layer 706 provided on the upper insulating layer 705 covering the lower wiring pattern layer 704.

  (4) In FIGS. 4 to 7, the first electrode L2a (third electrode) of the capacitive element C2 is electrically connected to the gate of the drive transistor Tdr. In this case, the first electrode L1a (first electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 are formed of a common semiconductor film in the semiconductor pattern layer. Since the data line 103 is located on the lower insulating layer that covers the semiconductor pattern layer, the common semiconductor film and the data line 103 can be separated three-dimensionally in this way. Therefore, the coupling capacitance between the common semiconductor film and the data line 103 can be reduced.

  On the other hand, as shown in FIGS. 11A and 11B, the first electrode L2a (third electrode) of the capacitive element C2 is electrically connected to the second electrode L1b (second electrode) of the capacitive element C1. In this case, the second electrode L1b (second electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 may be formed of a common semiconductor film.

  In this case, specifically, a semiconductor film (not shown) in which the channel region of the driving transistor Tdr is defined on the base surface such as the surface of the glass substrate 701, and the second electrode L1b (second electrode) of the capacitive element C1. ) And a first electrode L2a (third electrode) of the capacitive element C2 is provided. The semiconductor pattern layer 702 is covered with the lower insulating layer 703. Further, a lower wiring pattern layer 704 including a first electrode L1a (first electrode) of the capacitive element C1 and a second electrode L2b (fourth electrode) of the capacitive element C2 is provided on the lower insulating layer 703. ing. In this modification, the data line 103 is also included in the lower wiring pattern layer 704. The lower wiring pattern layer 704 is covered with an upper insulating layer 705.

  Thus, the first electrode L1a (first electrode) of the capacitive element C1, the second electrode L2b (fourth electrode) of the capacitive element C2, and the data line 103 are included in the common lower wiring pattern layer 704. It is. In addition, since the second electrode L2b (fourth electrode) of the capacitive element C2 is interposed between the first electrode L1a (first electrode) of the capacitive element C1 and the data line 103, the coupling capacitance can be reduced. it can. Note that the second electrode L2b (fourth electrode) of the capacitor C2 is preferably connected to a constant potential wiring. For example, the constant potential wiring is the power supply line 31.

  12A and 12B, when the first electrode L2a (third electrode) of the capacitive element C2 is electrically connected to the gate of the driving transistor Tdr, the capacitive element C1 The first electrode L1a (first electrode), the first electrode L2a (third electrode) of the capacitive element C2, and the data line 103 are included in the lower wiring pattern layer 704 provided on the lower insulating layer 703. It may be. Furthermore, the first electrode L1a (first electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 may be configured by a common electrode film.

  In this case, specifically, a semiconductor film (not shown) in which the channel region of the driving transistor Tdr is defined on the base surface such as the surface of the glass substrate 701, and the second electrode L1b (second electrode) of the capacitive element C1. ) And the second electrode L2b (fourth electrode) of the capacitive element C2 is provided. The semiconductor pattern layer 702 is covered with the lower insulating layer 703. Further, a lower wiring pattern layer 704 including a first electrode L1a (first electrode) of the capacitive element C1 and a first electrode L2a (third electrode) of the capacitive element C2 is provided on the lower insulating layer 703. ing. In the lower wiring pattern layer 704, the first electrode L1a (first electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 are configured by a common electrode film. In this modification, the data line 103 is also included in the lower wiring pattern layer 704. The lower wiring pattern layer 704 is covered with an upper insulating layer 705.

  Further, when this configuration is applied to a top emission type configuration, the first electrode L1a (first electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 are compared with FIG. It is not necessary to pattern the lower wiring pattern layer 704 between the first and second wiring patterns. For example, the thickness of the film included in the semiconductor pattern layer 702 is about 100 nm, and the thickness of the film included in the lower wiring pattern layer 704 is about 500 nm. Generally, since the wiring pattern is thicker than the semiconductor pattern, unevenness is reduced when the semiconductor pattern layer 702 is patterned between the capacitive element C1 and the capacitive element C2 than when the lower wiring pattern layer 704 is patterned. be able to. Therefore, with such a structure, unevenness of the light-emitting element can be reduced.

  Further, as shown in FIGS. 13A and 13B, the first electrode L2a (third electrode) of the capacitive element C2 is electrically connected to the second electrode L1b (second electrode) of the capacitive element C1. In the case where the first electrode L2a (third electrode) of the capacitive element C2 and the second electrode L1b (second electrode) of the capacitive element C1 are provided, the lower wiring pattern layer 704 provided on the lower insulating layer 703. May be included.

  In this case, specifically, a semiconductor film (not shown) in which a channel region of the driving transistor Tdr is defined on the base surface such as the surface of the glass substrate 701, and the first electrode L1a (first electrode) of the capacitive element C1. ) And the second electrode L2b (fourth electrode) of the capacitive element C2 is provided. The semiconductor pattern layer 702 is covered with the lower insulating layer 703. Further, a lower wiring pattern layer 704 including the second electrode L1b (second electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 is provided on the lower insulating layer 703. ing. Here, in the lower wiring pattern layer 704, the second electrode L1b (second electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2 are configured by a common electrode film. . The lower wiring pattern layer 704 is covered with an upper insulating layer 705.

  Even in this case, it is not necessary to pattern the lower wiring pattern layer 704 between the second electrode L1b (second electrode) of the capacitive element C1 and the first electrode L2a (third electrode) of the capacitive element C2. Therefore, also in this case, the unevenness in the capacitive elements C1 and C2 can be reduced.

  (5) Further, for example, the conductivity type of each transistor constituting the pixel circuit 400 is appropriately changed. For example, the drive transistor Tdr in FIG. 2 may be an n-channel type. Also in this case, the potential Vdd supplied to the power supply line 31 is set to a potential that turns on the drive transistor Tdr when supplied to the gate of the drive transistor Tdr.

  In the above-described embodiment and modification, the surface of a substrate such as the glass substrate 701 may be covered with a protective film. Even in the case where the protective film is located on the surface of the substrate, in this specification, the protective film and the underlying substrate are included and referred to as “substrate”.

<E: Application example>
Next, an electronic apparatus using the electro-optical device 1 will be described. FIG. 14 is a perspective view showing the configuration of a mobile personal computer that employs the electro-optical device 1 according to any one of the embodiments described above as a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device 1 uses an OLED element as an electro-optical element, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 15 shows a configuration of a mobile phone to which the electro-optical device 1 according to the embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1 as a display device. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

  FIG. 16 illustrates a configuration of a personal digital assistant (PDA) to which the electro-optical device 1 according to the embodiment is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 1 as a display device. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.

  The electronic apparatus to which the electro-optical device is applied includes, in addition to those shown in FIGS. 14 to 16, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, a calculator, a word processor, Examples include workstations, videophones, POS terminals, printers, scanners, copiers, video players, and devices equipped with touch panels. The use of the electro-optical device is not limited to image display. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. However, the electro-optical device is used. Here, the electronic circuit is a concept including not only a pixel circuit constituting a pixel of the display device as in each embodiment but also a circuit that is a unit of exposure in the image forming apparatus.

  DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 11, 12, 13, 14 ... Control line, 31 ... Power supply line, 32 ... Ground line, 33 ... Initialization power supply line, 100 ... Scanning line drive circuit, 103 ... Data line, 200 ... Data Line driver circuit, 400 ... pixel circuit, 420 ... OLED element, 500 ... power supply circuit, A ... pixel region, Tdr ... drive transistor, Tr4 ... light emission control transistor, Tr1, Tr2, Tr3 ... transistor, Sc1, Sc2, Sc3, Sc4 …Control signal.

Claims (10)

A plurality of scanning lines including a first scanning line;
A plurality of data lines including a first data line;
A plurality of unit circuits including a first unit circuit provided in accordance with intersections of the plurality of scanning lines and the plurality of data lines;
Power supply line for supplying power supply voltage,
The first unit circuit includes:
A driving transistor that sets a driving current according to the voltage of the gate;
An electro-optic element driven by the drive current;
A first capacitive element comprising a first electrode and a second electrode;
A first switching element that controls electrical connection between the first data line and the second electrode based on a control signal supplied via the first scan line;
A second capacitive element comprising a third electrode and a fourth electrode,
The driving transistor has a first terminal and a second terminal, and the first terminal is connected to the power line;
The first electrode is connected to the gate;
The third electrode is connected to the gate or the second electrode;
In the first unit circuit, at least a part of the second capacitor element is disposed between the first data line and the first capacitor element.
An electro-optical device. A potential line for supplying a predetermined potential;
The plurality of data lines include a second data line,
The potential line is provided in a direction in which the first data line and the second data line extend,
The first capacitive element is disposed between the second capacitive element and the potential line between the first data line and the second data line.
The electro-optical device according to claim 1. The plurality of data lines include a second data line,
Between the first data line and the second data line, the first capacitor element is disposed between a region where the electro-optic element is disposed and the second capacitor element.
The electro-optical device according to claim 1. Below the region where the electro-optic element is disposed, at least a part of the first capacitor element or the second capacitor element is disposed.
The electro-optical device according to claim 1, wherein the electro-optical device is provided. The third electrode is connected to the second electrode;
The first unit circuit includes:
A semiconductor pattern layer including a first semiconductor film of the driving transistor, the first electrode, and the fourth electrode;
An insulating layer covering the semiconductor pattern layer;
A wiring pattern layer including the second electrode and the third electrode provided on the insulating layer,
The second electrode and the third electrode are composed of a common film,
The fourth electrode is provided between the first data line and the first electrode,
The fourth electrode is electrically connected to the power line;
The electro-optical device according to claim 1, wherein the electro-optical device is provided. The third electrode is connected to the gate;
The first unit circuit includes:
A semiconductor pattern layer including the first semiconductor film of the driving transistor, the first electrode, and the third electrode;
An insulating layer covering the semiconductor pattern layer;
A wiring pattern layer including the second electrode and the fourth electrode provided on the insulating layer,
The first electrode and the third electrode are composed of a second semiconductor film provided in common.
The electro-optical device according to claim 1, wherein the electro-optical device is provided. The third electrode is connected to the gate;
The first unit circuit includes:
A semiconductor pattern layer including the first semiconductor film of the driving transistor, the second electrode, and the fourth electrode;
An insulating layer covering the semiconductor pattern layer;
A wiring pattern layer including the first electrode and the third electrode provided on the insulating layer,
The first electrode and the third electrode are composed of a common film,
The electro-optical device according to claim 1, wherein the electro-optical device is provided. The third electrode is connected to the second electrode;
The first unit circuit includes:
A semiconductor pattern layer including the first semiconductor film of the driving transistor, the second electrode, and the third electrode;
An insulating layer covering the semiconductor pattern layer;
A wiring pattern layer including the first electrode and the fourth electrode provided on the insulating layer,
The second electrode and the third electrode are composed of a common film,
The electro-optical device according to claim 1, wherein the electro-optical device is provided. A plurality of scanning lines including a first scanning line;
A plurality of data lines including a first data line;
A plurality of unit circuits including a first unit circuit provided in accordance with intersections of the plurality of scanning lines and the plurality of data lines;
A power supply line for supplying power supply voltage;
A potential line for supplying a predetermined potential,
The first unit circuit includes:
A driving transistor that sets a driving current according to the voltage of the gate;
An electro-optic element driven by the drive current;
A first capacitive element comprising a first electrode and a second electrode;
A second capacitive element comprising a third electrode and a fourth electrode;
A first switching element that controls electrical connection between the first data line and the second electrode based on a control signal supplied via the first scan line;
A second switching element;
A third switching element that controls electrical connection between the first electrode and the potential line;
The driving transistor has a first terminal and a second terminal, and the first terminal is connected to the power line;
The first electrode is connected to the gate;
The third electrode is connected to the gate or the second electrode;
The second switching element controls an electrical connection between the second terminal and the gate;
In the first unit circuit, at least a part of the second capacitor element is disposed between the first data line and the first capacitor element.
An electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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